getMinVectorRegisterBitWidth means what vector types is supported in
this target, and actually RISC-V support all fixed length vector types with
vector length less than getMinRVVVectorSizeInBits, so set it to 16,
means 2 x i8, that is minimal fixed length vector size in theory.
That also fixed one issue, some testcase migth become non-vectorizable
when -riscv-v-vector-bits-min set to larger value, because the vector size is
smaller than -riscv-v-vector-bits-min.
For example, following code can vectorize by SLP with
-riscv-v-vector-bits-min=128 or -riscv-v-vector-bits-min=256, but
can't vectorize -riscv-v-vector-bits-min=512 or larger:
void foo(double *da) {
da[0] = 0;
da[1] = 1;
da[2] = 2;
da[3] = 3;
}