[RISCV] Remove FCSR from RISCVRegisterInfo.

[craig.topper]

Summary

We only used this to mark it as a reserved register. But that's not
important if we don't do anything else with it.

I think if we were ever to do anything with it, we would need to
model it as a super register of FRM and FFLAGS. But it might be
easier to reference both FRM and FFLAGS in implicit defs/uses
for anything we were to do with "fcsr".

[sepavloff]

Using fflags and frm separately is almost always more convenient than fcsr. The exception is probably the implementation of functions fegetenv and fesetenv, but in that case using both fflags and frm also works.

LGTM

llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp

BitVector RISCVRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
   markSuperRegs(Reserved, RISCV::VL);
   markSuperRegs(Reserved, RISCV::VTYPE);
   markSuperRegs(Reserved, RISCV::VXSAT);
   markSuperRegs(Reserved, RISCV::VXRM);
 
   // Floating point environment registers.
   markSuperRegs(Reserved, RISCV::FRM);
   markSuperRegs(Reserved, RISCV::FFLAGS);
-  markSuperRegs(Reserved, RISCV::FCSR);
 
   assert(checkAllSuperRegsMarked(Reserved));
   return Reserved;
 }
 
 bool RISCVRegisterInfo::isAsmClobberable(const MachineFunction &MF,
                                          MCRegister PhysReg) const {
   return !MF.getSubtarget<RISCVSubtarget>().isRegisterReservedByUser(PhysReg);

llvm/lib/Target/RISCV/RISCVRegisterInfo.td

def "VRN" # nf # "M" # m: VReg<[untyped],
                                     !cast<RegisterTuples>("VN" # nf # "M" # m # "V0")),
                                     !mul(nf, m)>;
   }
 }
 
 // Special registers
 def FFLAGS : RISCVReg<0, "fflags">;
 def FRM    : RISCVReg<0, "frm">;
-def FCSR   : RISCVReg<0, "fcsr">;
 
 // Any type register. Used for .insn directives when we don't know what the
 // register types could be.
 // NOTE: The alignment and size are bogus values. The Size needs to be non-zero
 // or tablegen will use "untyped" to determine the size which will assert.
 let isAllocatable = 0 in
 def AnyReg : RegisterClass<"RISCV", [untyped], 32,
                            (add (sequence "X%u", 0, 31),
                                 (sequence "F%u_D", 0, 31),
                                 (sequence "V%u", 0, 31))> {
   let Size = 32;
 }