This is an archive of the discontinued LLVM Phabricator instance.

Differential D113959

[llvm][RISC-V] Use floating-point ABI by default if possible
Needs ReviewPublic

Authored by occheung on Nov 15 2021, 5:45 PM.

Details

Reviewers
asb
Summary

This patch makes changes to the default ABI for RISC-V targets.

Before patch, only integer ABI (ilp32e, ilp32, lp64) can be selected by default (without passing ABIName in MCOptions).
After patch, ilp32f/d and lp64f/d can be selected if F/D extensions are detected.

Tests are updated by adding specifying target-abi if necessary.

Diff Detail

Event Timeline

occheung created this revision.Nov 15 2021, 5:45 PM
Herald added subscribers: VincentWu, luke957, vkmr and 23 others. · View Herald TranscriptNov 15 2021, 5:45 PM
occheung requested review of this revision.Nov 15 2021, 5:45 PM
Herald added subscribers: llvm-commits, MaskRay. · View Herald TranscriptNov 15 2021, 5:45 PM
Harbormaster completed remote builds in B134403: Diff 387455.Nov 15 2021, 5:46 PM
jrtc27 added a comment.Nov 15 2021, 5:49 PM

I believe this is the consensus in https://github.com/riscv-non-isa/riscv-toolchain-conventions/issues/13 (which should be linked to). Do you know if GCC is doing the same? Because even if a certain default makes more sense than another, it's best to be consistent between toolchains to avoid surprises.

craig.topper added a subscriber: craig.topper.Nov 15 2021, 5:53 PM
In D113959#3133522, @jrtc27 wrote:

I believe this is the consensus in https://github.com/riscv-non-isa/riscv-toolchain-conventions/issues/13 (which should be linked to). Do you know if GCC is doing the same? Because even if a certain default makes more sense than another, it's best to be consistent between toolchains to avoid surprises.

Isn't clang behavior determined by riscv::getRISCVABI in clang/lib/Driver/ToolChains/Arch/RISCV.cpp rather than this code?

jrtc27 added a comment.Nov 15 2021, 5:55 PM

All the preparatory changes to the RUN lines should probably be committed separately from the functional change. How did you update the tests; did you search for all that enabled f and d, or did you just look for ones that failed? Just wondering if there's any subtlety there about tests that appear to be unchanged but end up following slightly different code paths from what they intend to test.

llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp
37

I'd put these two declarations the other way round so they match the canonical order; only the uses need to be in "reverse" order to ensure we check from most to least specific.

61

This comment isn't really correct any more, even with your added sentence; clearly you can't use an lp64 ABI on rv32, the whole point of it was stating that a soft-float ABI is the default.

jrtc27 added a comment.Nov 15 2021, 5:58 PM
In D113959#3133525, @craig.topper wrote:
In D113959#3133522, @jrtc27 wrote:

I believe this is the consensus in https://github.com/riscv-non-isa/riscv-toolchain-conventions/issues/13 (which should be linked to). Do you know if GCC is doing the same? Because even if a certain default makes more sense than another, it's best to be consistent between toolchains to avoid surprises.

Isn't clang behavior determined by riscv::getRISCVABI in clang/lib/Driver/ToolChains/Arch/RISCV.cpp rather than this code?

Oh, indeed, that's still separate. I'm in two minds as to whether llc should default to soft-float or base it on the attributes (ignoring the F-without-D default for now). Being consistent with clang has its benefits, but normally you want llc to be simple and not have it start changing behaviour in other ways when you just add an attribute...

occheung added a comment.Nov 15 2021, 6:01 PM
In D113959#3133528, @jrtc27 wrote:

How did you update the tests; did you search for all that enabled f and d, or did you just look for ones that failed? Just wondering if there's any subtlety there about tests that appear to be unchanged but end up following slightly different code paths from what they intend to test.

I looked for the ones that failed without specifying abi and then added the -target-abi ilp32 / lp64 argument.
Regardless of what the intended test were, llc will use ilp32/lp64 as default abi before patch, so I don't think setting -target-abi as that intended default values (before patch) actually changed the test.

jrtc27 added a comment.Nov 15 2021, 6:08 PM
In D113959#3133540, @occheung wrote:
In D113959#3133528, @jrtc27 wrote:

How did you update the tests; did you search for all that enabled f and d, or did you just look for ones that failed? Just wondering if there's any subtlety there about tests that appear to be unchanged but end up following slightly different code paths from what they intend to test.

I looked for the ones that failed without specifying abi and then added the -target-abi ilp32 / lp64 argument.
Regardless of what the intended test were, llc will use ilp32/lp64 as default abi before patch, so I don't think setting -target-abi as that intended default values (before patch) actually changed the test.

That's not what I'm concerned about; clearly those have no change in behaviour. It's the ones that _still_ use the computed default ABI that may now have changed for them but happen to not change the output; just because the output is the same doesn't mean the test is still testing the same thing. It's probably fine, but I'm just raising it as a potential concern to think about.

occheung updated this revision to Diff 387462.Nov 15 2021, 6:11 PM

Rebased to d7a8135.
I am unsure why the patching failed in the first place.

occheung updated this revision to Diff 387470.Nov 15 2021, 6:41 PM

Declared IsRVF before IsRVD.
Removed invalid ABI comment.

occheung updated this revision to Diff 387480.Nov 15 2021, 7:23 PM

Removed the unnecessarily added -target-abi ilp32/lp64 when neither F nor D extensions were included. (e.g. loop unroll test in the Transform subdirectory)

Harbormaster completed remote builds in B134417: Diff 387480.Nov 15 2021, 8:05 PM
occheung updated this revision to Diff 387485.Nov 15 2021, 8:20 PM

Fix failed tests.

Harbormaster completed remote builds in B134422: Diff 387485.Nov 15 2021, 9:00 PM
asb added a comment.Nov 17 2021, 7:11 AM

I've got no real objection to changing the default, but I just wondered if the current default was causing a problem for you?

I'd considered the clang-side default as user-facing and pretty important, but would have thought the LLVM tool defaults were less important. Even then, I can see the logic in aligning with what Clang does.

occheung added a comment.Nov 17 2021, 6:37 PM
In D113959#3137632, @asb wrote:

I've got no real objection to changing the default, but I just wondered if the current default was causing a problem for you?

It becomes an issue when we attempt to write LLVM IR with other platforms (e.g. llvmlite, inkwell, etc).
These libraries may not expose the ABI argument to their API, so when compiling with RISC-V hard-float targets, it will use the default integer ABI (ilp32/lp64).
Some other languages based on LLVM (e.g. Rust) may have selected the float ABI by their default.
It will cause ABI conflict when we need to link libraries built with different platforms (e.g. link dynamic libraries built with llvmlite to a binary built with Rust).

Well technically making a patch to these platforms would solve the issue (as my PR in llvmlite), but we will eventually have to apply the same patch to every application that didn't/haven't sort out the ABI argument.

jrtc27 added a comment.Nov 17 2021, 6:39 PM

That's not a convincing argument to me. If they only support one RISC-V ABI they can jut hardcode it. If they support multiple then they can expose it however they like.

jrtc27 added a comment.Nov 17 2021, 6:40 PM

(In the same way that they'll already have a hard-coded list of target features; it's really not a huge imposition to require them to also set the ABI at the same time)

asb added a comment.Nov 18 2021, 2:03 AM

I think anyone producing LLVM IR for RISC-V should explicitly set the ABI and of course any target features (-mattr for llc). The default rv32/rv64 target of course isn't very useful - most cores implement at least some of the standard extensions.

I'd also be very wary of users depending on the default ABI selection.

So I agree with @jrtc27 here - if any LLVM IR producing frontends aren't explicitly setting the ABI or providing a way to do so, they really need to. You need to be aware of the target ABI when generating IR of course - many things will appear fine if you don't, but you'll run in to corner cases. See clang/lib/CodeGen/TargetInfo.cpp for how Clang handles this. It's come up many times in the LLVM community that it would be nice to avoid the need for this, but nobody has taken it on so far.

sbourdeauducq added a subscriber: sbourdeauducq.Nov 18 2021, 9:09 PM
In D113959#3139654, @asb wrote:

I'd also be very wary of users depending on the default ABI selection.

Fair enough, but you also said that you had no real objection to changing the default. In practice this would really save us a ton of trouble (because of Windows and frustrating issues with package managers). So, could you change the default anyway?

sbourdeauducq added a comment.Nov 18 2021, 9:20 PM

Also note that the LLVM C API, which many libraries use including inkwell/llvm-sys, does not expose the ABI settings. Getting the default right most of the time would, in practice, help with using LLVM.

jrtc27 added a comment.Nov 18 2021, 9:23 PM

If that’s the case then it needs to be extended. Changing the default is not a fix, it’s a bodge.

jrtc27 added a comment.Nov 18 2021, 9:24 PM

Nor do I see how Windows or package managers are relevant to a discussion about how software should use LLVM’s APIs for compiling RISC-V code.

sbourdeauducq added a comment.Nov 18 2021, 9:26 PM

Because modifying a stack of libraries is a pain when dealing with conda/cargo/Windows. Try it if you don't believe me.

jrtc27 added a comment.Dec 9 2021, 7:46 AM

FYI the llvmlite PR to set MCOptions.ABIName got merged.

I continue to believe that this should not be necessary from an LLVM API consumer perspective. Anything not setting the ABI is broken and should be fixed, and it's not our problem that they don't use our API properly or exist in an ecosystem that makes it difficult to patch them. If anything I would rather there be no default in the backend, only in the Clang frontend, but the main reason not to do that is it's annoying for writing tests where most don't care what floating-point ABI is in use.

sbourdeauducq added a comment.Dec 9 2021, 8:00 AM

Whatever. I figured out how to cross-compile LLVM for Windows with mingw-gcc, so you can continue your bike-shedding, this is not my problem anymore as I can ship my own build. And, going forward, I will not waste my time sending patches to LLVM since the lack of pragmatism here is just ridiculous. This patch does not degrade the code base in any way.

sbourdeauducq removed a subscriber: sbourdeauducq.Dec 9 2021, 8:01 AM
liaolucy added a subscriber: liaolucy.Dec 15 2021, 10:15 PM
jrtc27 mentioned this in D118333: [RISCV] Use computeTargetABI from llc as well as clang.Jan 27 2022, 6:00 AM

Revision Contents

PathSize
llvm/
lib/
Target/
RISCV/
MCTargetDesc/
18 lines
test/
CodeGen/
RISCV/
4 lines
4 lines
4 lines
2 lines
2 lines
4 lines
4 lines
4 lines
4 lines
2 lines
4 lines
4 lines
4 lines
4 lines
4 lines
2 lines
4 lines
4 lines
2 lines
4 lines
8 lines
8 lines
4 lines
4 lines
4 lines
4 lines
8 lines
4 lines
4 lines
4 lines
9 lines
4 lines
4 lines
2 lines
2 lines
rvv/
4 lines
4 lines
4 lines
2 lines
2 lines
2 lines
2 lines
2 lines
2 lines
2 lines
2 lines
2 lines
2 lines
2 lines
2 lines
2 lines
2 lines
2 lines
2 lines
2 lines
2 lines
2 lines
2 lines
2 lines
2 lines
2 lines
2 lines
2 lines
2 lines
2 lines
2 lines
2 lines
2 lines
2 lines
2 lines
2 lines
2 lines
2 lines
2 lines
2 lines
2 lines
2 lines
2 lines
2 lines
2 lines
2 lines
2 lines
2 lines
2 lines
2 lines
2 lines
2 lines
2 lines
2 lines
2 lines
2 lines
2 lines
2 lines
2 lines
2 lines
2 lines
2 lines
2 lines
2 lines
2 lines
2 lines
2 lines
2 lines
2 lines
2 lines
2 lines
2 lines
2 lines
2 lines
2 lines
2 lines
2 lines
2 lines
8 lines
8 lines
2 lines
2 lines
Transforms/
LoopVectorize/
RISCV/
4 lines

Diff 387455

llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp

Show All 27 Lines
} // namespace RISCVSysReg } // namespace RISCVSysReg
namespace RISCVABI { namespace RISCVABI {
ABI computeTargetABI(const Triple &TT, FeatureBitset FeatureBits, ABI computeTargetABI(const Triple &TT, FeatureBitset FeatureBits,
StringRef ABIName) { StringRef ABIName) {
auto TargetABI = getTargetABI(ABIName); auto TargetABI = getTargetABI(ABIName);
bool IsRV64 = TT.isArch64Bit(); bool IsRV64 = TT.isArch64Bit();
bool IsRV32E = FeatureBits[RISCV::FeatureRV32E]; bool IsRV32E = FeatureBits[RISCV::FeatureRV32E];
bool IsRVD = FeatureBits[RISCV::FeatureStdExtD];
bool IsRVF = FeatureBits[RISCV::FeatureStdExtF];
jrtc27Unsubmitted
Not Done
ReplyInline Actions

I'd put these two declarations the other way round so they match the canonical order; only the uses need to be in "reverse" order to ensure we check from most to least specific.

jrtc27: I'd put these two declarations the other way round so they match the canonical order; only the…
if (!ABIName.empty() && TargetABI == ABI_Unknown) { if (!ABIName.empty() && TargetABI == ABI_Unknown) {
errs() errs()
<< "'" << ABIName << "'" << ABIName
<< "' is not a recognized ABI for this target (ignoring target-abi)\n"; << "' is not a recognized ABI for this target (ignoring target-abi)\n";
} else if (ABIName.startswith("ilp32") && IsRV64) { } else if (ABIName.startswith("ilp32") && IsRV64) {
errs() << "32-bit ABIs are not supported for 64-bit targets (ignoring " errs() << "32-bit ABIs are not supported for 64-bit targets (ignoring "
"target-abi)\n"; "target-abi)\n";
TargetABI = ABI_Unknown; TargetABI = ABI_Unknown;
} else if (ABIName.startswith("lp64") && !IsRV64) { } else if (ABIName.startswith("lp64") && !IsRV64) {
errs() << "64-bit ABIs are not supported for 32-bit targets (ignoring " errs() << "64-bit ABIs are not supported for 32-bit targets (ignoring "
"target-abi)\n"; "target-abi)\n";
TargetABI = ABI_Unknown; TargetABI = ABI_Unknown;
} else if (IsRV32E && TargetABI != ABI_ILP32E && TargetABI != ABI_Unknown) { } else if (IsRV32E && TargetABI != ABI_ILP32E && TargetABI != ABI_Unknown) {
// TODO: move this checking to RISCVTargetLowering and RISCVAsmParser // TODO: move this checking to RISCVTargetLowering and RISCVAsmParser
errs() errs()
<< "Only the ilp32e ABI is supported for RV32E (ignoring target-abi)\n"; << "Only the ilp32e ABI is supported for RV32E (ignoring target-abi)\n";
TargetABI = ABI_Unknown; TargetABI = ABI_Unknown;
} }
if (TargetABI != ABI_Unknown) if (TargetABI != ABI_Unknown)
return TargetABI; return TargetABI;
// For now, default to the ilp32/ilp32e/lp64 ABI if no explicit ABI is given // For now, default to the ilp32/ilp32e/lp64 ABI if no explicit ABI is given
jrtc27Unsubmitted
Not Done
ReplyInline Actions

This comment isn't really correct any more, even with your added sentence; clearly you can't use an lp64 ABI on rv32, the whole point of it was stating that a soft-float ABI is the default.

jrtc27: This comment isn't really correct any more, even with your added sentence; clearly you can't…
// or an invalid/unrecognised string is given. In the future, it might be // or an invalid/unrecognised string is given.
// worth changing this to default to ilp32f/lp64f and ilp32d/lp64d when // If double/single float extensions are detected, use double/single float ABI
// hardware support for floating point is present.
if (IsRV32E) if (IsRV32E)
return ABI_ILP32E; return ABI_ILP32E;
if (IsRV64) if (IsRV64) {
if (IsRVD)
return ABI_LP64D;
if (IsRVF)
return ABI_LP64F;
return ABI_LP64; return ABI_LP64;
}
if (IsRVD)
return ABI_ILP32D;
if (IsRVF)
return ABI_ILP32F;
return ABI_ILP32; return ABI_ILP32;
} }
ABI getTargetABI(StringRef ABIName) { ABI getTargetABI(StringRef ABIName) {
auto TargetABI = StringSwitch<ABI>(ABIName) auto TargetABI = StringSwitch<ABI>(ABIName)
.Case("ilp32", ABI_ILP32) .Case("ilp32", ABI_ILP32)
.Case("ilp32f", ABI_ILP32F) .Case("ilp32f", ABI_ILP32F)
.Case("ilp32d", ABI_ILP32D) .Case("ilp32d", ABI_ILP32D)
▲ Show 20 Lines • Show All 105 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/callee-saved-fpr32s.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv32 -mattr=+f -target-abi ilp32 -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=ILP32 ; RUN: | FileCheck %s -check-prefix=ILP32
; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv64 -mattr=+f -target-abi lp64 -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=LP64 ; RUN: | FileCheck %s -check-prefix=LP64
; RUN: llc -mtriple=riscv32 -mattr=+f -target-abi ilp32f -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv32 -mattr=+f -target-abi ilp32f -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=ILP32F ; RUN: | FileCheck %s -check-prefix=ILP32F
; RUN: llc -mtriple=riscv64 -mattr=+f -target-abi lp64f -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv64 -mattr=+f -target-abi lp64f -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=LP64F ; RUN: | FileCheck %s -check-prefix=LP64F
; RUN: llc -mtriple=riscv32 -mattr=+d -target-abi ilp32d -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv32 -mattr=+d -target-abi ilp32d -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=ILP32D ; RUN: | FileCheck %s -check-prefix=ILP32D
; RUN: llc -mtriple=riscv64 -mattr=+d -target-abi lp64d -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv64 -mattr=+d -target-abi lp64d -verify-machineinstrs < %s \
▲ Show 20 Lines • Show All 1,409 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/callee-saved-fpr64s.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+d -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv32 -mattr=+d -target-abi ilp32 -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=ILP32 ; RUN: | FileCheck %s -check-prefix=ILP32
; RUN: llc -mtriple=riscv64 -mattr=+d -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv64 -mattr=+d -target-abi lp64 -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=LP64 ; RUN: | FileCheck %s -check-prefix=LP64
; RUN: llc -mtriple=riscv32 -mattr=+d -target-abi ilp32d -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv32 -mattr=+d -target-abi ilp32d -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=ILP32D ; RUN: | FileCheck %s -check-prefix=ILP32D
; RUN: llc -mtriple=riscv64 -mattr=+d -target-abi lp64d -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv64 -mattr=+d -target-abi lp64d -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=LP64D ; RUN: | FileCheck %s -check-prefix=LP64D
@var = global [32 x double] zeroinitializer @var = global [32 x double] zeroinitializer
▲ Show 20 Lines • Show All 927 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/calling-conv-half.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s | FileCheck %s -check-prefix=RV32I ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s | FileCheck %s -check-prefix=RV32I
; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s | FileCheck %s -check-prefix=RV64I ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s | FileCheck %s -check-prefix=RV64I
; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s | FileCheck %s -check-prefix=RV32IF ; RUN: llc -mtriple=riscv32 -mattr=+f -target-abi=ilp32 -verify-machineinstrs < %s | FileCheck %s -check-prefix=RV32IF
; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s | FileCheck %s -check-prefix=RV64IF ; RUN: llc -mtriple=riscv64 -mattr=+f -target-abi=lp64 -verify-machineinstrs < %s | FileCheck %s -check-prefix=RV64IF
; RUN: llc -mtriple=riscv32 -mattr=+f -target-abi=ilp32f -verify-machineinstrs < %s | FileCheck %s -check-prefix=RV32-ILP32F ; RUN: llc -mtriple=riscv32 -mattr=+f -target-abi=ilp32f -verify-machineinstrs < %s | FileCheck %s -check-prefix=RV32-ILP32F
; RUN: llc -mtriple=riscv64 -mattr=+f -target-abi=lp64f -verify-machineinstrs < %s | FileCheck %s -check-prefix=RV64-LP64F ; RUN: llc -mtriple=riscv64 -mattr=+f -target-abi=lp64f -verify-machineinstrs < %s | FileCheck %s -check-prefix=RV64-LP64F
; Tests passing half arguments and returns without Zfh. ; Tests passing half arguments and returns without Zfh.
; Covers with and without F extension and ilp32f/ilp64f ; Covers with and without F extension and ilp32f/ilp64f
; calling conventions. ; calling conventions.
define i32 @callee_half_in_regs(i32 %a, half %b) nounwind { define i32 @callee_half_in_regs(i32 %a, half %b) nounwind {
▲ Show 20 Lines • Show All 513 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/calling-conv-rv32f-ilp32.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv32 -mattr=+f -target-abi ilp32 -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV32IF ; RUN: | FileCheck %s -check-prefix=RV32IF
; Exercises the ILP32 calling convention code in the case that f32 is a legal ; Exercises the ILP32 calling convention code in the case that f32 is a legal
; type. As well as testing that lowering is correct, these tests also aim to ; type. As well as testing that lowering is correct, these tests also aim to
; check that floating point load/store or integer load/store is chosen ; check that floating point load/store or integer load/store is chosen
; optimally when floats are passed on the stack. ; optimally when floats are passed on the stack.
define float @onstack_f32_noop(i64 %a, i64 %b, i64 %c, i64 %d, float %e, float %f) nounwind { define float @onstack_f32_noop(i64 %a, i64 %b, i64 %c, i64 %d, float %e, float %f) nounwind {
▲ Show 20 Lines • Show All 71 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/calling-conv-vector-float.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv64 -mattr=+f -target-abi=lp64 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64 %s ; RUN: | FileCheck -check-prefix=RV64 %s
; RUN: llc -mtriple=riscv64 -mattr=+f -target-abi=lp64f -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv64 -mattr=+f -target-abi=lp64f -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64LP64F %s ; RUN: | FileCheck -check-prefix=RV64LP64F %s
define <2 x float> @callee_v2f32(<2 x float> %x, <2 x float> %y) { define <2 x float> @callee_v2f32(<2 x float> %x, <2 x float> %y) {
; RV64-LABEL: callee_v2f32: ; RV64-LABEL: callee_v2f32:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: fmv.w.x ft0, a2 ; RV64-NEXT: fmv.w.x ft0, a2
▲ Show 20 Lines • Show All 53 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/codemodel-lowering.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+f -code-model=small -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv32 -mattr=+f -target-abi ilp32 -code-model=small -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV32I-SMALL ; RUN: | FileCheck %s -check-prefix=RV32I-SMALL
; RUN: llc -mtriple=riscv32 -mattr=+f -code-model=medium -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv32 -mattr=+f -target-abi ilp32 -code-model=medium -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV32I-MEDIUM ; RUN: | FileCheck %s -check-prefix=RV32I-MEDIUM
; Check lowering of globals ; Check lowering of globals
@G = global i32 0 @G = global i32 0
define i32 @lower_global(i32 %a) nounwind { define i32 @lower_global(i32 %a) nounwind {
; RV32I-SMALL-LABEL: lower_global: ; RV32I-SMALL-LABEL: lower_global:
; RV32I-SMALL: # %bb.0: ; RV32I-SMALL: # %bb.0:
▲ Show 20 Lines • Show All 137 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/double-arith.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+d -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv32 -mattr=+d -target-abi ilp32 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32IFD %s ; RUN: | FileCheck -check-prefix=RV32IFD %s
; RUN: llc -mtriple=riscv64 -mattr=+d -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv64 -mattr=+d -target-abi lp64 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64IFD %s ; RUN: | FileCheck -check-prefix=RV64IFD %s
; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32I %s ; RUN: | FileCheck -check-prefix=RV32I %s
; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64I %s ; RUN: | FileCheck -check-prefix=RV64I %s
; These tests are each targeted at a particular RISC-V FPU instruction. Most ; These tests are each targeted at a particular RISC-V FPU instruction. Most
; other files in this folder exercise LLVM IR instructions that don't directly ; other files in this folder exercise LLVM IR instructions that don't directly
▲ Show 20 Lines • Show All 1,666 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/double-bitmanip-dagcombines.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32I %s ; RUN: | FileCheck -check-prefix=RV32I %s
; RUN: llc -mtriple=riscv32 -mattr=+d -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv32 -mattr=+d -target-abi ilp32 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32IFD %s ; RUN: | FileCheck -check-prefix=RV32IFD %s
; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64I %s ; RUN: | FileCheck -check-prefix=RV64I %s
; RUN: llc -mtriple=riscv64 -mattr=+d -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv64 -mattr=+d -target-abi lp64 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64IFD %s ; RUN: | FileCheck -check-prefix=RV64IFD %s
; ;
; This file tests cases where simple floating point operations can be ; This file tests cases where simple floating point operations can be
; profitably handled though bit manipulation if a soft-float ABI is being used ; profitably handled though bit manipulation if a soft-float ABI is being used
; (e.g. fneg implemented by XORing the sign bit). This is typically handled in ; (e.g. fneg implemented by XORing the sign bit). This is typically handled in
; DAGCombiner::visitBITCAST, but this target-independent code may not trigger ; DAGCombiner::visitBITCAST, but this target-independent code may not trigger
; in cases where we perform custom legalisation (e.g. RV32IFD). ; in cases where we perform custom legalisation (e.g. RV32IFD).
▲ Show 20 Lines • Show All 125 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/double-br-fcmp.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+d -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv32 -mattr=+d -target-abi ilp32 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32IFD %s ; RUN: | FileCheck -check-prefix=RV32IFD %s
; RUN: llc -mtriple=riscv64 -mattr=+d -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv64 -mattr=+d -target-abi lp64 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64IFD %s ; RUN: | FileCheck -check-prefix=RV64IFD %s
declare void @abort() declare void @abort()
declare void @exit(i32) declare void @exit(i32)
define void @br_fcmp_false(double %a, double %b) nounwind { define void @br_fcmp_false(double %a, double %b) nounwind {
; RV32IFD-LABEL: br_fcmp_false: ; RV32IFD-LABEL: br_fcmp_false:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
▲ Show 20 Lines • Show All 693 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/double-calling-conv.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+d -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv32 -mattr=+d -target-abi ilp32 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32IFD %s ; RUN: | FileCheck -check-prefix=RV32IFD %s
; Sanity checks for calling convention lowering for RV32D. This can be ; Sanity checks for calling convention lowering for RV32D. This can be
; somewhat error-prone for soft-float RV32D due to the fact that f64 is legal ; somewhat error-prone for soft-float RV32D due to the fact that f64 is legal
; but i64 is not, and there is no instruction to move values directly between ; but i64 is not, and there is no instruction to move values directly between
; the GPRs and 64-bit FPRs. ; the GPRs and 64-bit FPRs.
define double @callee_double_inreg(double %a, double %b) nounwind { define double @callee_double_inreg(double %a, double %b) nounwind {
▲ Show 20 Lines • Show All 134 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/double-convert.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+d -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv32 -mattr=+d -target-abi ilp32 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32IFD %s ; RUN: | FileCheck -check-prefix=RV32IFD %s
; RUN: llc -mtriple=riscv64 -mattr=+d -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv64 -mattr=+d -target-abi lp64 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64IFD %s ; RUN: | FileCheck -check-prefix=RV64IFD %s
; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32I %s ; RUN: | FileCheck -check-prefix=RV32I %s
; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64I %s ; RUN: | FileCheck -check-prefix=RV64I %s
define float @fcvt_s_d(double %a) nounwind { define float @fcvt_s_d(double %a) nounwind {
; RV32IFD-LABEL: fcvt_s_d: ; RV32IFD-LABEL: fcvt_s_d:
▲ Show 20 Lines • Show All 1,565 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/double-fcmp.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+d -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv32 -mattr=+d -target-abi ilp32 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32IFD %s ; RUN: | FileCheck -check-prefix=RV32IFD %s
; RUN: llc -mtriple=riscv64 -mattr=+d -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv64 -mattr=+d -target-abi lp64 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64IFD %s ; RUN: | FileCheck -check-prefix=RV64IFD %s
; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32I %s ; RUN: | FileCheck -check-prefix=RV32I %s
; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64I %s ; RUN: | FileCheck -check-prefix=RV64I %s
define i32 @fcmp_false(double %a, double %b) nounwind { define i32 @fcmp_false(double %a, double %b) nounwind {
; RV32IFD-LABEL: fcmp_false: ; RV32IFD-LABEL: fcmp_false:
▲ Show 20 Lines • Show All 779 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/double-imm.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+d -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv32 -mattr=+d -target-abi ilp32 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32IFD %s ; RUN: | FileCheck -check-prefix=RV32IFD %s
; RUN: llc -mtriple=riscv64 -mattr=+d -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv64 -mattr=+d -target-abi lp64 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64IFD %s ; RUN: | FileCheck -check-prefix=RV64IFD %s
define double @double_imm() nounwind { define double @double_imm() nounwind {
; TODO: Should probably prefer fld or ld on RV64 rather than materialising an ; TODO: Should probably prefer fld or ld on RV64 rather than materialising an
; expensive constant. ; expensive constant.
; ;
; RV32IFD-LABEL: double_imm: ; RV32IFD-LABEL: double_imm:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
▲ Show 20 Lines • Show All 47 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/double-intrinsics.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+d \ ; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+d -target-abi ilp32 \
; RUN: -verify-machineinstrs | FileCheck -check-prefix=RV32IFD %s ; RUN: -verify-machineinstrs | FileCheck -check-prefix=RV32IFD %s
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+d \ ; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+d -target-abi lp64 \
; RUN: -verify-machineinstrs | FileCheck -check-prefix=RV64IFD %s ; RUN: -verify-machineinstrs | FileCheck -check-prefix=RV64IFD %s
; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 \ ; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 \
; RUN: -verify-machineinstrs | FileCheck -check-prefix=RV32I %s ; RUN: -verify-machineinstrs | FileCheck -check-prefix=RV32I %s
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 \ ; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 \
; RUN: -verify-machineinstrs | FileCheck -check-prefix=RV64I %s ; RUN: -verify-machineinstrs | FileCheck -check-prefix=RV64I %s
declare double @llvm.sqrt.f64(double) declare double @llvm.sqrt.f64(double)
▲ Show 20 Lines • Show All 1,285 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/double-mem.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+d -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv32 -mattr=+d -target-abi ilp32 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32IFD %s ; RUN: | FileCheck -check-prefix=RV32IFD %s
; RUN: llc -mtriple=riscv64 -mattr=+d -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv64 -mattr=+d -target-abi lp64 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64IFD %s ; RUN: | FileCheck -check-prefix=RV64IFD %s
define dso_local double @fld(double *%a) nounwind { define dso_local double @fld(double *%a) nounwind {
; RV32IFD-LABEL: fld: ; RV32IFD-LABEL: fld:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi sp, sp, -16 ; RV32IFD-NEXT: addi sp, sp, -16
; RV32IFD-NEXT: fld ft0, 0(a0) ; RV32IFD-NEXT: fld ft0, 0(a0)
; RV32IFD-NEXT: fld ft1, 24(a0) ; RV32IFD-NEXT: fld ft1, 24(a0)
▲ Show 20 Lines • Show All 250 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/double-previous-failure.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+d -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv32 -mattr=+d -target-abi ilp32 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32IFD %s ; RUN: | FileCheck -check-prefix=RV32IFD %s
define double @test(double %a) nounwind { define double @test(double %a) nounwind {
; RV32IFD-LABEL: test: ; RV32IFD-LABEL: test:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
ret double %a ret double %a
} }
▲ Show 20 Lines • Show All 49 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/double-select-fcmp.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+d -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv32 -mattr=+d -target-abi ilp32 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32IFD %s ; RUN: | FileCheck -check-prefix=RV32IFD %s
; RUN: llc -mtriple=riscv64 -mattr=+d -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv64 -mattr=+d -target-abi lp64 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64IFD %s ; RUN: | FileCheck -check-prefix=RV64IFD %s
define double @select_fcmp_false(double %a, double %b) nounwind { define double @select_fcmp_false(double %a, double %b) nounwind {
; RV32IFD-LABEL: select_fcmp_false: ; RV32IFD-LABEL: select_fcmp_false:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
; RV32IFD-NEXT: mv a1, a3 ; RV32IFD-NEXT: mv a1, a3
; RV32IFD-NEXT: mv a0, a2 ; RV32IFD-NEXT: mv a0, a2
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
▲ Show 20 Lines • Show All 592 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/double-stack-spill-restore.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+d -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv32 -mattr=+d -target-abi ilp32 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32IFD %s ; RUN: | FileCheck -check-prefix=RV32IFD %s
; RUN: llc -mtriple=riscv64 -mattr=+d -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv64 -mattr=+d -target-abi lp64 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64IFD %s ; RUN: | FileCheck -check-prefix=RV64IFD %s
define double @func(double %d, i32 %n) nounwind { define double @func(double %d, i32 %n) nounwind {
; RV32IFD-LABEL: func: ; RV32IFD-LABEL: func:
; RV32IFD: # %bb.0: # %entry ; RV32IFD: # %bb.0: # %entry
; RV32IFD-NEXT: addi sp, sp, -32 ; RV32IFD-NEXT: addi sp, sp, -32
; RV32IFD-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32IFD-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32IFD-NEXT: sw a0, 16(sp) ; RV32IFD-NEXT: sw a0, 16(sp)
▲ Show 20 Lines • Show All 58 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/fastcc-float.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+f,+d -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv32 -mattr=+f,+d -target-abi ilp32 -verify-machineinstrs < %s \
; RUN: | FileCheck %s ; RUN: | FileCheck %s
define fastcc float @callee(<32 x float> %A) nounwind { define fastcc float @callee(<32 x float> %A) nounwind {
; CHECK-LABEL: callee: ; CHECK-LABEL: callee:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: fmv.x.w a0, fa0 ; CHECK-NEXT: fmv.x.w a0, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%B = extractelement <32 x float> %A, i32 0 %B = extractelement <32 x float> %A, i32 0
▲ Show 20 Lines • Show All 61 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/float-arith.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv32 -mattr=+f -target-abi ilp32 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32IF %s ; RUN: | FileCheck -check-prefix=RV32IF %s
; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv64 -mattr=+f -target-abi lp64 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64IF %s ; RUN: | FileCheck -check-prefix=RV64IF %s
; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32I %s ; RUN: | FileCheck -check-prefix=RV32I %s
; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64I %s ; RUN: | FileCheck -check-prefix=RV64I %s
; These tests are each targeted at a particular RISC-V FPU instruction. Most ; These tests are each targeted at a particular RISC-V FPU instruction. Most
; other files in this folder exercise LLVM IR instructions that don't directly ; other files in this folder exercise LLVM IR instructions that don't directly
▲ Show 20 Lines • Show All 1,356 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/float-bit-preserving-dagcombines.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv32 -mattr=+f -target-abi ilp32 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32F %s ; RUN: | FileCheck -check-prefix=RV32F %s
; RUN: llc -mtriple=riscv32 -mattr=+f,+d -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv32 -mattr=+f,+d -target-abi ilp32 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32FD %s ; RUN: | FileCheck -check-prefix=RV32FD %s
; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv64 -mattr=+f -target-abi lp64 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64F %s ; RUN: | FileCheck -check-prefix=RV64F %s
; RUN: llc -mtriple=riscv64 -mattr=+f,+d -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv64 -mattr=+f,+d -target-abi lp64 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64FD %s ; RUN: | FileCheck -check-prefix=RV64FD %s
; These functions perform extra work to ensure that `%a3` starts in a ; These functions perform extra work to ensure that `%a3` starts in a
; floating-point register, if the machine has them, and the result of ; floating-point register, if the machine has them, and the result of
; the bitwise operation is then needed in a floating-point register. ; the bitwise operation is then needed in a floating-point register.
; This should mean the optimisations will fire even if you're using the ; This should mean the optimisations will fire even if you're using the
; soft-float ABI on a machine with hardware floating-point support. ; soft-float ABI on a machine with hardware floating-point support.
▲ Show 20 Lines • Show All 373 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/float-bitmanip-dagcombines.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv32 -target-abi ilp32 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32I %s ; RUN: | FileCheck -check-prefix=RV32I %s
; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv32 -mattr=+f -target-abi ilp32 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32IF %s ; RUN: | FileCheck -check-prefix=RV32IF %s
; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv64 -target-abi lp64 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64I %s ; RUN: | FileCheck -check-prefix=RV64I %s
; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv64 -mattr=+f -target-abi lp64 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64IF %s ; RUN: | FileCheck -check-prefix=RV64IF %s
; This file tests cases where simple floating point operations can be ; This file tests cases where simple floating point operations can be
; profitably handled though bit manipulation if a soft-float ABI is being used ; profitably handled though bit manipulation if a soft-float ABI is being used
; (e.g. fneg implemented by XORing the sign bit). This is typically handled in ; (e.g. fneg implemented by XORing the sign bit). This is typically handled in
; DAGCombiner::visitBITCAST, but this target-independent code may not trigger ; DAGCombiner::visitBITCAST, but this target-independent code may not trigger
; in cases where we perform custom legalisation (e.g. RV64F). ; in cases where we perform custom legalisation (e.g. RV64F).
▲ Show 20 Lines • Show All 110 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/float-br-fcmp.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv32 -mattr=+f -target-abi ilp32 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32IF %s ; RUN: | FileCheck -check-prefix=RV32IF %s
; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv64 -mattr=+f -target-abi lp64 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64IF %s ; RUN: | FileCheck -check-prefix=RV64IF %s
declare void @abort() declare void @abort()
declare void @exit(i32) declare void @exit(i32)
declare float @dummy(float) declare float @dummy(float)
define void @br_fcmp_false(float %a, float %b) nounwind { define void @br_fcmp_false(float %a, float %b) nounwind {
; RV32IF-LABEL: br_fcmp_false: ; RV32IF-LABEL: br_fcmp_false:
▲ Show 20 Lines • Show All 685 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/float-convert.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv32 -mattr=+f -target-abi ilp32 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32IF %s ; RUN: | FileCheck -check-prefix=RV32IF %s
; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv64 -mattr=+f -target-abi lp64 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64IF %s ; RUN: | FileCheck -check-prefix=RV64IF %s
; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32I %s ; RUN: | FileCheck -check-prefix=RV32I %s
; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64I %s ; RUN: | FileCheck -check-prefix=RV64I %s
; For RV64F, fcvt.l.s is semantically equivalent to fcvt.w.s in this case ; For RV64F, fcvt.l.s is semantically equivalent to fcvt.w.s in this case
; because fptosi will produce poison if the result doesn't fit into an i32. ; because fptosi will produce poison if the result doesn't fit into an i32.
▲ Show 20 Lines • Show All 1,354 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/float-fcmp.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv32 -mattr=+f -target-abi ilp32 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32IF %s ; RUN: | FileCheck -check-prefix=RV32IF %s
; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv64 -mattr=+f -target-abi lp64 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64IF %s ; RUN: | FileCheck -check-prefix=RV64IF %s
; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32I %s ; RUN: | FileCheck -check-prefix=RV32I %s
; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64I %s ; RUN: | FileCheck -check-prefix=RV64I %s
define i32 @fcmp_false(float %a, float %b) nounwind { define i32 @fcmp_false(float %a, float %b) nounwind {
; RV32IF-LABEL: fcmp_false: ; RV32IF-LABEL: fcmp_false:
▲ Show 20 Lines • Show All 679 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/float-imm.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv32 -mattr=+f -target-abi ilp32 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32IF %s ; RUN: | FileCheck -check-prefix=RV32IF %s
; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv64 -mattr=+f -target-abi lp64 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64IF %s ; RUN: | FileCheck -check-prefix=RV64IF %s
; TODO: constant pool shouldn't be necessary for RV64IF. ; TODO: constant pool shouldn't be necessary for RV64IF.
define float @float_imm() nounwind { define float @float_imm() nounwind {
; RV32IF-LABEL: float_imm: ; RV32IF-LABEL: float_imm:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: lui a0, 263313 ; RV32IF-NEXT: lui a0, 263313
; RV32IF-NEXT: addi a0, a0, -37 ; RV32IF-NEXT: addi a0, a0, -37
Show All 32 Lines

llvm/test/CodeGen/RISCV/float-intrinsics.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+f \ ; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+f -target-abi ilp32 \
; RUN: -verify-machineinstrs | FileCheck -check-prefix=RV32IF %s ; RUN: -verify-machineinstrs | FileCheck -check-prefix=RV32IF %s
; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+d \ ; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+d -target-abi ilp32 \
; RUN: -verify-machineinstrs | FileCheck -check-prefix=RV32IF %s ; RUN: -verify-machineinstrs | FileCheck -check-prefix=RV32IF %s
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+f \ ; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+f -target-abi lp64 \
; RUN: -verify-machineinstrs | FileCheck -check-prefix=RV64IF %s ; RUN: -verify-machineinstrs | FileCheck -check-prefix=RV64IF %s
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+d \ ; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+d -target-abi lp64 \
; RUN: -verify-machineinstrs | FileCheck -check-prefix=RV64IF %s ; RUN: -verify-machineinstrs | FileCheck -check-prefix=RV64IF %s
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 \ ; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 \
; RUN: -verify-machineinstrs | FileCheck -check-prefix=RV64I %s ; RUN: -verify-machineinstrs | FileCheck -check-prefix=RV64I %s
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 \ ; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 \
; RUN: -verify-machineinstrs | FileCheck -check-prefix=RV64I %s ; RUN: -verify-machineinstrs | FileCheck -check-prefix=RV64I %s
declare float @llvm.sqrt.f32(float) declare float @llvm.sqrt.f32(float)
▲ Show 20 Lines • Show All 945 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/float-mem.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv32 -mattr=+f -target-abi ilp32 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32IF %s ; RUN: | FileCheck -check-prefix=RV32IF %s
; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv64 -mattr=+f -target-abi lp64 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64IF %s ; RUN: | FileCheck -check-prefix=RV64IF %s
define dso_local float @flw(float *%a) nounwind { define dso_local float @flw(float *%a) nounwind {
; RV32IF-LABEL: flw: ; RV32IF-LABEL: flw:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: flw ft0, 0(a0) ; RV32IF-NEXT: flw ft0, 0(a0)
; RV32IF-NEXT: flw ft1, 12(a0) ; RV32IF-NEXT: flw ft1, 12(a0)
; RV32IF-NEXT: fadd.s ft0, ft0, ft1 ; RV32IF-NEXT: fadd.s ft0, ft0, ft1
▲ Show 20 Lines • Show All 194 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/float-select-fcmp.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv32 -mattr=+f -target-abi ilp32 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32IF %s ; RUN: | FileCheck -check-prefix=RV32IF %s
; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv64 -mattr=+f -target-abi lp64 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64IF %s ; RUN: | FileCheck -check-prefix=RV64IF %s
define float @select_fcmp_false(float %a, float %b) nounwind { define float @select_fcmp_false(float %a, float %b) nounwind {
; RV32IF-LABEL: select_fcmp_false: ; RV32IF-LABEL: select_fcmp_false:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: mv a0, a1 ; RV32IF-NEXT: mv a0, a1
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; ;
▲ Show 20 Lines • Show All 473 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/fpenv.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s | FileCheck -check-prefix=RV32IF %s ; RUN: llc -mtriple=riscv32 -mattr=+f -target-abi ilp32 -verify-machineinstrs < %s | FileCheck -check-prefix=RV32IF %s
; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s | FileCheck -check-prefix=RV64IF %s ; RUN: llc -mtriple=riscv64 -mattr=+f -target-abi lp64 -verify-machineinstrs < %s | FileCheck -check-prefix=RV64IF %s
define i32 @func_01() { define i32 @func_01() {
; RV32IF-LABEL: func_01: ; RV32IF-LABEL: func_01:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: frrm a0 ; RV32IF-NEXT: frrm a0
; RV32IF-NEXT: slli a0, a0, 2 ; RV32IF-NEXT: slli a0, a0, 2
; RV32IF-NEXT: lui a1, 66 ; RV32IF-NEXT: lui a1, 66
; RV32IF-NEXT: addi a1, a1, 769 ; RV32IF-NEXT: addi a1, a1, 769
▲ Show 20 Lines • Show All 114 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/inline-asm-clobbers.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32I %s ; RUN: | FileCheck -check-prefix=RV32I %s
; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64I %s ; RUN: | FileCheck -check-prefix=RV64I %s
; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv32 -mattr=+f -target-abi ilp32 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32I %s ; RUN: | FileCheck -check-prefix=RV32I %s
; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv64 -mattr=+f -target-abi lp64 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64I %s ; RUN: | FileCheck -check-prefix=RV64I %s
; RUN: llc -mtriple=riscv32 -mattr=+d -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv32 -mattr=+d -target-abi ilp32 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32I %s ; RUN: | FileCheck -check-prefix=RV32I %s
; RUN: llc -mtriple=riscv64 -mattr=+d -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv64 -mattr=+d -target-abi lp64 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64I %s ; RUN: | FileCheck -check-prefix=RV64I %s
; RUN: llc -mtriple=riscv32 -mattr=+f -target-abi ilp32f -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv32 -mattr=+f -target-abi ilp32f -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32IF %s ; RUN: | FileCheck -check-prefix=RV32IF %s
; RUN: llc -mtriple=riscv64 -mattr=+f -target-abi lp64f -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv64 -mattr=+f -target-abi lp64f -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64IF %s ; RUN: | FileCheck -check-prefix=RV64IF %s
; RUN: llc -mtriple=riscv32 -mattr=+d -target-abi ilp32d -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv32 -mattr=+d -target-abi ilp32d -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32ID %s ; RUN: | FileCheck -check-prefix=RV32ID %s
; RUN: llc -mtriple=riscv64 -mattr=+d -target-abi lp64d -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv64 -mattr=+d -target-abi lp64d -verify-machineinstrs < %s \
▲ Show 20 Lines • Show All 42 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/inline-asm-d-constraint-f.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+d -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv32 -mattr=+d -target-abi ilp32 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32F %s ; RUN: | FileCheck -check-prefix=RV32F %s
; RUN: llc -mtriple=riscv64 -mattr=+d -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv64 -mattr=+d -target-abi lp64 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64F %s ; RUN: | FileCheck -check-prefix=RV64F %s
@gd = external global double @gd = external global double
define double @constraint_f_double(double %a) nounwind { define double @constraint_f_double(double %a) nounwind {
; RV32F-LABEL: constraint_f_double: ; RV32F-LABEL: constraint_f_double:
; RV32F: # %bb.0: ; RV32F: # %bb.0:
; RV32F-NEXT: addi sp, sp, -16 ; RV32F-NEXT: addi sp, sp, -16
▲ Show 20 Lines • Show All 61 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/inline-asm-f-constraint-f.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv32 -mattr=+f -target-abi ilp32 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32F %s ; RUN: | FileCheck -check-prefix=RV32F %s
; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv64 -mattr=+f -target-abi lp64 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64F %s ; RUN: | FileCheck -check-prefix=RV64F %s
@gf = external global float @gf = external global float
define float @constraint_f_float(float %a) nounwind { define float @constraint_f_float(float %a) nounwind {
; RV32F-LABEL: constraint_f_float: ; RV32F-LABEL: constraint_f_float:
; RV32F: # %bb.0: ; RV32F: # %bb.0:
; RV32F-NEXT: lui a1, %hi(gf) ; RV32F-NEXT: lui a1, %hi(gf)
▲ Show 20 Lines • Show All 49 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rv64d-double-convert.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -mattr=+d -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv64 -mattr=+d -target-abi lp64 -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV64ID ; RUN: | FileCheck %s -check-prefix=RV64ID
; This file exhaustively checks double<->i32 conversions. In general, ; This file exhaustively checks double<->i32 conversions. In general,
; fcvt.l[u].d can be selected instead of fcvt.w[u].d because poison is ; fcvt.l[u].d can be selected instead of fcvt.w[u].d because poison is
; generated for an fpto[s|u]i conversion if the result doesn't fit in the ; generated for an fpto[s|u]i conversion if the result doesn't fit in the
; target type. ; target type.
define i32 @aext_fptosi(double %a) nounwind { define i32 @aext_fptosi(double %a) nounwind {
▲ Show 20 Lines • Show All 120 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rv64f-float-convert.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv64 -mattr=+f -target-abi lp64 -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV64IF ; RUN: | FileCheck %s -check-prefix=RV64IF
; This file exhaustively checks float<->i32 conversions. In general, ; This file exhaustively checks float<->i32 conversions. In general,
; fcvt.l[u].s can be selected instead of fcvt.w[u].s because poison is ; fcvt.l[u].s can be selected instead of fcvt.w[u].s because poison is
; generated for an fpto[s|u]i conversion if the result doesn't fit in the ; generated for an fpto[s|u]i conversion if the result doesn't fit in the
; target type. ; target type.
define i32 @aext_fptosi(float %a) nounwind { define i32 @aext_fptosi(float %a) nounwind {
▲ Show 20 Lines • Show All 177 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/constant-folding.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -target-abi ilp32 -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s \
; RUN: | FileCheck %s --check-prefixes=CHECK,RV32 ; RUN: | FileCheck %s --check-prefixes=CHECK,RV32
; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -target-abi lp64 -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s \
; RUN: | FileCheck %s --check-prefixes=CHECK,RV64 ; RUN: | FileCheck %s --check-prefixes=CHECK,RV64
; These tests check that the scalable-vector version of this series of ; These tests check that the scalable-vector version of this series of
; instructions does not get into an infinite DAGCombine loop. This was ; instructions does not get into an infinite DAGCombine loop. This was
; originally exposing an infinite loop between an 'and' of two truncates being promoted ; originally exposing an infinite loop between an 'and' of two truncates being promoted
; to the larger value type, then that 'truncate' being split back up into an ; to the larger value type, then that 'truncate' being split back up into an
; 'and' of two truncates. ; 'and' of two truncates.
; This didn't happen in the fixed-length test because a truncate of the ; This didn't happen in the fixed-length test because a truncate of the
▲ Show 20 Lines • Show All 55 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-bitcast.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+d,+experimental-zfh,+experimental-v -verify-machineinstrs -riscv-v-vector-bits-min=128 < %s | FileCheck %s --check-prefixes=CHECK,RV32-FP ; RUN: llc -mtriple=riscv32 -mattr=+d,+experimental-zfh,+experimental-v -target-abi ilp32 -verify-machineinstrs -riscv-v-vector-bits-min=128 < %s | FileCheck %s --check-prefixes=CHECK,RV32-FP
; RUN: llc -mtriple=riscv64 -mattr=+d,+experimental-zfh,+experimental-v -verify-machineinstrs -riscv-v-vector-bits-min=128 < %s | FileCheck %s --check-prefixes=CHECK,RV64-FP ; RUN: llc -mtriple=riscv64 -mattr=+d,+experimental-zfh,+experimental-v -target-abi lp64 -verify-machineinstrs -riscv-v-vector-bits-min=128 < %s | FileCheck %s --check-prefixes=CHECK,RV64-FP
define i16 @bitcast_v1f16_i16(<1 x half> %a) { define i16 @bitcast_v1f16_i16(<1 x half> %a) {
; CHECK-LABEL: bitcast_v1f16_i16: ; CHECK-LABEL: bitcast_v1f16_i16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 0, e16, mf4, ta, mu ; CHECK-NEXT: vsetivli zero, 0, e16, mf4, ta, mu
; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%b = bitcast <1 x half> %a to i16 %b = bitcast <1 x half> %a to i16
▲ Show 20 Lines • Show All 514 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/select-sra.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefix=RV32 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -target-abi ilp32 -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefix=RV32
; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefix=RV64 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -target-abi lp64 -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefix=RV64
; This test checks a regression in the select-to-sra transform, which was ; This test checks a regression in the select-to-sra transform, which was
; asserting (without a precondition) when the vector constants implicitly ; asserting (without a precondition) when the vector constants implicitly
; truncated their inputs, as we do on RV64. ; truncated their inputs, as we do on RV64.
define <4 x i32> @vselect_of_consts(<4 x i1> %cc) { define <4 x i32> @vselect_of_consts(<4 x i1> %cc) {
; RV32-LABEL: vselect_of_consts: ; RV32-LABEL: vselect_of_consts:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: lui a0, 284280 ; RV32-NEXT: lui a0, 284280
Show All 21 Lines

llvm/test/CodeGen/RISCV/rvv/vfadd-rv32.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -target-abi ilp32 -verify-machineinstrs \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
declare <vscale x 1 x half> @llvm.riscv.vfadd.nxv1f16.nxv1f16( declare <vscale x 1 x half> @llvm.riscv.vfadd.nxv1f16.nxv1f16(
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
i32); i32);
define <vscale x 1 x half> @intrinsic_vfadd_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i32 %2) nounwind { define <vscale x 1 x half> @intrinsic_vfadd_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vfadd_vv_nxv1f16_nxv1f16_nxv1f16: ; CHECK-LABEL: intrinsic_vfadd_vv_nxv1f16_nxv1f16_nxv1f16:
▲ Show 20 Lines • Show All 1,407 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vfadd-rv64.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -mattr=+experimental-zfh \ ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -mattr=+experimental-zfh \
; RUN: -mattr=+d -verify-machineinstrs \ ; RUN: -mattr=+d -target-abi lp64 -verify-machineinstrs \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
declare <vscale x 1 x half> @llvm.riscv.vfadd.nxv1f16.nxv1f16( declare <vscale x 1 x half> @llvm.riscv.vfadd.nxv1f16.nxv1f16(
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
i64); i64);
define <vscale x 1 x half> @intrinsic_vfadd_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2) nounwind { define <vscale x 1 x half> @intrinsic_vfadd_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vfadd_vv_nxv1f16_nxv1f16_nxv1f16: ; CHECK-LABEL: intrinsic_vfadd_vv_nxv1f16_nxv1f16_nxv1f16:
▲ Show 20 Lines • Show All 1,375 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vfdiv-rv32.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -target-abi ilp32 -verify-machineinstrs \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
declare <vscale x 1 x half> @llvm.riscv.vfdiv.nxv1f16.nxv1f16( declare <vscale x 1 x half> @llvm.riscv.vfdiv.nxv1f16.nxv1f16(
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
i32); i32);
define <vscale x 1 x half> @intrinsic_vfdiv_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i32 %2) nounwind { define <vscale x 1 x half> @intrinsic_vfdiv_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vfdiv_vv_nxv1f16_nxv1f16_nxv1f16: ; CHECK-LABEL: intrinsic_vfdiv_vv_nxv1f16_nxv1f16_nxv1f16:
▲ Show 20 Lines • Show All 1,407 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vfdiv-rv64.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -target-abi lp64 -verify-machineinstrs \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
declare <vscale x 1 x half> @llvm.riscv.vfdiv.nxv1f16( declare <vscale x 1 x half> @llvm.riscv.vfdiv.nxv1f16(
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
i64); i64);
define <vscale x 1 x half> @intrinsic_vfdiv_vv_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2) nounwind { define <vscale x 1 x half> @intrinsic_vfdiv_vv_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vfdiv_vv_nxv1f16_nxv1f16: ; CHECK-LABEL: intrinsic_vfdiv_vv_nxv1f16_nxv1f16:
▲ Show 20 Lines • Show All 1,375 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vfmacc-rv32.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -target-abi ilp32 -verify-machineinstrs \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
declare <vscale x 1 x half> @llvm.riscv.vfmacc.nxv1f16.nxv1f16( declare <vscale x 1 x half> @llvm.riscv.vfmacc.nxv1f16.nxv1f16(
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
i32); i32);
define <vscale x 1 x half> @intrinsic_vfmacc_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i32 %3) nounwind { define <vscale x 1 x half> @intrinsic_vfmacc_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i32 %3) nounwind {
▲ Show 20 Lines • Show All 1,144 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vfmacc-rv64.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -target-abi lp64 -verify-machineinstrs \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
declare <vscale x 1 x half> @llvm.riscv.vfmacc.nxv1f16.nxv1f16( declare <vscale x 1 x half> @llvm.riscv.vfmacc.nxv1f16.nxv1f16(
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
i64); i64);
define <vscale x 1 x half> @intrinsic_vfmacc_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 %3) nounwind { define <vscale x 1 x half> @intrinsic_vfmacc_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 %3) nounwind {
▲ Show 20 Lines • Show All 1,120 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vfmadd-rv32.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -target-abi ilp32 -verify-machineinstrs \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
declare <vscale x 1 x half> @llvm.riscv.vfmadd.nxv1f16.nxv1f16( declare <vscale x 1 x half> @llvm.riscv.vfmadd.nxv1f16.nxv1f16(
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
i32); i32);
define <vscale x 1 x half> @intrinsic_vfmadd_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i32 %3) nounwind { define <vscale x 1 x half> @intrinsic_vfmadd_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i32 %3) nounwind {
▲ Show 20 Lines • Show All 1,144 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vfmadd-rv64.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -target-abi lp64 -verify-machineinstrs \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
declare <vscale x 1 x half> @llvm.riscv.vfmadd.nxv1f16.nxv1f16( declare <vscale x 1 x half> @llvm.riscv.vfmadd.nxv1f16.nxv1f16(
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
i64); i64);
define <vscale x 1 x half> @intrinsic_vfmadd_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 %3) nounwind { define <vscale x 1 x half> @intrinsic_vfmadd_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 %3) nounwind {
▲ Show 20 Lines • Show All 1,120 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vfmax-rv32.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -target-abi ilp32 -verify-machineinstrs \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
declare <vscale x 1 x half> @llvm.riscv.vfmax.nxv1f16.nxv1f16( declare <vscale x 1 x half> @llvm.riscv.vfmax.nxv1f16.nxv1f16(
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
i32); i32);
define <vscale x 1 x half> @intrinsic_vfmax_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i32 %2) nounwind { define <vscale x 1 x half> @intrinsic_vfmax_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vfmax_vv_nxv1f16_nxv1f16_nxv1f16: ; CHECK-LABEL: intrinsic_vfmax_vv_nxv1f16_nxv1f16_nxv1f16:
▲ Show 20 Lines • Show All 1,407 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vfmax-rv64.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -target-abi lp64 -verify-machineinstrs \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
declare <vscale x 1 x half> @llvm.riscv.vfmax.nxv1f16.nxv1f16( declare <vscale x 1 x half> @llvm.riscv.vfmax.nxv1f16.nxv1f16(
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
i64); i64);
define <vscale x 1 x half> @intrinsic_vfmax_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2) nounwind { define <vscale x 1 x half> @intrinsic_vfmax_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vfmax_vv_nxv1f16_nxv1f16_nxv1f16: ; CHECK-LABEL: intrinsic_vfmax_vv_nxv1f16_nxv1f16_nxv1f16:
▲ Show 20 Lines • Show All 1,375 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vfmerge-rv32.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -target-abi ilp32 -verify-machineinstrs \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
declare <vscale x 1 x half> @llvm.riscv.vfmerge.nxv1f16.nxv1f16( declare <vscale x 1 x half> @llvm.riscv.vfmerge.nxv1f16.nxv1f16(
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 1 x half> @intrinsic_vfmerge_vvm_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x i1> %2, i32 %3) nounwind { define <vscale x 1 x half> @intrinsic_vfmerge_vvm_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
▲ Show 20 Lines • Show All 923 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vfmerge-rv64.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -target-abi lp64 -verify-machineinstrs \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
declare <vscale x 1 x half> @llvm.riscv.vfmerge.nxv1f16.nxv1f16( declare <vscale x 1 x half> @llvm.riscv.vfmerge.nxv1f16.nxv1f16(
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 1 x half> @intrinsic_vfmerge_vvm_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x i1> %2, i64 %3) nounwind { define <vscale x 1 x half> @intrinsic_vfmerge_vvm_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
▲ Show 20 Lines • Show All 907 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vfmin-rv32.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -target-abi ilp32 -verify-machineinstrs \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
declare <vscale x 1 x half> @llvm.riscv.vfmin.nxv1f16.nxv1f16( declare <vscale x 1 x half> @llvm.riscv.vfmin.nxv1f16.nxv1f16(
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
i32); i32);
define <vscale x 1 x half> @intrinsic_vfmin_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i32 %2) nounwind { define <vscale x 1 x half> @intrinsic_vfmin_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vfmin_vv_nxv1f16_nxv1f16_nxv1f16: ; CHECK-LABEL: intrinsic_vfmin_vv_nxv1f16_nxv1f16_nxv1f16:
▲ Show 20 Lines • Show All 1,407 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vfmin-rv64.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -target-abi lp64 -verify-machineinstrs \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
declare <vscale x 1 x half> @llvm.riscv.vfmin.nxv1f16.nxv1f16( declare <vscale x 1 x half> @llvm.riscv.vfmin.nxv1f16.nxv1f16(
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
i64); i64);
define <vscale x 1 x half> @intrinsic_vfmin_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2) nounwind { define <vscale x 1 x half> @intrinsic_vfmin_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vfmin_vv_nxv1f16_nxv1f16_nxv1f16: ; CHECK-LABEL: intrinsic_vfmin_vv_nxv1f16_nxv1f16_nxv1f16:
▲ Show 20 Lines • Show All 1,375 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vfmsac-rv32.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -target-abi ilp32 -verify-machineinstrs \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
declare <vscale x 1 x half> @llvm.riscv.vfmsac.nxv1f16.nxv1f16( declare <vscale x 1 x half> @llvm.riscv.vfmsac.nxv1f16.nxv1f16(
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
i32); i32);
define <vscale x 1 x half> @intrinsic_vfmsac_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i32 %3) nounwind { define <vscale x 1 x half> @intrinsic_vfmsac_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i32 %3) nounwind {
▲ Show 20 Lines • Show All 1,144 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vfmsac-rv64.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -target-abi lp64 -verify-machineinstrs \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
declare <vscale x 1 x half> @llvm.riscv.vfmsac.nxv1f16.nxv1f16( declare <vscale x 1 x half> @llvm.riscv.vfmsac.nxv1f16.nxv1f16(
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
i64); i64);
define <vscale x 1 x half> @intrinsic_vfmsac_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 %3) nounwind { define <vscale x 1 x half> @intrinsic_vfmsac_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 %3) nounwind {
▲ Show 20 Lines • Show All 1,120 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vfmsub-rv32.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -target-abi ilp32 -verify-machineinstrs \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
declare <vscale x 1 x half> @llvm.riscv.vfmsub.nxv1f16.nxv1f16( declare <vscale x 1 x half> @llvm.riscv.vfmsub.nxv1f16.nxv1f16(
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
i32); i32);
define <vscale x 1 x half> @intrinsic_vfmsub_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i32 %3) nounwind { define <vscale x 1 x half> @intrinsic_vfmsub_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i32 %3) nounwind {
▲ Show 20 Lines • Show All 1,144 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vfmsub-rv64.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -target-abi lp64 -verify-machineinstrs \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
declare <vscale x 1 x half> @llvm.riscv.vfmsub.nxv1f16.nxv1f16( declare <vscale x 1 x half> @llvm.riscv.vfmsub.nxv1f16.nxv1f16(
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
i64); i64);
define <vscale x 1 x half> @intrinsic_vfmsub_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 %3) nounwind { define <vscale x 1 x half> @intrinsic_vfmsub_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 %3) nounwind {
▲ Show 20 Lines • Show All 1,120 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vfmul-rv32.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -target-abi ilp32 -verify-machineinstrs \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
declare <vscale x 1 x half> @llvm.riscv.vfmul.nxv1f16.nxv1f16( declare <vscale x 1 x half> @llvm.riscv.vfmul.nxv1f16.nxv1f16(
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
i32); i32);
define <vscale x 1 x half> @intrinsic_vfmul_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i32 %2) nounwind { define <vscale x 1 x half> @intrinsic_vfmul_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vfmul_vv_nxv1f16_nxv1f16_nxv1f16: ; CHECK-LABEL: intrinsic_vfmul_vv_nxv1f16_nxv1f16_nxv1f16:
▲ Show 20 Lines • Show All 1,407 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vfmul-rv64.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -target-abi lp64 -verify-machineinstrs \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
declare <vscale x 1 x half> @llvm.riscv.vfmul.nxv1f16( declare <vscale x 1 x half> @llvm.riscv.vfmul.nxv1f16(
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
i64); i64);
define <vscale x 1 x half> @intrinsic_vfmul_vv_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2) nounwind { define <vscale x 1 x half> @intrinsic_vfmul_vv_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vfmul_vv_nxv1f16_nxv1f16: ; CHECK-LABEL: intrinsic_vfmul_vv_nxv1f16_nxv1f16:
▲ Show 20 Lines • Show All 1,375 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vfnmacc-rv32.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -target-abi ilp32 -verify-machineinstrs \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
declare <vscale x 1 x half> @llvm.riscv.vfnmacc.nxv1f16.nxv1f16( declare <vscale x 1 x half> @llvm.riscv.vfnmacc.nxv1f16.nxv1f16(
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
i32); i32);
define <vscale x 1 x half> @intrinsic_vfnmacc_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i32 %3) nounwind { define <vscale x 1 x half> @intrinsic_vfnmacc_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i32 %3) nounwind {
▲ Show 20 Lines • Show All 1,144 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vfnmacc-rv64.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -target-abi lp64 -verify-machineinstrs \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
declare <vscale x 1 x half> @llvm.riscv.vfnmacc.nxv1f16.nxv1f16( declare <vscale x 1 x half> @llvm.riscv.vfnmacc.nxv1f16.nxv1f16(
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
i64); i64);
define <vscale x 1 x half> @intrinsic_vfnmacc_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 %3) nounwind { define <vscale x 1 x half> @intrinsic_vfnmacc_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 %3) nounwind {
▲ Show 20 Lines • Show All 1,120 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vfnmadd-rv32.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -target-abi ilp32 -verify-machineinstrs \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
declare <vscale x 1 x half> @llvm.riscv.vfnmadd.nxv1f16.nxv1f16( declare <vscale x 1 x half> @llvm.riscv.vfnmadd.nxv1f16.nxv1f16(
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
i32); i32);
define <vscale x 1 x half> @intrinsic_vfnmadd_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i32 %3) nounwind { define <vscale x 1 x half> @intrinsic_vfnmadd_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i32 %3) nounwind {
▲ Show 20 Lines • Show All 1,144 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vfnmadd-rv64.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -target-abi lp64 -verify-machineinstrs \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
declare <vscale x 1 x half> @llvm.riscv.vfnmadd.nxv1f16.nxv1f16( declare <vscale x 1 x half> @llvm.riscv.vfnmadd.nxv1f16.nxv1f16(
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
i64); i64);
define <vscale x 1 x half> @intrinsic_vfnmadd_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 %3) nounwind { define <vscale x 1 x half> @intrinsic_vfnmadd_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 %3) nounwind {
▲ Show 20 Lines • Show All 1,120 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vfnmsac-rv32.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -target-abi ilp32 -verify-machineinstrs \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
declare <vscale x 1 x half> @llvm.riscv.vfnmsac.nxv1f16.nxv1f16( declare <vscale x 1 x half> @llvm.riscv.vfnmsac.nxv1f16.nxv1f16(
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
i32); i32);
define <vscale x 1 x half> @intrinsic_vfnmsac_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i32 %3) nounwind { define <vscale x 1 x half> @intrinsic_vfnmsac_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i32 %3) nounwind {
▲ Show 20 Lines • Show All 1,144 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vfnmsac-rv64.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -target-abi lp64 -verify-machineinstrs \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
declare <vscale x 1 x half> @llvm.riscv.vfnmsac.nxv1f16.nxv1f16( declare <vscale x 1 x half> @llvm.riscv.vfnmsac.nxv1f16.nxv1f16(
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
i64); i64);
define <vscale x 1 x half> @intrinsic_vfnmsac_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 %3) nounwind { define <vscale x 1 x half> @intrinsic_vfnmsac_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 %3) nounwind {
▲ Show 20 Lines • Show All 1,120 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vfnmsub-rv32.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -target-abi ilp32 -verify-machineinstrs \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
declare <vscale x 1 x half> @llvm.riscv.vfnmsub.nxv1f16.nxv1f16( declare <vscale x 1 x half> @llvm.riscv.vfnmsub.nxv1f16.nxv1f16(
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
i32); i32);
define <vscale x 1 x half> @intrinsic_vfnmsub_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i32 %3) nounwind { define <vscale x 1 x half> @intrinsic_vfnmsub_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i32 %3) nounwind {
▲ Show 20 Lines • Show All 1,144 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vfnmsub-rv64.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -target-abi lp64 -verify-machineinstrs \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
declare <vscale x 1 x half> @llvm.riscv.vfnmsub.nxv1f16.nxv1f16( declare <vscale x 1 x half> @llvm.riscv.vfnmsub.nxv1f16.nxv1f16(
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
i64); i64);
define <vscale x 1 x half> @intrinsic_vfnmsub_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 %3) nounwind { define <vscale x 1 x half> @intrinsic_vfnmsub_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 %3) nounwind {
▲ Show 20 Lines • Show All 1,120 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vfrdiv-rv32.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -target-abi ilp32 -verify-machineinstrs \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
declare <vscale x 1 x half> @llvm.riscv.vfrdiv.nxv1f16.f16( declare <vscale x 1 x half> @llvm.riscv.vfrdiv.nxv1f16.f16(
<vscale x 1 x half>, <vscale x 1 x half>,
half, half,
i32); i32);
define <vscale x 1 x half> @intrinsic_vfrdiv_vf_nxv1f16_nxv1f16_f16(<vscale x 1 x half> %0, half %1, i32 %2) nounwind { define <vscale x 1 x half> @intrinsic_vfrdiv_vf_nxv1f16_nxv1f16_f16(<vscale x 1 x half> %0, half %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vfrdiv_vf_nxv1f16_nxv1f16_f16: ; CHECK-LABEL: intrinsic_vfrdiv_vf_nxv1f16_nxv1f16_f16:
▲ Show 20 Lines • Show All 729 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vfrdiv-rv64.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -target-abi lp64 -verify-machineinstrs \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
declare <vscale x 1 x half> @llvm.riscv.vfrdiv.nxv1f16.f16( declare <vscale x 1 x half> @llvm.riscv.vfrdiv.nxv1f16.f16(
<vscale x 1 x half>, <vscale x 1 x half>,
half, half,
i64); i64);
define <vscale x 1 x half> @intrinsic_vfrdiv_vf_nxv1f16_f16(<vscale x 1 x half> %0, half %1, i64 %2) nounwind { define <vscale x 1 x half> @intrinsic_vfrdiv_vf_nxv1f16_f16(<vscale x 1 x half> %0, half %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vfrdiv_vf_nxv1f16_f16: ; CHECK-LABEL: intrinsic_vfrdiv_vf_nxv1f16_f16:
▲ Show 20 Lines • Show All 697 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vfrsub-rv32.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -target-abi ilp32 -verify-machineinstrs \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
declare <vscale x 1 x half> @llvm.riscv.vfrsub.nxv1f16.f16( declare <vscale x 1 x half> @llvm.riscv.vfrsub.nxv1f16.f16(
<vscale x 1 x half>, <vscale x 1 x half>,
half, half,
i32); i32);
define <vscale x 1 x half> @intrinsic_vfrsub_vf_nxv1f16_nxv1f16_f16(<vscale x 1 x half> %0, half %1, i32 %2) nounwind { define <vscale x 1 x half> @intrinsic_vfrsub_vf_nxv1f16_nxv1f16_f16(<vscale x 1 x half> %0, half %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vfrsub_vf_nxv1f16_nxv1f16_f16: ; CHECK-LABEL: intrinsic_vfrsub_vf_nxv1f16_nxv1f16_f16:
▲ Show 20 Lines • Show All 729 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vfrsub-rv64.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -mattr=+experimental-zfh \ ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -mattr=+experimental-zfh \
; RUN: -mattr=+d -verify-machineinstrs \ ; RUN: -mattr=+d -target-abi lp64 -verify-machineinstrs \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
declare <vscale x 1 x half> @llvm.riscv.vfrsub.nxv1f16.f16( declare <vscale x 1 x half> @llvm.riscv.vfrsub.nxv1f16.f16(
<vscale x 1 x half>, <vscale x 1 x half>,
half, half,
i64); i64);
define <vscale x 1 x half> @intrinsic_vfrsub_vf_nxv1f16_nxv1f16_f16(<vscale x 1 x half> %0, half %1, i64 %2) nounwind { define <vscale x 1 x half> @intrinsic_vfrsub_vf_nxv1f16_nxv1f16_f16(<vscale x 1 x half> %0, half %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vfrsub_vf_nxv1f16_nxv1f16_f16: ; CHECK-LABEL: intrinsic_vfrsub_vf_nxv1f16_nxv1f16_f16:
▲ Show 20 Lines • Show All 697 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vfsgnj-rv32.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -target-abi ilp32 -verify-machineinstrs \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
declare <vscale x 1 x half> @llvm.riscv.vfsgnj.nxv1f16.nxv1f16( declare <vscale x 1 x half> @llvm.riscv.vfsgnj.nxv1f16.nxv1f16(
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
i32); i32);
define <vscale x 1 x half> @intrinsic_vfsgnj_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i32 %2) nounwind { define <vscale x 1 x half> @intrinsic_vfsgnj_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vfsgnj_vv_nxv1f16_nxv1f16_nxv1f16: ; CHECK-LABEL: intrinsic_vfsgnj_vv_nxv1f16_nxv1f16_nxv1f16:
▲ Show 20 Lines • Show All 1,407 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vfsgnj-rv64.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -target-abi lp64 -verify-machineinstrs \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
declare <vscale x 1 x half> @llvm.riscv.vfsgnj.nxv1f16( declare <vscale x 1 x half> @llvm.riscv.vfsgnj.nxv1f16(
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
i64); i64);
define <vscale x 1 x half> @intrinsic_vfsgnj_vv_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2) nounwind { define <vscale x 1 x half> @intrinsic_vfsgnj_vv_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vfsgnj_vv_nxv1f16_nxv1f16: ; CHECK-LABEL: intrinsic_vfsgnj_vv_nxv1f16_nxv1f16:
▲ Show 20 Lines • Show All 1,375 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vfsgnjn-rv32.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -target-abi ilp32 -verify-machineinstrs \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
declare <vscale x 1 x half> @llvm.riscv.vfsgnjn.nxv1f16.nxv1f16( declare <vscale x 1 x half> @llvm.riscv.vfsgnjn.nxv1f16.nxv1f16(
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
i32); i32);
define <vscale x 1 x half> @intrinsic_vfsgnjn_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i32 %2) nounwind { define <vscale x 1 x half> @intrinsic_vfsgnjn_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vfsgnjn_vv_nxv1f16_nxv1f16_nxv1f16: ; CHECK-LABEL: intrinsic_vfsgnjn_vv_nxv1f16_nxv1f16_nxv1f16:
▲ Show 20 Lines • Show All 1,407 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vfsgnjn-rv64.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -target-abi lp64 -verify-machineinstrs \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
declare <vscale x 1 x half> @llvm.riscv.vfsgnjn.nxv1f16( declare <vscale x 1 x half> @llvm.riscv.vfsgnjn.nxv1f16(
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
i64); i64);
define <vscale x 1 x half> @intrinsic_vfsgnjn_vv_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2) nounwind { define <vscale x 1 x half> @intrinsic_vfsgnjn_vv_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vfsgnjn_vv_nxv1f16_nxv1f16: ; CHECK-LABEL: intrinsic_vfsgnjn_vv_nxv1f16_nxv1f16:
▲ Show 20 Lines • Show All 1,375 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vfsgnjx-rv32.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -target-abi ilp32 -verify-machineinstrs \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
declare <vscale x 1 x half> @llvm.riscv.vfsgnjx.nxv1f16.nxv1f16( declare <vscale x 1 x half> @llvm.riscv.vfsgnjx.nxv1f16.nxv1f16(
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
i32); i32);
define <vscale x 1 x half> @intrinsic_vfsgnjx_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i32 %2) nounwind { define <vscale x 1 x half> @intrinsic_vfsgnjx_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vfsgnjx_vv_nxv1f16_nxv1f16_nxv1f16: ; CHECK-LABEL: intrinsic_vfsgnjx_vv_nxv1f16_nxv1f16_nxv1f16:
▲ Show 20 Lines • Show All 1,407 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vfsgnjx-rv64.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -target-abi lp64 -verify-machineinstrs \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
declare <vscale x 1 x half> @llvm.riscv.vfsgnjx.nxv1f16( declare <vscale x 1 x half> @llvm.riscv.vfsgnjx.nxv1f16(
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
i64); i64);
define <vscale x 1 x half> @intrinsic_vfsgnjx_vv_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2) nounwind { define <vscale x 1 x half> @intrinsic_vfsgnjx_vv_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vfsgnjx_vv_nxv1f16_nxv1f16: ; CHECK-LABEL: intrinsic_vfsgnjx_vv_nxv1f16_nxv1f16:
▲ Show 20 Lines • Show All 1,375 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vfslide1down-rv32.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -target-abi ilp32 -verify-machineinstrs \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
declare <vscale x 1 x half> @llvm.riscv.vfslide1down.nxv1f16.f16( declare <vscale x 1 x half> @llvm.riscv.vfslide1down.nxv1f16.f16(
<vscale x 1 x half>, <vscale x 1 x half>,
half, half,
i32); i32);
define <vscale x 1 x half> @intrinsic_vfslide1down_vf_nxv1f16_nxv1f16_f16(<vscale x 1 x half> %0, half %1, i32 %2) nounwind { define <vscale x 1 x half> @intrinsic_vfslide1down_vf_nxv1f16_nxv1f16_f16(<vscale x 1 x half> %0, half %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vfslide1down_vf_nxv1f16_nxv1f16_f16: ; CHECK-LABEL: intrinsic_vfslide1down_vf_nxv1f16_nxv1f16_f16:
▲ Show 20 Lines • Show All 729 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vfslide1down-rv64.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -target-abi lp64 -verify-machineinstrs \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
declare <vscale x 1 x half> @llvm.riscv.vfslide1down.nxv1f16.f16( declare <vscale x 1 x half> @llvm.riscv.vfslide1down.nxv1f16.f16(
<vscale x 1 x half>, <vscale x 1 x half>,
half, half,
i64); i64);
define <vscale x 1 x half> @intrinsic_vfslide1down_vf_nxv1f16_nxv1f16_f16(<vscale x 1 x half> %0, half %1, i64 %2) nounwind { define <vscale x 1 x half> @intrinsic_vfslide1down_vf_nxv1f16_nxv1f16_f16(<vscale x 1 x half> %0, half %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vfslide1down_vf_nxv1f16_nxv1f16_f16: ; CHECK-LABEL: intrinsic_vfslide1down_vf_nxv1f16_nxv1f16_f16:
▲ Show 20 Lines • Show All 697 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vfslide1up-rv32.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -target-abi ilp32 -verify-machineinstrs \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
declare <vscale x 1 x half> @llvm.riscv.vfslide1up.nxv1f16.f16( declare <vscale x 1 x half> @llvm.riscv.vfslide1up.nxv1f16.f16(
<vscale x 1 x half>, <vscale x 1 x half>,
half, half,
i32); i32);
define <vscale x 1 x half> @intrinsic_vfslide1up_vf_nxv1f16_nxv1f16_f16(<vscale x 1 x half> %0, half %1, i32 %2) nounwind { define <vscale x 1 x half> @intrinsic_vfslide1up_vf_nxv1f16_nxv1f16_f16(<vscale x 1 x half> %0, half %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vfslide1up_vf_nxv1f16_nxv1f16_f16: ; CHECK-LABEL: intrinsic_vfslide1up_vf_nxv1f16_nxv1f16_f16:
▲ Show 20 Lines • Show All 744 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vfslide1up-rv64.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -target-abi lp64 -verify-machineinstrs \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
declare <vscale x 1 x half> @llvm.riscv.vfslide1up.nxv1f16.f16( declare <vscale x 1 x half> @llvm.riscv.vfslide1up.nxv1f16.f16(
<vscale x 1 x half>, <vscale x 1 x half>,
half, half,
i64); i64);
define <vscale x 1 x half> @intrinsic_vfslide1up_vf_nxv1f16_nxv1f16_f16(<vscale x 1 x half> %0, half %1, i64 %2) nounwind { define <vscale x 1 x half> @intrinsic_vfslide1up_vf_nxv1f16_nxv1f16_f16(<vscale x 1 x half> %0, half %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vfslide1up_vf_nxv1f16_nxv1f16_f16: ; CHECK-LABEL: intrinsic_vfslide1up_vf_nxv1f16_nxv1f16_f16:
▲ Show 20 Lines • Show All 712 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vfsub-rv32.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -target-abi ilp32 -verify-machineinstrs \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
declare <vscale x 1 x half> @llvm.riscv.vfsub.nxv1f16.nxv1f16( declare <vscale x 1 x half> @llvm.riscv.vfsub.nxv1f16.nxv1f16(
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
i32); i32);
define <vscale x 1 x half> @intrinsic_vfsub_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i32 %2) nounwind { define <vscale x 1 x half> @intrinsic_vfsub_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vfsub_vv_nxv1f16_nxv1f16_nxv1f16: ; CHECK-LABEL: intrinsic_vfsub_vv_nxv1f16_nxv1f16_nxv1f16:
▲ Show 20 Lines • Show All 1,407 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vfsub-rv64.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -mattr=+experimental-zfh \ ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -mattr=+experimental-zfh \
; RUN: -mattr=+d -verify-machineinstrs \ ; RUN: -mattr=+d -target-abi lp64 -verify-machineinstrs \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
declare <vscale x 1 x half> @llvm.riscv.vfsub.nxv1f16.nxv1f16( declare <vscale x 1 x half> @llvm.riscv.vfsub.nxv1f16.nxv1f16(
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
i64); i64);
define <vscale x 1 x half> @intrinsic_vfsub_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2) nounwind { define <vscale x 1 x half> @intrinsic_vfsub_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vfsub_vv_nxv1f16_nxv1f16_nxv1f16: ; CHECK-LABEL: intrinsic_vfsub_vv_nxv1f16_nxv1f16_nxv1f16:
▲ Show 20 Lines • Show All 1,375 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vfwadd-rv32.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -target-abi ilp32 -verify-machineinstrs \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
declare <vscale x 1 x float> @llvm.riscv.vfwadd.nxv1f32.nxv1f16.nxv1f16( declare <vscale x 1 x float> @llvm.riscv.vfwadd.nxv1f32.nxv1f16.nxv1f16(
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
i32); i32);
define <vscale x 1 x float> @intrinsic_vfwadd_vv_nxv1f32_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i32 %2) nounwind { define <vscale x 1 x float> @intrinsic_vfwadd_vv_nxv1f32_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vfwadd_vv_nxv1f32_nxv1f16_nxv1f16: ; CHECK-LABEL: intrinsic_vfwadd_vv_nxv1f32_nxv1f16_nxv1f16:
▲ Show 20 Lines • Show All 838 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vfwadd-rv64.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -target-abi lp64 -verify-machineinstrs \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
declare <vscale x 1 x float> @llvm.riscv.vfwadd.nxv1f32.nxv1f16.nxv1f16( declare <vscale x 1 x float> @llvm.riscv.vfwadd.nxv1f32.nxv1f16.nxv1f16(
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
i64); i64);
define <vscale x 1 x float> @intrinsic_vfwadd_vv_nxv1f32_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2) nounwind { define <vscale x 1 x float> @intrinsic_vfwadd_vv_nxv1f32_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vfwadd_vv_nxv1f32_nxv1f16_nxv1f16: ; CHECK-LABEL: intrinsic_vfwadd_vv_nxv1f32_nxv1f16_nxv1f16:
▲ Show 20 Lines • Show All 838 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vfwadd.w-rv32.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -target-abi ilp32 -verify-machineinstrs \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
declare <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f32.nxv1f16( declare <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f32.nxv1f16(
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x half>, <vscale x 1 x half>,
i32); i32);
define <vscale x 1 x float> @intrinsic_vfwadd.w_wv_nxv1f32_nxv1f32_nxv1f16(<vscale x 1 x float> %0, <vscale x 1 x half> %1, i32 %2) nounwind { define <vscale x 1 x float> @intrinsic_vfwadd.w_wv_nxv1f32_nxv1f32_nxv1f16(<vscale x 1 x float> %0, <vscale x 1 x half> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vfwadd.w_wv_nxv1f32_nxv1f32_nxv1f16: ; CHECK-LABEL: intrinsic_vfwadd.w_wv_nxv1f32_nxv1f32_nxv1f16:
▲ Show 20 Lines • Show All 1,265 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vfwadd.w-rv64.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -target-abi lp64 -verify-machineinstrs \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
declare <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f32.nxv1f16( declare <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f32.nxv1f16(
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x half>, <vscale x 1 x half>,
i64); i64);
define <vscale x 1 x float> @intrinsic_vfwadd.w_wv_nxv1f32_nxv1f32_nxv1f16(<vscale x 1 x float> %0, <vscale x 1 x half> %1, i64 %2) nounwind { define <vscale x 1 x float> @intrinsic_vfwadd.w_wv_nxv1f32_nxv1f32_nxv1f16(<vscale x 1 x float> %0, <vscale x 1 x half> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vfwadd.w_wv_nxv1f32_nxv1f32_nxv1f16: ; CHECK-LABEL: intrinsic_vfwadd.w_wv_nxv1f32_nxv1f32_nxv1f16:
▲ Show 20 Lines • Show All 1,265 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vfwmacc-rv32.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -target-abi ilp32 -verify-machineinstrs \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
declare <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.nxv1f16( declare <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.nxv1f16(
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
i32); i32);
define <vscale x 1 x float> @intrinsic_vfwmacc_vv_nxv1f32_nxv1f16_nxv1f16(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i32 %3) nounwind { define <vscale x 1 x float> @intrinsic_vfwmacc_vv_nxv1f32_nxv1f16_nxv1f16(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i32 %3) nounwind {
▲ Show 20 Lines • Show All 838 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vfwmacc-rv64.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -target-abi lp64 -verify-machineinstrs \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
declare <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.nxv1f16( declare <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.nxv1f16(
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
i64); i64);
define <vscale x 1 x float> @intrinsic_vfwmacc_vv_nxv1f32_nxv1f16_nxv1f16(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 %3) nounwind { define <vscale x 1 x float> @intrinsic_vfwmacc_vv_nxv1f32_nxv1f16_nxv1f16(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 %3) nounwind {
▲ Show 20 Lines • Show All 838 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vfwmsac-rv32.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -target-abi ilp32 -verify-machineinstrs \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
declare <vscale x 1 x float> @llvm.riscv.vfwmsac.nxv1f32.nxv1f16( declare <vscale x 1 x float> @llvm.riscv.vfwmsac.nxv1f32.nxv1f16(
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
i32); i32);
define <vscale x 1 x float> @intrinsic_vfwmsac_vv_nxv1f32_nxv1f16_nxv1f16(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i32 %3) nounwind { define <vscale x 1 x float> @intrinsic_vfwmsac_vv_nxv1f32_nxv1f16_nxv1f16(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i32 %3) nounwind {
▲ Show 20 Lines • Show All 838 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vfwmsac-rv64.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -target-abi lp64 -verify-machineinstrs \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
declare <vscale x 1 x float> @llvm.riscv.vfwmsac.nxv1f32.nxv1f16( declare <vscale x 1 x float> @llvm.riscv.vfwmsac.nxv1f32.nxv1f16(
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
i64); i64);
define <vscale x 1 x float> @intrinsic_vfwmsac_vv_nxv1f32_nxv1f16_nxv1f16(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 %3) nounwind { define <vscale x 1 x float> @intrinsic_vfwmsac_vv_nxv1f32_nxv1f16_nxv1f16(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 %3) nounwind {
▲ Show 20 Lines • Show All 838 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vfwmul-rv32.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -target-abi ilp32 -verify-machineinstrs \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
declare <vscale x 1 x float> @llvm.riscv.vfwmul.nxv1f32.nxv1f16.nxv1f16( declare <vscale x 1 x float> @llvm.riscv.vfwmul.nxv1f32.nxv1f16.nxv1f16(
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
i32); i32);
define <vscale x 1 x float> @intrinsic_vfwmul_vv_nxv1f32_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i32 %2) nounwind { define <vscale x 1 x float> @intrinsic_vfwmul_vv_nxv1f32_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vfwmul_vv_nxv1f32_nxv1f16_nxv1f16: ; CHECK-LABEL: intrinsic_vfwmul_vv_nxv1f32_nxv1f16_nxv1f16:
▲ Show 20 Lines • Show All 838 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vfwmul-rv64.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -target-abi lp64 -verify-machineinstrs \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
declare <vscale x 1 x float> @llvm.riscv.vfwmul.nxv1f32.nxv1f16.nxv1f16( declare <vscale x 1 x float> @llvm.riscv.vfwmul.nxv1f32.nxv1f16.nxv1f16(
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
i64); i64);
define <vscale x 1 x float> @intrinsic_vfwmul_vv_nxv1f32_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2) nounwind { define <vscale x 1 x float> @intrinsic_vfwmul_vv_nxv1f32_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vfwmul_vv_nxv1f32_nxv1f16_nxv1f16: ; CHECK-LABEL: intrinsic_vfwmul_vv_nxv1f32_nxv1f16_nxv1f16:
▲ Show 20 Lines • Show All 838 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vfwnmacc-rv32.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -target-abi ilp32 -verify-machineinstrs \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
declare <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.nxv1f16( declare <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.nxv1f16(
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
i32); i32);
define <vscale x 1 x float> @intrinsic_vfwnmacc_vv_nxv1f32_nxv1f16_nxv1f16(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i32 %3) nounwind { define <vscale x 1 x float> @intrinsic_vfwnmacc_vv_nxv1f32_nxv1f16_nxv1f16(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i32 %3) nounwind {
▲ Show 20 Lines • Show All 838 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vfwnmacc-rv64.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -target-abi lp64 -verify-machineinstrs \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
declare <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.nxv1f16( declare <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.nxv1f16(
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
i64); i64);
define <vscale x 1 x float> @intrinsic_vfwnmacc_vv_nxv1f32_nxv1f16_nxv1f16(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 %3) nounwind { define <vscale x 1 x float> @intrinsic_vfwnmacc_vv_nxv1f32_nxv1f16_nxv1f16(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 %3) nounwind {
▲ Show 20 Lines • Show All 838 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vfwnmsac-rv32.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -target-abi ilp32 -verify-machineinstrs \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
declare <vscale x 1 x float> @llvm.riscv.vfwnmsac.nxv1f32.nxv1f16( declare <vscale x 1 x float> @llvm.riscv.vfwnmsac.nxv1f32.nxv1f16(
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
i32); i32);
define <vscale x 1 x float> @intrinsic_vfwnmsac_vv_nxv1f32_nxv1f16_nxv1f16(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i32 %3) nounwind { define <vscale x 1 x float> @intrinsic_vfwnmsac_vv_nxv1f32_nxv1f16_nxv1f16(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i32 %3) nounwind {
▲ Show 20 Lines • Show All 838 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vfwnmsac-rv64.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -target-abi lp64 -verify-machineinstrs \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
declare <vscale x 1 x float> @llvm.riscv.vfwnmsac.nxv1f32.nxv1f16( declare <vscale x 1 x float> @llvm.riscv.vfwnmsac.nxv1f32.nxv1f16(
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
i64); i64);
define <vscale x 1 x float> @intrinsic_vfwnmsac_vv_nxv1f32_nxv1f16_nxv1f16(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 %3) nounwind { define <vscale x 1 x float> @intrinsic_vfwnmsac_vv_nxv1f32_nxv1f16_nxv1f16(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 %3) nounwind {
▲ Show 20 Lines • Show All 838 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vfwsub-rv32.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -target-abi ilp32 -verify-machineinstrs \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
declare <vscale x 1 x float> @llvm.riscv.vfwsub.nxv1f32.nxv1f16.nxv1f16( declare <vscale x 1 x float> @llvm.riscv.vfwsub.nxv1f32.nxv1f16.nxv1f16(
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
i32); i32);
define <vscale x 1 x float> @intrinsic_vfwsub_vv_nxv1f32_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i32 %2) nounwind { define <vscale x 1 x float> @intrinsic_vfwsub_vv_nxv1f32_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vfwsub_vv_nxv1f32_nxv1f16_nxv1f16: ; CHECK-LABEL: intrinsic_vfwsub_vv_nxv1f32_nxv1f16_nxv1f16:
▲ Show 20 Lines • Show All 838 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vfwsub-rv64.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -target-abi lp64 -verify-machineinstrs \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
declare <vscale x 1 x float> @llvm.riscv.vfwsub.nxv1f32.nxv1f16.nxv1f16( declare <vscale x 1 x float> @llvm.riscv.vfwsub.nxv1f32.nxv1f16.nxv1f16(
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
i64); i64);
define <vscale x 1 x float> @intrinsic_vfwsub_vv_nxv1f32_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2) nounwind { define <vscale x 1 x float> @intrinsic_vfwsub_vv_nxv1f32_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vfwsub_vv_nxv1f32_nxv1f16_nxv1f16: ; CHECK-LABEL: intrinsic_vfwsub_vv_nxv1f32_nxv1f16_nxv1f16:
▲ Show 20 Lines • Show All 838 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vfwsub.w-rv32.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -target-abi ilp32 -verify-machineinstrs \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
declare <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.nxv1f16( declare <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.nxv1f16(
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x half>, <vscale x 1 x half>,
i32); i32);
define <vscale x 1 x float> @intrinsic_vfwsub.w_wv_nxv1f32_nxv1f32_nxv1f16(<vscale x 1 x float> %0, <vscale x 1 x half> %1, i32 %2) nounwind { define <vscale x 1 x float> @intrinsic_vfwsub.w_wv_nxv1f32_nxv1f32_nxv1f16(<vscale x 1 x float> %0, <vscale x 1 x half> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vfwsub.w_wv_nxv1f32_nxv1f32_nxv1f16: ; CHECK-LABEL: intrinsic_vfwsub.w_wv_nxv1f32_nxv1f32_nxv1f16:
▲ Show 20 Lines • Show All 1,265 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vfwsub.w-rv64.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -target-abi lp64 -verify-machineinstrs \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
declare <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.nxv1f16( declare <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.nxv1f16(
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x half>, <vscale x 1 x half>,
i64); i64);
define <vscale x 1 x float> @intrinsic_vfwsub.w_wv_nxv1f32_nxv1f32_nxv1f16(<vscale x 1 x float> %0, <vscale x 1 x half> %1, i64 %2) nounwind { define <vscale x 1 x float> @intrinsic_vfwsub.w_wv_nxv1f32_nxv1f32_nxv1f16(<vscale x 1 x float> %0, <vscale x 1 x half> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vfwsub.w_wv_nxv1f32_nxv1f32_nxv1f16: ; CHECK-LABEL: intrinsic_vfwsub.w_wv_nxv1f32_nxv1f32_nxv1f16:
▲ Show 20 Lines • Show All 1,265 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vmfeq-rv32.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -target-abi ilp32 -verify-machineinstrs \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
declare <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1f16( declare <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1f16(
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
i32); i32);
define <vscale x 1 x i1> @intrinsic_vmfeq_vv_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i32 %2) nounwind { define <vscale x 1 x i1> @intrinsic_vmfeq_vv_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vmfeq_vv_nxv1f16_nxv1f16: ; CHECK-LABEL: intrinsic_vmfeq_vv_nxv1f16_nxv1f16:
▲ Show 20 Lines • Show All 1,228 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vmfeq-rv64.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -target-abi lp64 -verify-machineinstrs \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
declare <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1f16( declare <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1f16(
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
i64); i64);
define <vscale x 1 x i1> @intrinsic_vmfeq_vv_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2) nounwind { define <vscale x 1 x i1> @intrinsic_vmfeq_vv_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmfeq_vv_nxv1f16_nxv1f16: ; CHECK-LABEL: intrinsic_vmfeq_vv_nxv1f16_nxv1f16:
▲ Show 20 Lines • Show All 1,204 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vmfge-rv32.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -target-abi ilp32 -verify-machineinstrs \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
declare <vscale x 1 x i1> @llvm.riscv.vmfge.nxv1f16( declare <vscale x 1 x i1> @llvm.riscv.vmfge.nxv1f16(
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
i32); i32);
define <vscale x 1 x i1> @intrinsic_vmfge_vv_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i32 %2) nounwind { define <vscale x 1 x i1> @intrinsic_vmfge_vv_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vmfge_vv_nxv1f16_nxv1f16: ; CHECK-LABEL: intrinsic_vmfge_vv_nxv1f16_nxv1f16:
▲ Show 20 Lines • Show All 1,228 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vmfge-rv64.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -target-abi lp64 -verify-machineinstrs \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
declare <vscale x 1 x i1> @llvm.riscv.vmfge.nxv1f16( declare <vscale x 1 x i1> @llvm.riscv.vmfge.nxv1f16(
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
i64); i64);
define <vscale x 1 x i1> @intrinsic_vmfge_vv_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2) nounwind { define <vscale x 1 x i1> @intrinsic_vmfge_vv_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmfge_vv_nxv1f16_nxv1f16: ; CHECK-LABEL: intrinsic_vmfge_vv_nxv1f16_nxv1f16:
▲ Show 20 Lines • Show All 1,204 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vmfgt-rv32.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -target-abi ilp32 -verify-machineinstrs \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
declare <vscale x 1 x i1> @llvm.riscv.vmfgt.nxv1f16( declare <vscale x 1 x i1> @llvm.riscv.vmfgt.nxv1f16(
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
i32); i32);
define <vscale x 1 x i1> @intrinsic_vmfgt_vv_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i32 %2) nounwind { define <vscale x 1 x i1> @intrinsic_vmfgt_vv_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vmfgt_vv_nxv1f16_nxv1f16: ; CHECK-LABEL: intrinsic_vmfgt_vv_nxv1f16_nxv1f16:
▲ Show 20 Lines • Show All 1,228 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vmfgt-rv64.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -target-abi lp64 -verify-machineinstrs \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
declare <vscale x 1 x i1> @llvm.riscv.vmfgt.nxv1f16( declare <vscale x 1 x i1> @llvm.riscv.vmfgt.nxv1f16(
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
i64); i64);
define <vscale x 1 x i1> @intrinsic_vmfgt_vv_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2) nounwind { define <vscale x 1 x i1> @intrinsic_vmfgt_vv_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmfgt_vv_nxv1f16_nxv1f16: ; CHECK-LABEL: intrinsic_vmfgt_vv_nxv1f16_nxv1f16:
▲ Show 20 Lines • Show All 1,204 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vmfle-rv32.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -target-abi ilp32 -verify-machineinstrs \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
declare <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1f16( declare <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1f16(
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
i32); i32);
define <vscale x 1 x i1> @intrinsic_vmfle_vv_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i32 %2) nounwind { define <vscale x 1 x i1> @intrinsic_vmfle_vv_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vmfle_vv_nxv1f16_nxv1f16: ; CHECK-LABEL: intrinsic_vmfle_vv_nxv1f16_nxv1f16:
▲ Show 20 Lines • Show All 1,228 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vmfle-rv64.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -target-abi lp64 -verify-machineinstrs \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
declare <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1f16( declare <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1f16(
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
i64); i64);
define <vscale x 1 x i1> @intrinsic_vmfle_vv_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2) nounwind { define <vscale x 1 x i1> @intrinsic_vmfle_vv_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmfle_vv_nxv1f16_nxv1f16: ; CHECK-LABEL: intrinsic_vmfle_vv_nxv1f16_nxv1f16:
▲ Show 20 Lines • Show All 1,204 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vmflt-rv32.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -target-abi ilp32 -verify-machineinstrs \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
declare <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1f16( declare <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1f16(
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
i32); i32);
define <vscale x 1 x i1> @intrinsic_vmflt_vv_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i32 %2) nounwind { define <vscale x 1 x i1> @intrinsic_vmflt_vv_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vmflt_vv_nxv1f16_nxv1f16: ; CHECK-LABEL: intrinsic_vmflt_vv_nxv1f16_nxv1f16:
▲ Show 20 Lines • Show All 1,228 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vmflt-rv64.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -target-abi lp64 -verify-machineinstrs \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
declare <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1f16( declare <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1f16(
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
i64); i64);
define <vscale x 1 x i1> @intrinsic_vmflt_vv_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2) nounwind { define <vscale x 1 x i1> @intrinsic_vmflt_vv_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmflt_vv_nxv1f16_nxv1f16: ; CHECK-LABEL: intrinsic_vmflt_vv_nxv1f16_nxv1f16:
▲ Show 20 Lines • Show All 1,204 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vmfne-rv32.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -target-abi ilp32 -verify-machineinstrs \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
declare <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1f16( declare <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1f16(
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
i32); i32);
define <vscale x 1 x i1> @intrinsic_vmfne_vv_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i32 %2) nounwind { define <vscale x 1 x i1> @intrinsic_vmfne_vv_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vmfne_vv_nxv1f16_nxv1f16: ; CHECK-LABEL: intrinsic_vmfne_vv_nxv1f16_nxv1f16:
▲ Show 20 Lines • Show All 1,228 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vmfne-rv64.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -target-abi lp64 -verify-machineinstrs \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
declare <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1f16( declare <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1f16(
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
i64); i64);
define <vscale x 1 x i1> @intrinsic_vmfne_vv_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2) nounwind { define <vscale x 1 x i1> @intrinsic_vmfne_vv_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmfne_vv_nxv1f16_nxv1f16: ; CHECK-LABEL: intrinsic_vmfne_vv_nxv1f16_nxv1f16:
▲ Show 20 Lines • Show All 1,204 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -mattr=+m,+f,+d,+a,+c,+experimental-v \ ; RUN: llc -mtriple=riscv64 -mattr=+m,+f,+d,+a,+c,+experimental-v -target-abi lp64 \
; RUN: -verify-machineinstrs -O2 < %s | FileCheck %s ; RUN: -verify-machineinstrs -O2 < %s | FileCheck %s
; The following tests check whether inserting VSETVLI avoids inserting ; The following tests check whether inserting VSETVLI avoids inserting
; unneeded vsetvlis across basic blocks. ; unneeded vsetvlis across basic blocks.
declare i64 @llvm.riscv.vsetvli(i64, i64, i64) declare i64 @llvm.riscv.vsetvli(i64, i64, i64)
declare <vscale x 1 x double> @llvm.riscv.vfadd.nxv1f64.nxv1f64(<vscale x 1 x double>, <vscale x 1 x double>, i64) declare <vscale x 1 x double> @llvm.riscv.vfadd.nxv1f64.nxv1f64(<vscale x 1 x double>, <vscale x 1 x double>, i64)
▲ Show 20 Lines • Show All 576 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/select-const.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32I %s ; RUN: | FileCheck -check-prefix=RV32I %s
; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv32 -mattr=+f -target-abi ilp32 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32IF %s ; RUN: | FileCheck -check-prefix=RV32IF %s
; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbt -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbt -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32IBT %s ; RUN: | FileCheck -check-prefix=RV32IBT %s
; RUN: llc -mtriple=riscv32 -mattr=+f,+experimental-zbt -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv32 -mattr=+f,+experimental-zbt -target-abi ilp32 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32IFBT %s ; RUN: | FileCheck -check-prefix=RV32IFBT %s
; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64I %s ; RUN: | FileCheck -check-prefix=RV64I %s
; RUN: llc -mtriple=riscv64 -mattr=+f,+d -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv64 -mattr=+f,+d -target-abi lp64 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64IFD %s ; RUN: | FileCheck -check-prefix=RV64IFD %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbt -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbt -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64IBT %s ; RUN: | FileCheck -check-prefix=RV64IBT %s
; RUN: llc -mtriple=riscv64 -mattr=+f,+d,+experimental-zbt -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv64 -mattr=+f,+d,+experimental-zbt -target-abi lp64 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64IFDBT %s ; RUN: | FileCheck -check-prefix=RV64IFDBT %s
;; This tests how good we are at materialising constants using `select`. The aim ;; This tests how good we are at materialising constants using `select`. The aim
;; is that we do so without a branch if possible (at the moment our lowering of ;; is that we do so without a branch if possible (at the moment our lowering of
;; select always introduces a branch). ;; select always introduces a branch).
;; ;;
;; Currently the hook `convertSelectOfConstantsToMath` only is useful when the ;; Currently the hook `convertSelectOfConstantsToMath` only is useful when the
;; constants are either 1 away from each other, or one is a power of two and ;; constants are either 1 away from each other, or one is a power of two and
▲ Show 20 Lines • Show All 299 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/select-optimize-multiple.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+d -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv32 -mattr=+d -target-abi ilp32 -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV32I ; RUN: | FileCheck %s -check-prefix=RV32I
; RUN: llc -mtriple=riscv32 -mattr=+d,+experimental-zbt -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv32 -mattr=+d,+experimental-zbt -target-abi ilp32 -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV32IBT ; RUN: | FileCheck %s -check-prefix=RV32IBT
; RUN: llc -mtriple=riscv64 -mattr=+d -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv64 -mattr=+d -target-abi lp64 -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV64I ; RUN: | FileCheck %s -check-prefix=RV64I
; RUN: llc -mtriple=riscv64 -mattr=+d,+experimental-zbt -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv64 -mattr=+d,+experimental-zbt -target-abi lp64 -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV64IBT ; RUN: | FileCheck %s -check-prefix=RV64IBT
; Selects of wide values are split into two selects, which can easily cause ; Selects of wide values are split into two selects, which can easily cause
; unnecessary control flow. Here we check some cases where we can currently ; unnecessary control flow. Here we check some cases where we can currently
; emit a sequence of selects with shared control flow. ; emit a sequence of selects with shared control flow.
define i64 @cmovcc64(i32 signext %a, i64 %b, i64 %c) nounwind { define i64 @cmovcc64(i32 signext %a, i64 %b, i64 %c) nounwind {
; RV32I-LABEL: cmovcc64: ; RV32I-LABEL: cmovcc64:
▲ Show 20 Lines • Show All 519 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/spill-fpr-scalar.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh \ ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh \
; RUN: -verify-machineinstrs < %s \ ; RUN: -target-abi lp64 -verify-machineinstrs < %s \
; RUN: | FileCheck %s ; RUN: | FileCheck %s
declare half @llvm.riscv.vfmv.f.s.nxv1f16(<vscale x 1 x half>) declare half @llvm.riscv.vfmv.f.s.nxv1f16(<vscale x 1 x half>)
declare float @llvm.riscv.vfmv.f.s.nxv1f32(<vscale x 1 x float>) declare float @llvm.riscv.vfmv.f.s.nxv1f32(<vscale x 1 x float>)
declare double @llvm.riscv.vfmv.f.s.nxv1f64(<vscale x 1 x double>) declare double @llvm.riscv.vfmv.f.s.nxv1f64(<vscale x 1 x double>)
declare <vscale x 1 x half> @llvm.riscv.vfmv.v.f.nxv1f16(half, i64); declare <vscale x 1 x half> @llvm.riscv.vfmv.v.f.nxv1f16(half, i64);
declare <vscale x 1 x float> @llvm.riscv.vfmv.v.f.nxv1f32(float, i64); declare <vscale x 1 x float> @llvm.riscv.vfmv.v.f.nxv1f32(float, i64);
▲ Show 20 Lines • Show All 64 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/vararg.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=ILP32-ILP32F-FPELIM %s ; RUN: | FileCheck -check-prefix=ILP32-ILP32F-FPELIM %s
; RUN: llc -mtriple=riscv32 -verify-machineinstrs -frame-pointer=all < %s \ ; RUN: llc -mtriple=riscv32 -verify-machineinstrs -frame-pointer=all < %s \
; RUN: | FileCheck -check-prefix=ILP32-ILP32F-WITHFP %s ; RUN: | FileCheck -check-prefix=ILP32-ILP32F-WITHFP %s
; RUN: llc -mtriple=riscv32 -mattr=+d -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv32 -mattr=+d -target-abi ilp32 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32D-ILP32-ILP32F-ILP32D-FPELIM %s ; RUN: | FileCheck -check-prefix=RV32D-ILP32-ILP32F-ILP32D-FPELIM %s
; RUN: llc -mtriple=riscv32 -mattr=+d -target-abi ilp32f \ ; RUN: llc -mtriple=riscv32 -mattr=+d -target-abi ilp32f \
; RUN: -verify-machineinstrs < %s \ ; RUN: -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32D-ILP32-ILP32F-ILP32D-FPELIM %s ; RUN: | FileCheck -check-prefix=RV32D-ILP32-ILP32F-ILP32D-FPELIM %s
; RUN: llc -mtriple=riscv32 -mattr=+d -target-abi ilp32d \ ; RUN: llc -mtriple=riscv32 -mattr=+d -target-abi ilp32d \
; RUN: -verify-machineinstrs < %s \ ; RUN: -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32D-ILP32-ILP32F-ILP32D-FPELIM %s ; RUN: | FileCheck -check-prefix=RV32D-ILP32-ILP32F-ILP32D-FPELIM %s
; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
▲ Show 20 Lines • Show All 1,937 Lines • Show Last 20 Lines

llvm/test/Transforms/LoopVectorize/RISCV/riscv-unroll.ll

; RUN: opt < %s -loop-vectorize -mtriple=riscv64 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -S | FileCheck %s ; RUN: opt < %s -loop-vectorize -mtriple=riscv64 -mattr=+experimental-v -target-abi lp64 -riscv-v-vector-bits-min=128 -S | FileCheck %s
; RUN: opt < %s -loop-vectorize -mtriple=riscv32 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -S | FileCheck %s ; RUN: opt < %s -loop-vectorize -mtriple=riscv32 -mattr=+experimental-v -target-abi ilp32 -riscv-v-vector-bits-min=128 -S | FileCheck %s
; Function Attrs: nounwind ; Function Attrs: nounwind
define i32* @array_add(i32* noalias nocapture readonly %a, i32* noalias nocapture readonly %b, i32* %c, i32 %size) { define i32* @array_add(i32* noalias nocapture readonly %a, i32* noalias nocapture readonly %b, i32* %c, i32 %size) {
;CHECK-LABEL: array_add ;CHECK-LABEL: array_add
;CHECK: load <4 x i32> ;CHECK: load <4 x i32>
;CHECK: load <4 x i32> ;CHECK: load <4 x i32>
;CHECK: add nsw <4 x i32> ;CHECK: add nsw <4 x i32>
;CHECK: store <4 x i32> ;CHECK: store <4 x i32>
Show All 28 Lines