[AArch64][SVE] Use TargetFrameIndex in more SVE load/store addressing modes

[bsmith]

Summary

Add support for generating TargetFrameIndex in complex patterns for
indexed addressing modes in SVE. Additionally, add missing load/stores
to getMemOpInfo and getLoadStoreImmIdx.

[peterwaller-arm]

llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td

2246

If these patterns are no longer needed, does the same thing apply to the two remaining uses of am_sve_fi?

https://github.com/llvm/llvm-project/blob/888af47095d5a7121c1d78566df59c292f30ceaf/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td#L2304-L2305
https://github.com/llvm/llvm-project/blob/888af47095d5a7121c1d78566df59c292f30ceaf/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td#L2314-L2315

... and if so could am_sve_fi be removed? I'm guessing here that these are no longer necessary because some other part of the lowering handles it after your change, and I see that STR_PXI and LDR_PXI are already handled around there.

[bsmith]

llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td

2246

Not in their current state, no. The Other uses of arm_sve_fi are in places that don't have patterns for that the indexed complex patterns that have changed. I did consider changing those instruction patterns, but it's not clear to me why they have been written like that, and given it's not causing an issue I opted to leave them as is.

[peterwaller-arm]

LGTM.

[mnadeem]

Seeing a crash after this. Created a bug report here: https://github.com/llvm/llvm-project/issues/53781

llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp

 /// SelectAddrModeIndexedSVE - Attempt selection of the addressing mode:
 /// Base + OffImm * sizeof(MemVT) for Min >= OffImm <= Max
 /// where Root is the memory access using N for its address.
 template <int64_t Min, int64_t Max>
 bool AArch64DAGToDAGISel::SelectAddrModeIndexedSVE(SDNode *Root, SDValue N,
                                                    SDValue &Base,
                                                    SDValue &OffImm) {
   const EVT MemVT = getMemVTFromNode(*(CurDAG->getContext()), Root);
+  const DataLayout &DL = CurDAG->getDataLayout();
+
+  if (N.getOpcode() == ISD::FrameIndex) {
+    int FI = cast<FrameIndexSDNode>(N)->getIndex();
+    Base = CurDAG->getTargetFrameIndex(FI, TLI->getPointerTy(DL));
+    OffImm = CurDAG->getTargetConstant(0, SDLoc(N), MVT::i64);
+    return true;
+  }
 
   if (MemVT == EVT())
     return false;
 
   if (N.getOpcode() != ISD::ADD)
     return false;
 
   SDValue VScale = N.getOperand(1);
   if (VScale.getOpcode() != ISD::VSCALE)
     return false;
 
   TypeSize TS = MemVT.getSizeInBits();
   int64_t MemWidthBytes = static_cast<int64_t>(TS.getKnownMinSize()) / 8;
   int64_t MulImm = cast<ConstantSDNode>(VScale.getOperand(0))->getSExtValue();
 
   if ((MulImm % MemWidthBytes) != 0)
     return false;
 
   int64_t Offset = MulImm / MemWidthBytes;
   if (Offset < Min || Offset > Max)
     return false;
 
   Base = N.getOperand(0);
+  if (Base.getOpcode() == ISD::FrameIndex) {
+    int FI = cast<FrameIndexSDNode>(Base)->getIndex();
+    Base = CurDAG->getTargetFrameIndex(FI, TLI->getPointerTy(DL));
+  }
+
   OffImm = CurDAG->getTargetConstant(Offset, SDLoc(N), MVT::i64);
   return true;
 }
 
 /// Select register plus register addressing mode for SVE, with scaled
 /// offset.
 bool AArch64DAGToDAGISel::SelectSVERegRegAddrMode(SDValue N, unsigned Scale,
                                                   SDValue &Base,

llvm/lib/Target/AArch64/AArch64InstrInfo.cpp

unsigned AArch64InstrInfo::getLoadStoreImmIdx(unsigned Opc) {
   case AArch64::STPWi:
   case AArch64::STPSi:
   case AArch64::LDNPWi:
   case AArch64::LDNPSi:
   case AArch64::STNPWi:
   case AArch64::STNPSi:
   case AArch64::LDG:
   case AArch64::STGPi:
+
   case AArch64::LD1B_IMM:
-  case AArch64::LD1H_IMM:
-  case AArch64::LD1W_IMM:
-  case AArch64::LD1D_IMM:
-  case AArch64::ST1B_IMM:
-  case AArch64::ST1H_IMM:
-  case AArch64::ST1W_IMM:
-  case AArch64::ST1D_IMM:
   case AArch64::LD1B_H_IMM:
+  case AArch64::LD1B_S_IMM:
+  case AArch64::LD1B_D_IMM:
   case AArch64::LD1SB_H_IMM:
+  case AArch64::LD1SB_S_IMM:
+  case AArch64::LD1SB_D_IMM:
+  case AArch64::LD1H_IMM:
   case AArch64::LD1H_S_IMM:
+  case AArch64::LD1H_D_IMM:
   case AArch64::LD1SH_S_IMM:
+  case AArch64::LD1SH_D_IMM:
+  case AArch64::LD1W_IMM:
   case AArch64::LD1W_D_IMM:
   case AArch64::LD1SW_D_IMM:
+  case AArch64::LD1D_IMM:
+
+  case AArch64::ST1B_IMM:
   case AArch64::ST1B_H_IMM:
-  case AArch64::ST1H_S_IMM:
-  case AArch64::ST1W_D_IMM:
-  case AArch64::LD1B_S_IMM:
-  case AArch64::LD1SB_S_IMM:
-  case AArch64::LD1H_D_IMM:
-  case AArch64::LD1SH_D_IMM:
   case AArch64::ST1B_S_IMM:
-  case AArch64::ST1H_D_IMM:
-  case AArch64::LD1B_D_IMM:
-  case AArch64::LD1SB_D_IMM:
   case AArch64::ST1B_D_IMM:
+  case AArch64::ST1H_IMM:
+  case AArch64::ST1H_S_IMM:
+  case AArch64::ST1H_D_IMM:
+  case AArch64::ST1W_IMM:
+  case AArch64::ST1W_D_IMM:
+  case AArch64::ST1D_IMM:
+
   case AArch64::LD1RB_IMM:
   case AArch64::LD1RB_H_IMM:
   case AArch64::LD1RB_S_IMM:
   case AArch64::LD1RB_D_IMM:
   case AArch64::LD1RSB_H_IMM:
   case AArch64::LD1RSB_S_IMM:
   case AArch64::LD1RSB_D_IMM:
   case AArch64::LD1RH_IMM:
   case AArch64::LD1RH_S_IMM:
   case AArch64::LD1RH_D_IMM:
   case AArch64::LD1RSH_S_IMM:
   case AArch64::LD1RSH_D_IMM:
   case AArch64::LD1RW_IMM:
   case AArch64::LD1RW_D_IMM:
   case AArch64::LD1RSW_IMM:
   case AArch64::LD1RD_IMM:
+
+  case AArch64::LDNT1B_ZRI:
+  case AArch64::LDNT1H_ZRI:
+  case AArch64::LDNT1W_ZRI:
+  case AArch64::LDNT1D_ZRI:
+  case AArch64::STNT1B_ZRI:
+  case AArch64::STNT1H_ZRI:
+  case AArch64::STNT1W_ZRI:
+  case AArch64::STNT1D_ZRI:
+
+  case AArch64::LDNF1B_IMM:
+  case AArch64::LDNF1B_H_IMM:
+  case AArch64::LDNF1B_S_IMM:
+  case AArch64::LDNF1B_D_IMM:
+  case AArch64::LDNF1SB_H_IMM:
+  case AArch64::LDNF1SB_S_IMM:
+  case AArch64::LDNF1SB_D_IMM:
+  case AArch64::LDNF1H_IMM:
+  case AArch64::LDNF1H_S_IMM:
+  case AArch64::LDNF1H_D_IMM:
+  case AArch64::LDNF1SH_S_IMM:
+  case AArch64::LDNF1SH_D_IMM:
+  case AArch64::LDNF1W_IMM:
+  case AArch64::LDNF1W_D_IMM:
+  case AArch64::LDNF1SW_D_IMM:
+  case AArch64::LDNF1D_IMM:
     return 3;
   case AArch64::ADDG:
   case AArch64::STGOffset:
   case AArch64::LDR_PXI:
   case AArch64::STR_PXI:
     return 2;
   }
 }
case AArch64::STR_ZXI:
     Width = SVEMaxBytesPerVector;
     MinOffset = -256;
     MaxOffset = 255;
     break;
   case AArch64::LD1B_IMM:
   case AArch64::LD1H_IMM:
   case AArch64::LD1W_IMM:
   case AArch64::LD1D_IMM:
+  case AArch64::LDNT1B_ZRI:
+  case AArch64::LDNT1H_ZRI:
+  case AArch64::LDNT1W_ZRI:
+  case AArch64::LDNT1D_ZRI:
   case AArch64::ST1B_IMM:
   case AArch64::ST1H_IMM:
   case AArch64::ST1W_IMM:
   case AArch64::ST1D_IMM:
+  case AArch64::STNT1B_ZRI:
+  case AArch64::STNT1H_ZRI:
+  case AArch64::STNT1W_ZRI:
+  case AArch64::STNT1D_ZRI:
+  case AArch64::LDNF1B_IMM:
+  case AArch64::LDNF1H_IMM:
+  case AArch64::LDNF1W_IMM:
+  case AArch64::LDNF1D_IMM:
     // A full vectors worth of data
     // Width = mbytes * elements
     Scale = TypeSize::Scalable(16);
     Width = SVEMaxBytesPerVector;
     MinOffset = -8;
     MaxOffset = 7;
     break;
   case AArch64::LD1B_H_IMM:
   case AArch64::LD1SB_H_IMM:
   case AArch64::LD1H_S_IMM:
   case AArch64::LD1SH_S_IMM:
   case AArch64::LD1W_D_IMM:
   case AArch64::LD1SW_D_IMM:
   case AArch64::ST1B_H_IMM:
   case AArch64::ST1H_S_IMM:
   case AArch64::ST1W_D_IMM:
+  case AArch64::LDNF1B_H_IMM:
+  case AArch64::LDNF1SB_H_IMM:
+  case AArch64::LDNF1H_S_IMM:
+  case AArch64::LDNF1SH_S_IMM:
+  case AArch64::LDNF1W_D_IMM:
+  case AArch64::LDNF1SW_D_IMM:
     // A half vector worth of data
     // Width = mbytes * elements
     Scale = TypeSize::Scalable(8);
     Width = SVEMaxBytesPerVector / 2;
     MinOffset = -8;
     MaxOffset = 7;
     break;
   case AArch64::LD1B_S_IMM:
   case AArch64::LD1SB_S_IMM:
   case AArch64::LD1H_D_IMM:
   case AArch64::LD1SH_D_IMM:
   case AArch64::ST1B_S_IMM:
   case AArch64::ST1H_D_IMM:
+  case AArch64::LDNF1B_S_IMM:
+  case AArch64::LDNF1SB_S_IMM:
+  case AArch64::LDNF1H_D_IMM:
+  case AArch64::LDNF1SH_D_IMM:
     // A quarter vector worth of data
     // Width = mbytes * elements
     Scale = TypeSize::Scalable(4);
     Width = SVEMaxBytesPerVector / 4;
     MinOffset = -8;
     MaxOffset = 7;
     break;
   case AArch64::LD1B_D_IMM:
   case AArch64::LD1SB_D_IMM:
   case AArch64::ST1B_D_IMM:
+  case AArch64::LDNF1B_D_IMM:
+  case AArch64::LDNF1SB_D_IMM:
     // A eighth vector worth of data
     // Width = mbytes * elements
     Scale = TypeSize::Scalable(2);
     Width = SVEMaxBytesPerVector / 8;
     MinOffset = -8;
     MaxOffset = 7;
     break;
   case AArch64::ST2GOffset:

llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td

multiclass unpred_store<PatFrag Store, ValueType Ty, Instruction RegRegInst,
     let AddedComplexity = 1 in {
       def _reg : Pat<(Store (Ty ZPR:$val), (AddrCP GPR64sp:$base, GPR64:$offset)),
                      (RegRegInst ZPR:$val, (PTrue 31), GPR64sp:$base, GPR64:$offset)>;
     }
     let AddedComplexity = 2 in {
       def _imm : Pat<(Store (Ty ZPR:$val), (am_sve_indexed_s4 GPR64sp:$base, simm4s1:$offset)),
                      (RegImmInst ZPR:$val, (PTrue 31), GPR64sp:$base, simm4s1:$offset)>;
     }
-    let AddedComplexity = 3 in {
-      def _fi : Pat<(Store (Ty ZPR:$val), (am_sve_fi GPR64sp:$base, simm4s1:$offset)),
-                    (RegImmInst ZPR:$val, (PTrue 31), GPR64sp:$base, simm4s1:$offset)>;
-    }
 
     def : Pat<(Store (Ty ZPR:$val), GPR64:$base),
               (RegImmInst ZPR:$val, (PTrue 31), GPR64:$base, (i64 0))>;
   }
 
   defm : unpred_store<         store, nxv16i8,    ST1B,   ST1B_IMM, PTRUE_B, am_sve_regreg_lsl0>;
   defm : unpred_store< truncstorevi8, nxv8i16,  ST1B_H, ST1B_H_IMM, PTRUE_H, am_sve_regreg_lsl0>;
   defm : unpred_store< truncstorevi8, nxv4i32,  ST1B_S, ST1B_S_IMM, PTRUE_S, am_sve_regreg_lsl0>;
multiclass unpred_load<PatFrag Load, ValueType Ty, Instruction RegRegInst,
     let AddedComplexity = 1 in {
       def _reg: Pat<(Ty (Load  (AddrCP GPR64sp:$base, GPR64:$offset))),
                     (RegRegInst (PTrue 31), GPR64sp:$base, GPR64:$offset)>;
     }
     let AddedComplexity = 2 in {
       def _imm: Pat<(Ty (Load  (am_sve_indexed_s4 GPR64sp:$base, simm4s1:$offset))),
                     (RegImmInst (PTrue 31), GPR64sp:$base, simm4s1:$offset)>;
     }
-    let AddedComplexity = 3 in {
-      def _fi : Pat<(Ty (Load  (am_sve_fi GPR64sp:$base, simm4s1:$offset))),
-                    (RegImmInst (PTrue 31), GPR64sp:$base, simm4s1:$offset)>;
-    }
 
     def : Pat<(Ty (Load GPR64:$base)),
               (RegImmInst (PTrue 31), GPR64:$base, (i64 0))>;
   }
 
   defm : unpred_load<        load, nxv16i8,    LD1B,    LD1B_IMM, PTRUE_B, am_sve_regreg_lsl0>;
   defm : unpred_load< zextloadvi8, nxv8i16,  LD1B_H,  LD1B_H_IMM, PTRUE_H, am_sve_regreg_lsl0>;
   defm : unpred_load< zextloadvi8, nxv4i32,  LD1B_S,  LD1B_S_IMM, PTRUE_S, am_sve_regreg_lsl0>;

llvm/test/CodeGen/AArch64/named-vector-shuffles-sve.ll

 
 ; Ensure index is clamped when we cannot prove it's less than 2048-bit.
 define <vscale x 16 x i8> @splice_nxv16i8_clamped_idx(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) #0 {
 ; CHECK-LABEL: splice_nxv16i8_clamped_idx:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    str x29, [sp, #-16]! // 8-byte Folded Spill
 ; CHECK-NEXT:    addvl sp, sp, #-2
 ; CHECK-NEXT:    mov x8, #-1
-; CHECK-NEXT:    mov x9, sp
-; CHECK-NEXT:    mov w10, #256
+; CHECK-NEXT:    mov w9, #256
 ; CHECK-NEXT:    ptrue p0.b
 ; CHECK-NEXT:    st1b { z0.b }, p0, [sp]
+; CHECK-NEXT:    st1b { z1.b }, p0, [sp, #1, mul vl]
 ; CHECK-NEXT:    addvl x8, x8, #1
-; CHECK-NEXT:    st1b { z1.b }, p0, [x9, #1, mul vl]
 ; CHECK-NEXT:    cmp x8, #256
-; CHECK-NEXT:    csel x8, x8, x10, lo
+; CHECK-NEXT:    csel x8, x8, x9, lo
+; CHECK-NEXT:    mov x9, sp
 ; CHECK-NEXT:    ld1b { z0.b }, p0/z, [x9, x8]
 ; CHECK-NEXT:    addvl sp, sp, #2
 ; CHECK-NEXT:    ldr x29, [sp], #16 // 8-byte Folded Reload
 ; CHECK-NEXT:    ret
   %res = call <vscale x 16 x i8> @llvm.experimental.vector.splice.nxv16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b, i32 256)
   ret <vscale x 16 x i8> %res
 }
 

 
 ; Ensure index is clamped when we cannot prove it's less than 2048-bit.
 define <vscale x 8 x i16> @splice_nxv8i16_clamped_idx(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) #0 {
 ; CHECK-LABEL: splice_nxv8i16_clamped_idx:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    str x29, [sp, #-16]! // 8-byte Folded Spill
 ; CHECK-NEXT:    addvl sp, sp, #-2
 ; CHECK-NEXT:    cnth x8
-; CHECK-NEXT:    mov x9, sp
+; CHECK-NEXT:    mov w9, #128
 ; CHECK-NEXT:    sub x8, x8, #1
-; CHECK-NEXT:    mov w10, #128
-; CHECK-NEXT:    cmp x8, #128
 ; CHECK-NEXT:    ptrue p0.h
-; CHECK-NEXT:    csel x8, x8, x10, lo
+; CHECK-NEXT:    cmp x8, #128
 ; CHECK-NEXT:    st1h { z0.h }, p0, [sp]
-; CHECK-NEXT:    st1h { z1.h }, p0, [x9, #1, mul vl]
+; CHECK-NEXT:    csel x8, x8, x9, lo
+; CHECK-NEXT:    mov x9, sp
+; CHECK-NEXT:    st1h { z1.h }, p0, [sp, #1, mul vl]
 ; CHECK-NEXT:    ld1h { z0.h }, p0/z, [x9, x8, lsl #1]
 ; CHECK-NEXT:    addvl sp, sp, #2
 ; CHECK-NEXT:    ldr x29, [sp], #16 // 8-byte Folded Reload
 ; CHECK-NEXT:    ret
   %res = call <vscale x 8 x i16> @llvm.experimental.vector.splice.nxv8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b, i32 128)
   ret <vscale x 8 x i16> %res
 }
 

 
 ; Ensure index is clamped when we cannot prove it's less than 2048-bit.
 define <vscale x 4 x i32> @splice_nxv4i32_clamped_idx(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {
 ; CHECK-LABEL: splice_nxv4i32_clamped_idx:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    str x29, [sp, #-16]! // 8-byte Folded Spill
 ; CHECK-NEXT:    addvl sp, sp, #-2
 ; CHECK-NEXT:    cntw x8
-; CHECK-NEXT:    mov x9, sp
+; CHECK-NEXT:    mov w9, #64
 ; CHECK-NEXT:    sub x8, x8, #1
-; CHECK-NEXT:    mov w10, #64
-; CHECK-NEXT:    cmp x8, #64
 ; CHECK-NEXT:    ptrue p0.s
-; CHECK-NEXT:    csel x8, x8, x10, lo
+; CHECK-NEXT:    cmp x8, #64
 ; CHECK-NEXT:    st1w { z0.s }, p0, [sp]
-; CHECK-NEXT:    st1w { z1.s }, p0, [x9, #1, mul vl]
+; CHECK-NEXT:    csel x8, x8, x9, lo
+; CHECK-NEXT:    mov x9, sp
+; CHECK-NEXT:    st1w { z1.s }, p0, [sp, #1, mul vl]
 ; CHECK-NEXT:    ld1w { z0.s }, p0/z, [x9, x8, lsl #2]
 ; CHECK-NEXT:    addvl sp, sp, #2
 ; CHECK-NEXT:    ldr x29, [sp], #16 // 8-byte Folded Reload
 ; CHECK-NEXT:    ret
   %res = call <vscale x 4 x i32> @llvm.experimental.vector.splice.nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, i32 64)
   ret <vscale x 4 x i32> %res
 }
 

 
 ; Ensure index is clamped when we cannot prove it's less than 2048-bit.
 define <vscale x 2 x i64> @splice_nxv2i64_clamped_idx(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) #0 {
 ; CHECK-LABEL: splice_nxv2i64_clamped_idx:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    str x29, [sp, #-16]! // 8-byte Folded Spill
 ; CHECK-NEXT:    addvl sp, sp, #-2
 ; CHECK-NEXT:    cntd x8
-; CHECK-NEXT:    mov x9, sp
+; CHECK-NEXT:    mov w9, #32
 ; CHECK-NEXT:    sub x8, x8, #1
-; CHECK-NEXT:    mov w10, #32
-; CHECK-NEXT:    cmp x8, #32
 ; CHECK-NEXT:    ptrue p0.d
-; CHECK-NEXT:    csel x8, x8, x10, lo
+; CHECK-NEXT:    cmp x8, #32
 ; CHECK-NEXT:    st1d { z0.d }, p0, [sp]
-; CHECK-NEXT:    st1d { z1.d }, p0, [x9, #1, mul vl]
+; CHECK-NEXT:    csel x8, x8, x9, lo
+; CHECK-NEXT:    mov x9, sp
+; CHECK-NEXT:    st1d { z1.d }, p0, [sp, #1, mul vl]
 ; CHECK-NEXT:    ld1d { z0.d }, p0/z, [x9, x8, lsl #3]
 ; CHECK-NEXT:    addvl sp, sp, #2
 ; CHECK-NEXT:    ldr x29, [sp], #16 // 8-byte Folded Reload
 ; CHECK-NEXT:    ret
   %res = call <vscale x 2 x i64> @llvm.experimental.vector.splice.nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b, i32 32)
   ret <vscale x 2 x i64> %res
 }
 

 ; CHECK-LABEL: splice_nxv2f16_neg2_idx:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    str x29, [sp, #-16]! // 8-byte Folded Spill
 ; CHECK-NEXT:    addvl sp, sp, #-2
 ; CHECK-NEXT:    mov x8, sp
 ; CHECK-NEXT:    mov x9, #-8
 ; CHECK-NEXT:    ptrue p0.h
 ; CHECK-NEXT:    st1h { z0.h }, p0, [sp]
-; CHECK-NEXT:    st1h { z1.h }, p0, [x8, #1, mul vl]
+; CHECK-NEXT:    st1h { z1.h }, p0, [sp, #1, mul vl]
 ; CHECK-NEXT:    addvl x8, x8, #1
 ; CHECK-NEXT:    ld1h { z0.h }, p0/z, [x8, x9, lsl #1]
 ; CHECK-NEXT:    addvl sp, sp, #2
 ; CHECK-NEXT:    ldr x29, [sp], #16 // 8-byte Folded Reload
 ; CHECK-NEXT:    ret
   %res = call <vscale x 2 x half> @llvm.experimental.vector.splice.nxv2f16(<vscale x 2 x half> %a, <vscale x 2 x half> %b, i32 -2)
   ret <vscale x 2 x half> %res
 }

 define <vscale x 2 x half> @splice_nxv2f16_clamped_idx(<vscale x 2 x half> %a, <vscale x 2 x half> %b) #0 {
 ; CHECK-LABEL: splice_nxv2f16_clamped_idx:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    str x29, [sp, #-16]! // 8-byte Folded Spill
 ; CHECK-NEXT:    addvl sp, sp, #-2
 ; CHECK-NEXT:    cntd x8
 ; CHECK-NEXT:    mov w9, #32
 ; CHECK-NEXT:    sub x8, x8, #1
-; CHECK-NEXT:    mov x10, sp
-; CHECK-NEXT:    cmp x8, #32
 ; CHECK-NEXT:    ptrue p0.h
-; CHECK-NEXT:    csel x8, x8, x9, lo
+; CHECK-NEXT:    cmp x8, #32
 ; CHECK-NEXT:    st1h { z0.h }, p0, [sp]
+; CHECK-NEXT:    csel x8, x8, x9, lo
+; CHECK-NEXT:    mov x9, sp
 ; CHECK-NEXT:    lsl x8, x8, #3
-; CHECK-NEXT:    st1h { z1.h }, p0, [x10, #1, mul vl]
+; CHECK-NEXT:    st1h { z1.h }, p0, [sp, #1, mul vl]
 ; CHECK-NEXT:    ptrue p0.b
-; CHECK-NEXT:    ld1b { z0.b }, p0/z, [x10, x8]
+; CHECK-NEXT:    ld1b { z0.b }, p0/z, [x9, x8]
 ; CHECK-NEXT:    addvl sp, sp, #2
 ; CHECK-NEXT:    ldr x29, [sp], #16 // 8-byte Folded Reload
 ; CHECK-NEXT:    ret
   %res = call <vscale x 2 x half> @llvm.experimental.vector.splice.nxv2f16(<vscale x 2 x half> %a, <vscale x 2 x half> %b, i32 32)
   ret <vscale x 2 x half> %res
 }
 
 define <vscale x 4 x half> @splice_nxv4f16_neg_idx(<vscale x 4 x half> %a, <vscale x 4 x half> %b) #0 {

 ; CHECK-LABEL: splice_nxv4f16_neg3_idx:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    str x29, [sp, #-16]! // 8-byte Folded Spill
 ; CHECK-NEXT:    addvl sp, sp, #-2
 ; CHECK-NEXT:    mov x8, sp
 ; CHECK-NEXT:    mov x9, #-6
 ; CHECK-NEXT:    ptrue p0.h
 ; CHECK-NEXT:    st1h { z0.h }, p0, [sp]
-; CHECK-NEXT:    st1h { z1.h }, p0, [x8, #1, mul vl]
+; CHECK-NEXT:    st1h { z1.h }, p0, [sp, #1, mul vl]
 ; CHECK-NEXT:    addvl x8, x8, #1
 ; CHECK-NEXT:    ld1h { z0.h }, p0/z, [x8, x9, lsl #1]
 ; CHECK-NEXT:    addvl sp, sp, #2
 ; CHECK-NEXT:    ldr x29, [sp], #16 // 8-byte Folded Reload
 ; CHECK-NEXT:    ret
   %res = call <vscale x 4 x half> @llvm.experimental.vector.splice.nxv4f16(<vscale x 4 x half> %a, <vscale x 4 x half> %b, i32 -3)
   ret <vscale x 4 x half> %res
 }

 define <vscale x 4 x half> @splice_nxv4f16_clamped_idx(<vscale x 4 x half> %a, <vscale x 4 x half> %b) #0 {
 ; CHECK-LABEL: splice_nxv4f16_clamped_idx:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    str x29, [sp, #-16]! // 8-byte Folded Spill
 ; CHECK-NEXT:    addvl sp, sp, #-2
 ; CHECK-NEXT:    cntw x8
 ; CHECK-NEXT:    mov w9, #64
 ; CHECK-NEXT:    sub x8, x8, #1
-; CHECK-NEXT:    mov x10, sp
-; CHECK-NEXT:    cmp x8, #64
 ; CHECK-NEXT:    ptrue p0.h
-; CHECK-NEXT:    csel x8, x8, x9, lo
+; CHECK-NEXT:    cmp x8, #64
 ; CHECK-NEXT:    st1h { z0.h }, p0, [sp]
+; CHECK-NEXT:    csel x8, x8, x9, lo
+; CHECK-NEXT:    mov x9, sp
 ; CHECK-NEXT:    lsl x8, x8, #2
-; CHECK-NEXT:    st1h { z1.h }, p0, [x10, #1, mul vl]
+; CHECK-NEXT:    st1h { z1.h }, p0, [sp, #1, mul vl]
 ; CHECK-NEXT:    ptrue p0.b
-; CHECK-NEXT:    ld1b { z0.b }, p0/z, [x10, x8]
+; CHECK-NEXT:    ld1b { z0.b }, p0/z, [x9, x8]
 ; CHECK-NEXT:    addvl sp, sp, #2
 ; CHECK-NEXT:    ldr x29, [sp], #16 // 8-byte Folded Reload
 ; CHECK-NEXT:    ret
   %res = call <vscale x 4 x half> @llvm.experimental.vector.splice.nxv4f16(<vscale x 4 x half> %a, <vscale x 4 x half> %b, i32 64)
   ret <vscale x 4 x half> %res
 }
 
 define <vscale x 8 x half> @splice_nxv8f16_first_idx(<vscale x 8 x half> %a, <vscale x 8 x half> %b) #0 {

 
 ; Ensure index is clamped when we cannot prove it's less than 2048-bit.
 define <vscale x 8 x half> @splice_nxv8f16_clamped_idx(<vscale x 8 x half> %a, <vscale x 8 x half> %b) #0 {
 ; CHECK-LABEL: splice_nxv8f16_clamped_idx:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    str x29, [sp, #-16]! // 8-byte Folded Spill
 ; CHECK-NEXT:    addvl sp, sp, #-2
 ; CHECK-NEXT:    cnth x8
-; CHECK-NEXT:    mov x9, sp
+; CHECK-NEXT:    mov w9, #128
 ; CHECK-NEXT:    sub x8, x8, #1
-; CHECK-NEXT:    mov w10, #128
-; CHECK-NEXT:    cmp x8, #128
 ; CHECK-NEXT:    ptrue p0.h
-; CHECK-NEXT:    csel x8, x8, x10, lo
+; CHECK-NEXT:    cmp x8, #128
 ; CHECK-NEXT:    st1h { z0.h }, p0, [sp]
-; CHECK-NEXT:    st1h { z1.h }, p0, [x9, #1, mul vl]
+; CHECK-NEXT:    csel x8, x8, x9, lo
+; CHECK-NEXT:    mov x9, sp
+; CHECK-NEXT:    st1h { z1.h }, p0, [sp, #1, mul vl]
 ; CHECK-NEXT:    ld1h { z0.h }, p0/z, [x9, x8, lsl #1]
 ; CHECK-NEXT:    addvl sp, sp, #2
 ; CHECK-NEXT:    ldr x29, [sp], #16 // 8-byte Folded Reload
 ; CHECK-NEXT:    ret
   %res = call <vscale x 8 x half> @llvm.experimental.vector.splice.nxv8f16(<vscale x 8 x half> %a, <vscale x 8 x half> %b, i32 128)
   ret <vscale x 8 x half> %res
 }
 

 ; CHECK-LABEL: splice_nxv2f32_neg2_idx:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    str x29, [sp, #-16]! // 8-byte Folded Spill
 ; CHECK-NEXT:    addvl sp, sp, #-2
 ; CHECK-NEXT:    mov x8, sp
 ; CHECK-NEXT:    mov x9, #-4
 ; CHECK-NEXT:    ptrue p0.s
 ; CHECK-NEXT:    st1w { z0.s }, p0, [sp]
-; CHECK-NEXT:    st1w { z1.s }, p0, [x8, #1, mul vl]
+; CHECK-NEXT:    st1w { z1.s }, p0, [sp, #1, mul vl]
 ; CHECK-NEXT:    addvl x8, x8, #1
 ; CHECK-NEXT:    ld1w { z0.s }, p0/z, [x8, x9, lsl #2]
 ; CHECK-NEXT:    addvl sp, sp, #2
 ; CHECK-NEXT:    ldr x29, [sp], #16 // 8-byte Folded Reload
 ; CHECK-NEXT:    ret
   %res = call <vscale x 2 x float> @llvm.experimental.vector.splice.nxv2f32(<vscale x 2 x float> %a, <vscale x 2 x float> %b, i32 -2)
   ret <vscale x 2 x float> %res
 }

 define <vscale x 2 x float> @splice_nxv2f32_clamped_idx(<vscale x 2 x float> %a, <vscale x 2 x float> %b) #0 {
 ; CHECK-LABEL: splice_nxv2f32_clamped_idx:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    str x29, [sp, #-16]! // 8-byte Folded Spill
 ; CHECK-NEXT:    addvl sp, sp, #-2
 ; CHECK-NEXT:    cntd x8
 ; CHECK-NEXT:    mov w9, #32
 ; CHECK-NEXT:    sub x8, x8, #1
-; CHECK-NEXT:    mov x10, sp
-; CHECK-NEXT:    cmp x8, #32
 ; CHECK-NEXT:    ptrue p0.s
-; CHECK-NEXT:    csel x8, x8, x9, lo
+; CHECK-NEXT:    cmp x8, #32
 ; CHECK-NEXT:    st1w { z0.s }, p0, [sp]
+; CHECK-NEXT:    csel x8, x8, x9, lo
+; CHECK-NEXT:    mov x9, sp
 ; CHECK-NEXT:    lsl x8, x8, #3
-; CHECK-NEXT:    st1w { z1.s }, p0, [x10, #1, mul vl]
+; CHECK-NEXT:    st1w { z1.s }, p0, [sp, #1, mul vl]
 ; CHECK-NEXT:    ptrue p0.b
-; CHECK-NEXT:    ld1b { z0.b }, p0/z, [x10, x8]
+; CHECK-NEXT:    ld1b { z0.b }, p0/z, [x9, x8]
 ; CHECK-NEXT:    addvl sp, sp, #2
 ; CHECK-NEXT:    ldr x29, [sp], #16 // 8-byte Folded Reload
 ; CHECK-NEXT:    ret
   %res = call <vscale x 2 x float> @llvm.experimental.vector.splice.nxv2f32(<vscale x 2 x float> %a, <vscale x 2 x float> %b, i32 32)
   ret <vscale x 2 x float> %res
 }
 
 define <vscale x 4 x float> @splice_nxv4f32_first_idx(<vscale x 4 x float> %a, <vscale x 4 x float> %b) #0 {

 
 ; Ensure index is clamped when we cannot prove it's less than 2048-bit.
 define <vscale x 4 x float> @splice_nxv4f32_clamped_idx(<vscale x 4 x float> %a, <vscale x 4 x float> %b) #0 {
 ; CHECK-LABEL: splice_nxv4f32_clamped_idx:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    str x29, [sp, #-16]! // 8-byte Folded Spill
 ; CHECK-NEXT:    addvl sp, sp, #-2
 ; CHECK-NEXT:    cntw x8
-; CHECK-NEXT:    mov x9, sp
+; CHECK-NEXT:    mov w9, #64
 ; CHECK-NEXT:    sub x8, x8, #1
-; CHECK-NEXT:    mov w10, #64
-; CHECK-NEXT:    cmp x8, #64
 ; CHECK-NEXT:    ptrue p0.s
-; CHECK-NEXT:    csel x8, x8, x10, lo
+; CHECK-NEXT:    cmp x8, #64
 ; CHECK-NEXT:    st1w { z0.s }, p0, [sp]
-; CHECK-NEXT:    st1w { z1.s }, p0, [x9, #1, mul vl]
+; CHECK-NEXT:    csel x8, x8, x9, lo
+; CHECK-NEXT:    mov x9, sp
+; CHECK-NEXT:    st1w { z1.s }, p0, [sp, #1, mul vl]
 ; CHECK-NEXT:    ld1w { z0.s }, p0/z, [x9, x8, lsl #2]
 ; CHECK-NEXT:    addvl sp, sp, #2
 ; CHECK-NEXT:    ldr x29, [sp], #16 // 8-byte Folded Reload
 ; CHECK-NEXT:    ret
   %res = call <vscale x 4 x float> @llvm.experimental.vector.splice.nxv4f32(<vscale x 4 x float> %a, <vscale x 4 x float> %b, i32 64)
   ret <vscale x 4 x float> %res
 }
 

 
 ; Ensure index is clamped when we cannot prove it's less than 2048-bit.
 define <vscale x 2 x double> @splice_nxv2f64_clamped_idx(<vscale x 2 x double> %a, <vscale x 2 x double> %b) #0 {
 ; CHECK-LABEL: splice_nxv2f64_clamped_idx:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    str x29, [sp, #-16]! // 8-byte Folded Spill
 ; CHECK-NEXT:    addvl sp, sp, #-2
 ; CHECK-NEXT:    cntd x8
-; CHECK-NEXT:    mov x9, sp
+; CHECK-NEXT:    mov w9, #32
 ; CHECK-NEXT:    sub x8, x8, #1
-; CHECK-NEXT:    mov w10, #32
-; CHECK-NEXT:    cmp x8, #32
 ; CHECK-NEXT:    ptrue p0.d
-; CHECK-NEXT:    csel x8, x8, x10, lo
+; CHECK-NEXT:    cmp x8, #32
 ; CHECK-NEXT:    st1d { z0.d }, p0, [sp]
-; CHECK-NEXT:    st1d { z1.d }, p0, [x9, #1, mul vl]
+; CHECK-NEXT:    csel x8, x8, x9, lo
+; CHECK-NEXT:    mov x9, sp
+; CHECK-NEXT:    st1d { z1.d }, p0, [sp, #1, mul vl]
 ; CHECK-NEXT:    ld1d { z0.d }, p0/z, [x9, x8, lsl #3]
 ; CHECK-NEXT:    addvl sp, sp, #2
 ; CHECK-NEXT:    ldr x29, [sp], #16 // 8-byte Folded Reload
 ; CHECK-NEXT:    ret
   %res = call <vscale x 2 x double> @llvm.experimental.vector.splice.nxv2f64(<vscale x 2 x double> %a, <vscale x 2 x double> %b, i32 32)
   ret <vscale x 2 x double> %res
 }
 

 ; Verify splitvec type legalisation works as expected.
 define <vscale x 8 x i32> @splice_nxv8i32_idx(<vscale x 8 x i32> %a, <vscale x 8 x i32> %b) #0 {
 ; CHECK-LABEL: splice_nxv8i32_idx:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    str x29, [sp, #-16]! // 8-byte Folded Spill
 ; CHECK-NEXT:    addvl sp, sp, #-4
 ; CHECK-NEXT:    mov x8, sp
 ; CHECK-NEXT:    ptrue p0.s
-; CHECK-NEXT:    orr x9, x8, #0x8
-; CHECK-NEXT:    st1w { z1.s }, p0, [x8, #1, mul vl]
+; CHECK-NEXT:    orr x8, x8, #0x8
+; CHECK-NEXT:    st1w { z1.s }, p0, [sp, #1, mul vl]
 ; CHECK-NEXT:    st1w { z0.s }, p0, [sp]
-; CHECK-NEXT:    st1w { z3.s }, p0, [x8, #3, mul vl]
-; CHECK-NEXT:    st1w { z2.s }, p0, [x8, #2, mul vl]
-; CHECK-NEXT:    ld1w { z0.s }, p0/z, [x9]
-; CHECK-NEXT:    ld1w { z1.s }, p0/z, [x9, #1, mul vl]
+; CHECK-NEXT:    st1w { z3.s }, p0, [sp, #3, mul vl]
+; CHECK-NEXT:    st1w { z2.s }, p0, [sp, #2, mul vl]
+; CHECK-NEXT:    ld1w { z0.s }, p0/z, [x8]
+; CHECK-NEXT:    ld1w { z1.s }, p0/z, [x8, #1, mul vl]
 ; CHECK-NEXT:    addvl sp, sp, #4
 ; CHECK-NEXT:    ldr x29, [sp], #16 // 8-byte Folded Reload
 ; CHECK-NEXT:    ret
   %res = call <vscale x 8 x i32> @llvm.experimental.vector.splice.nxv8i32(<vscale x 8 x i32> %a, <vscale x 8 x i32> %b, i32 2)
   ret <vscale x 8 x i32> %res
 }
 
 ; Verify splitvec type legalisation works as expected.
 define <vscale x 16 x float> @splice_nxv16f32_clamped_idx(<vscale x 16 x float> %a, <vscale x 16 x float> %b) #0 {
 ; CHECK-LABEL: splice_nxv16f32_clamped_idx:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    str x29, [sp, #-16]! // 8-byte Folded Spill
 ; CHECK-NEXT:    addvl sp, sp, #-8
 ; CHECK-NEXT:    mov x8, #-1
-; CHECK-NEXT:    mov w10, #16
-; CHECK-NEXT:    mov x9, sp
+; CHECK-NEXT:    mov w9, #16
 ; CHECK-NEXT:    ptrue p0.s
+; CHECK-NEXT:    st1w { z3.s }, p0, [sp, #3, mul vl]
+; CHECK-NEXT:    st1w { z2.s }, p0, [sp, #2, mul vl]
 ; CHECK-NEXT:    addvl x8, x8, #1
+; CHECK-NEXT:    st1w { z1.s }, p0, [sp, #1, mul vl]
 ; CHECK-NEXT:    cmp x8, #16
-; CHECK-NEXT:    st1w { z3.s }, p0, [x9, #3, mul vl]
-; CHECK-NEXT:    csel x8, x8, x10, lo
-; CHECK-NEXT:    st1w { z2.s }, p0, [x9, #2, mul vl]
-; CHECK-NEXT:    st1w { z1.s }, p0, [x9, #1, mul vl]
 ; CHECK-NEXT:    st1w { z0.s }, p0, [sp]
+; CHECK-NEXT:    csel x8, x8, x9, lo
+; CHECK-NEXT:    mov x9, sp
+; CHECK-NEXT:    st1w { z7.s }, p0, [sp, #7, mul vl]
+; CHECK-NEXT:    st1w { z4.s }, p0, [sp, #4, mul vl]
 ; CHECK-NEXT:    add x10, x9, x8, lsl #2
-; CHECK-NEXT:    st1w { z7.s }, p0, [x9, #7, mul vl]
-; CHECK-NEXT:    st1w { z4.s }, p0, [x9, #4, mul vl]
-; CHECK-NEXT:    st1w { z5.s }, p0, [x9, #5, mul vl]
-; CHECK-NEXT:    st1w { z6.s }, p0, [x9, #6, mul vl]
+; CHECK-NEXT:    st1w { z5.s }, p0, [sp, #5, mul vl]
+; CHECK-NEXT:    st1w { z6.s }, p0, [sp, #6, mul vl]
 ; CHECK-NEXT:    ld1w { z0.s }, p0/z, [x9, x8, lsl #2]
 ; CHECK-NEXT:    ld1w { z1.s }, p0/z, [x10, #1, mul vl]
 ; CHECK-NEXT:    ld1w { z2.s }, p0/z, [x10, #2, mul vl]
 ; CHECK-NEXT:    ld1w { z3.s }, p0/z, [x10, #3, mul vl]
 ; CHECK-NEXT:    addvl sp, sp, #8
 ; CHECK-NEXT:    ldr x29, [sp], #16 // 8-byte Folded Reload
 ; CHECK-NEXT:    ret
   %res = call <vscale x 16 x float> @llvm.experimental.vector.splice.nxv16f32(<vscale x 16 x float> %a, <vscale x 16 x float> %b, i32 16)
   ret <vscale x 16 x float> %res
 }
 
 ;
 ; VECTOR_SPLICE (trailing elements)
 ;
 
 define <vscale x 16 x i8> @splice_nxv16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) #0 {
 ; CHECK-LABEL: splice_nxv16i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    str x29, [sp, #-16]! // 8-byte Folded Spill
 ; CHECK-NEXT:    addvl sp, sp, #-2
 ; CHECK-NEXT:    mov x8, sp
 ; CHECK-NEXT:    mov x9, #-16
 ; CHECK-NEXT:    ptrue p0.b
 ; CHECK-NEXT:    st1b { z0.b }, p0, [sp]
-; CHECK-NEXT:    st1b { z1.b }, p0, [x8, #1, mul vl]
+; CHECK-NEXT:    st1b { z1.b }, p0, [sp, #1, mul vl]
 ; CHECK-NEXT:    addvl x8, x8, #1
 ; CHECK-NEXT:    ld1b { z0.b }, p0/z, [x8, x9]
 ; CHECK-NEXT:    addvl sp, sp, #2
 ; CHECK-NEXT:    ldr x29, [sp], #16 // 8-byte Folded Reload
 ; CHECK-NEXT:    ret
   %res = call <vscale x 16 x i8> @llvm.experimental.vector.splice.nxv16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b, i32 -16)
   ret <vscale x 16 x i8> %res
 }

 ; CHECK-NEXT:    str x29, [sp, #-16]! // 8-byte Folded Spill
 ; CHECK-NEXT:    addvl sp, sp, #-2
 ; CHECK-NEXT:    mov x8, sp
 ; CHECK-NEXT:    rdvl x9, #1
 ; CHECK-NEXT:    cmp x9, #17
 ; CHECK-NEXT:    mov w10, #17
 ; CHECK-NEXT:    csel x9, x9, x10, lo
 ; CHECK-NEXT:    ptrue p0.b
-; CHECK-NEXT:    addvl x10, x8, #1
+; CHECK-NEXT:    addvl x8, x8, #1
 ; CHECK-NEXT:    st1b { z0.b }, p0, [sp]
-; CHECK-NEXT:    sub x9, x10, x9
-; CHECK-NEXT:    st1b { z1.b }, p0, [x8, #1, mul vl]
-; CHECK-NEXT:    ld1b { z0.b }, p0/z, [x9]
+; CHECK-NEXT:    sub x8, x8, x9
+; CHECK-NEXT:    st1b { z1.b }, p0, [sp, #1, mul vl]
+; CHECK-NEXT:    ld1b { z0.b }, p0/z, [x8]
 ; CHECK-NEXT:    addvl sp, sp, #2
 ; CHECK-NEXT:    ldr x29, [sp], #16 // 8-byte Folded Reload
 ; CHECK-NEXT:    ret
   %res = call <vscale x 16 x i8> @llvm.experimental.vector.splice.nxv16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b, i32 -17)
   ret <vscale x 16 x i8> %res
 }
 
 define <vscale x 8 x i16> @splice_nxv8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) #0 {
 ; CHECK-LABEL: splice_nxv8i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    str x29, [sp, #-16]! // 8-byte Folded Spill
 ; CHECK-NEXT:    addvl sp, sp, #-2
 ; CHECK-NEXT:    mov x8, sp
 ; CHECK-NEXT:    mov x9, #-8
 ; CHECK-NEXT:    ptrue p0.h
 ; CHECK-NEXT:    st1h { z0.h }, p0, [sp]
-; CHECK-NEXT:    st1h { z1.h }, p0, [x8, #1, mul vl]
+; CHECK-NEXT:    st1h { z1.h }, p0, [sp, #1, mul vl]
 ; CHECK-NEXT:    addvl x8, x8, #1
 ; CHECK-NEXT:    ld1h { z0.h }, p0/z, [x8, x9, lsl #1]
 ; CHECK-NEXT:    addvl sp, sp, #2
 ; CHECK-NEXT:    ldr x29, [sp], #16 // 8-byte Folded Reload
 ; CHECK-NEXT:    ret
   %res = call <vscale x 8 x i16> @llvm.experimental.vector.splice.nxv8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b, i32 -8)
   ret <vscale x 8 x i16> %res
 }

 ; CHECK-NEXT:    str x29, [sp, #-16]! // 8-byte Folded Spill
 ; CHECK-NEXT:    addvl sp, sp, #-2
 ; CHECK-NEXT:    mov x8, sp
 ; CHECK-NEXT:    rdvl x9, #1
 ; CHECK-NEXT:    cmp x9, #18
 ; CHECK-NEXT:    mov w10, #18
 ; CHECK-NEXT:    csel x9, x9, x10, lo
 ; CHECK-NEXT:    ptrue p0.h
-; CHECK-NEXT:    addvl x10, x8, #1
+; CHECK-NEXT:    addvl x8, x8, #1
 ; CHECK-NEXT:    st1h { z0.h }, p0, [sp]
-; CHECK-NEXT:    sub x9, x10, x9
-; CHECK-NEXT:    st1h { z1.h }, p0, [x8, #1, mul vl]
-; CHECK-NEXT:    ld1h { z0.h }, p0/z, [x9]
+; CHECK-NEXT:    sub x8, x8, x9
+; CHECK-NEXT:    st1h { z1.h }, p0, [sp, #1, mul vl]
+; CHECK-NEXT:    ld1h { z0.h }, p0/z, [x8]
 ; CHECK-NEXT:    addvl sp, sp, #2
 ; CHECK-NEXT:    ldr x29, [sp], #16 // 8-byte Folded Reload
 ; CHECK-NEXT:    ret
   %res = call <vscale x 8 x i16> @llvm.experimental.vector.splice.nxv8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b, i32 -9)
   ret <vscale x 8 x i16> %res
 }
 
 define <vscale x 4 x i32> @splice_nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {
 ; CHECK-LABEL: splice_nxv4i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    str x29, [sp, #-16]! // 8-byte Folded Spill
 ; CHECK-NEXT:    addvl sp, sp, #-2
 ; CHECK-NEXT:    mov x8, sp
 ; CHECK-NEXT:    mov x9, #-4
 ; CHECK-NEXT:    ptrue p0.s
 ; CHECK-NEXT:    st1w { z0.s }, p0, [sp]
-; CHECK-NEXT:    st1w { z1.s }, p0, [x8, #1, mul vl]
+; CHECK-NEXT:    st1w { z1.s }, p0, [sp, #1, mul vl]
 ; CHECK-NEXT:    addvl x8, x8, #1
 ; CHECK-NEXT:    ld1w { z0.s }, p0/z, [x8, x9, lsl #2]
 ; CHECK-NEXT:    addvl sp, sp, #2
 ; CHECK-NEXT:    ldr x29, [sp], #16 // 8-byte Folded Reload
 ; CHECK-NEXT:    ret
   %res = call <vscale x 4 x i32> @llvm.experimental.vector.splice.nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, i32 -4)
   ret <vscale x 4 x i32> %res
 }

 ; CHECK-NEXT:    str x29, [sp, #-16]! // 8-byte Folded Spill
 ; CHECK-NEXT:    addvl sp, sp, #-2
 ; CHECK-NEXT:    mov x8, sp
 ; CHECK-NEXT:    rdvl x9, #1
 ; CHECK-NEXT:    cmp x9, #20
 ; CHECK-NEXT:    mov w10, #20
 ; CHECK-NEXT:    csel x9, x9, x10, lo
 ; CHECK-NEXT:    ptrue p0.s
-; CHECK-NEXT:    addvl x10, x8, #1
+; CHECK-NEXT:    addvl x8, x8, #1
 ; CHECK-NEXT:    st1w { z0.s }, p0, [sp]
-; CHECK-NEXT:    sub x9, x10, x9
-; CHECK-NEXT:    st1w { z1.s }, p0, [x8, #1, mul vl]
-; CHECK-NEXT:    ld1w { z0.s }, p0/z, [x9]
+; CHECK-NEXT:    sub x8, x8, x9
+; CHECK-NEXT:    st1w { z1.s }, p0, [sp, #1, mul vl]
+; CHECK-NEXT:    ld1w { z0.s }, p0/z, [x8]
 ; CHECK-NEXT:    addvl sp, sp, #2
 ; CHECK-NEXT:    ldr x29, [sp], #16 // 8-byte Folded Reload
 ; CHECK-NEXT:    ret
   %res = call <vscale x 4 x i32> @llvm.experimental.vector.splice.nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, i32 -5)
   ret <vscale x 4 x i32> %res
 }
 
 define <vscale x 2 x i64> @splice_nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) #0 {
 ; CHECK-LABEL: splice_nxv2i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    str x29, [sp, #-16]! // 8-byte Folded Spill
 ; CHECK-NEXT:    addvl sp, sp, #-2
 ; CHECK-NEXT:    mov x8, sp
 ; CHECK-NEXT:    mov x9, #-2
 ; CHECK-NEXT:    ptrue p0.d
 ; CHECK-NEXT:    st1d { z0.d }, p0, [sp]
-; CHECK-NEXT:    st1d { z1.d }, p0, [x8, #1, mul vl]
+; CHECK-NEXT:    st1d { z1.d }, p0, [sp, #1, mul vl]
 ; CHECK-NEXT:    addvl x8, x8, #1
 ; CHECK-NEXT:    ld1d { z0.d }, p0/z, [x8, x9, lsl #3]
 ; CHECK-NEXT:    addvl sp, sp, #2
 ; CHECK-NEXT:    ldr x29, [sp], #16 // 8-byte Folded Reload
 ; CHECK-NEXT:    ret
   %res = call <vscale x 2 x i64> @llvm.experimental.vector.splice.nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b, i32 -2)
   ret <vscale x 2 x i64> %res
 }

 ; CHECK-NEXT:    str x29, [sp, #-16]! // 8-byte Folded Spill
 ; CHECK-NEXT:    addvl sp, sp, #-2
 ; CHECK-NEXT:    mov x8, sp
 ; CHECK-NEXT:    rdvl x9, #1
 ; CHECK-NEXT:    cmp x9, #24
 ; CHECK-NEXT:    mov w10, #24
 ; CHECK-NEXT:    csel x9, x9, x10, lo
 ; CHECK-NEXT:    ptrue p0.d
-; CHECK-NEXT:    addvl x10, x8, #1
+; CHECK-NEXT:    addvl x8, x8, #1
 ; CHECK-NEXT:    st1d { z0.d }, p0, [sp]
-; CHECK-NEXT:    sub x9, x10, x9
-; CHECK-NEXT:    st1d { z1.d }, p0, [x8, #1, mul vl]
-; CHECK-NEXT:    ld1d { z0.d }, p0/z, [x9]
+; CHECK-NEXT:    sub x8, x8, x9
+; CHECK-NEXT:    st1d { z1.d }, p0, [sp, #1, mul vl]
+; CHECK-NEXT:    ld1d { z0.d }, p0/z, [x8]
 ; CHECK-NEXT:    addvl sp, sp, #2
 ; CHECK-NEXT:    ldr x29, [sp], #16 // 8-byte Folded Reload
 ; CHECK-NEXT:    ret
   %res = call <vscale x 2 x i64> @llvm.experimental.vector.splice.nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b, i32 -3)
   ret <vscale x 2 x i64> %res
 }
 
 define <vscale x 8 x half> @splice_nxv8f16(<vscale x 8 x half> %a, <vscale x 8 x half> %b) #0 {
 ; CHECK-LABEL: splice_nxv8f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    str x29, [sp, #-16]! // 8-byte Folded Spill
 ; CHECK-NEXT:    addvl sp, sp, #-2
 ; CHECK-NEXT:    mov x8, sp
 ; CHECK-NEXT:    mov x9, #-8
 ; CHECK-NEXT:    ptrue p0.h
 ; CHECK-NEXT:    st1h { z0.h }, p0, [sp]
-; CHECK-NEXT:    st1h { z1.h }, p0, [x8, #1, mul vl]
+; CHECK-NEXT:    st1h { z1.h }, p0, [sp, #1, mul vl]
 ; CHECK-NEXT:    addvl x8, x8, #1
 ; CHECK-NEXT:    ld1h { z0.h }, p0/z, [x8, x9, lsl #1]
 ; CHECK-NEXT:    addvl sp, sp, #2
 ; CHECK-NEXT:    ldr x29, [sp], #16 // 8-byte Folded Reload
 ; CHECK-NEXT:    ret
   %res = call <vscale x 8 x half> @llvm.experimental.vector.splice.nxv8f16(<vscale x 8 x half> %a, <vscale x 8 x half> %b, i32 -8)
   ret <vscale x 8 x half> %res
 }

 ; CHECK-NEXT:    str x29, [sp, #-16]! // 8-byte Folded Spill
 ; CHECK-NEXT:    addvl sp, sp, #-2
 ; CHECK-NEXT:    mov x8, sp
 ; CHECK-NEXT:    rdvl x9, #1
 ; CHECK-NEXT:    cmp x9, #18
 ; CHECK-NEXT:    mov w10, #18
 ; CHECK-NEXT:    csel x9, x9, x10, lo
 ; CHECK-NEXT:    ptrue p0.h
-; CHECK-NEXT:    addvl x10, x8, #1
+; CHECK-NEXT:    addvl x8, x8, #1
 ; CHECK-NEXT:    st1h { z0.h }, p0, [sp]
-; CHECK-NEXT:    sub x9, x10, x9
-; CHECK-NEXT:    st1h { z1.h }, p0, [x8, #1, mul vl]
-; CHECK-NEXT:    ld1h { z0.h }, p0/z, [x9]
+; CHECK-NEXT:    sub x8, x8, x9
+; CHECK-NEXT:    st1h { z1.h }, p0, [sp, #1, mul vl]
+; CHECK-NEXT:    ld1h { z0.h }, p0/z, [x8]
 ; CHECK-NEXT:    addvl sp, sp, #2
 ; CHECK-NEXT:    ldr x29, [sp], #16 // 8-byte Folded Reload
 ; CHECK-NEXT:    ret
   %res = call <vscale x 8 x half> @llvm.experimental.vector.splice.nxv8f16(<vscale x 8 x half> %a, <vscale x 8 x half> %b, i32 -9)
   ret <vscale x 8 x half> %res
 }
 
 define <vscale x 4 x float> @splice_nxv4f32(<vscale x 4 x float> %a, <vscale x 4 x float> %b) #0 {
 ; CHECK-LABEL: splice_nxv4f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    str x29, [sp, #-16]! // 8-byte Folded Spill
 ; CHECK-NEXT:    addvl sp, sp, #-2
 ; CHECK-NEXT:    mov x8, sp
 ; CHECK-NEXT:    mov x9, #-4
 ; CHECK-NEXT:    ptrue p0.s
 ; CHECK-NEXT:    st1w { z0.s }, p0, [sp]
-; CHECK-NEXT:    st1w { z1.s }, p0, [x8, #1, mul vl]
+; CHECK-NEXT:    st1w { z1.s }, p0, [sp, #1, mul vl]
 ; CHECK-NEXT:    addvl x8, x8, #1
 ; CHECK-NEXT:    ld1w { z0.s }, p0/z, [x8, x9, lsl #2]
 ; CHECK-NEXT:    addvl sp, sp, #2
 ; CHECK-NEXT:    ldr x29, [sp], #16 // 8-byte Folded Reload
 ; CHECK-NEXT:    ret
   %res = call <vscale x 4 x float> @llvm.experimental.vector.splice.nxv4f32(<vscale x 4 x float> %a, <vscale x 4 x float> %b, i32 -4)
   ret <vscale x 4 x float> %res
 }

 ; CHECK-NEXT:    str x29, [sp, #-16]! // 8-byte Folded Spill
 ; CHECK-NEXT:    addvl sp, sp, #-2
 ; CHECK-NEXT:    mov x8, sp
 ; CHECK-NEXT:    rdvl x9, #1
 ; CHECK-NEXT:    cmp x9, #20
 ; CHECK-NEXT:    mov w10, #20
 ; CHECK-NEXT:    csel x9, x9, x10, lo
 ; CHECK-NEXT:    ptrue p0.s
-; CHECK-NEXT:    addvl x10, x8, #1
+; CHECK-NEXT:    addvl x8, x8, #1
 ; CHECK-NEXT:    st1w { z0.s }, p0, [sp]
-; CHECK-NEXT:    sub x9, x10, x9
-; CHECK-NEXT:    st1w { z1.s }, p0, [x8, #1, mul vl]
-; CHECK-NEXT:    ld1w { z0.s }, p0/z, [x9]
+; CHECK-NEXT:    sub x8, x8, x9
+; CHECK-NEXT:    st1w { z1.s }, p0, [sp, #1, mul vl]
+; CHECK-NEXT:    ld1w { z0.s }, p0/z, [x8]
 ; CHECK-NEXT:    addvl sp, sp, #2
 ; CHECK-NEXT:    ldr x29, [sp], #16 // 8-byte Folded Reload
 ; CHECK-NEXT:    ret
   %res = call <vscale x 4 x float> @llvm.experimental.vector.splice.nxv4f32(<vscale x 4 x float> %a, <vscale x 4 x float> %b, i32 -5)
   ret <vscale x 4 x float> %res
 }
 
 define <vscale x 2 x double> @splice_nxv2f64(<vscale x 2 x double> %a, <vscale x 2 x double> %b) #0 {
 ; CHECK-LABEL: splice_nxv2f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    str x29, [sp, #-16]! // 8-byte Folded Spill
 ; CHECK-NEXT:    addvl sp, sp, #-2
 ; CHECK-NEXT:    mov x8, sp
 ; CHECK-NEXT:    mov x9, #-2
 ; CHECK-NEXT:    ptrue p0.d
 ; CHECK-NEXT:    st1d { z0.d }, p0, [sp]
-; CHECK-NEXT:    st1d { z1.d }, p0, [x8, #1, mul vl]
+; CHECK-NEXT:    st1d { z1.d }, p0, [sp, #1, mul vl]
 ; CHECK-NEXT:    addvl x8, x8, #1
 ; CHECK-NEXT:    ld1d { z0.d }, p0/z, [x8, x9, lsl #3]
 ; CHECK-NEXT:    addvl sp, sp, #2
 ; CHECK-NEXT:    ldr x29, [sp], #16 // 8-byte Folded Reload
 ; CHECK-NEXT:    ret
   %res = call <vscale x 2 x double> @llvm.experimental.vector.splice.nxv2f64(<vscale x 2 x double> %a, <vscale x 2 x double> %b, i32 -2)
   ret <vscale x 2 x double> %res
 }

 ; CHECK-NEXT:    str x29, [sp, #-16]! // 8-byte Folded Spill
 ; CHECK-NEXT:    addvl sp, sp, #-2
 ; CHECK-NEXT:    mov x8, sp
 ; CHECK-NEXT:    rdvl x9, #1
 ; CHECK-NEXT:    cmp x9, #24
 ; CHECK-NEXT:    mov w10, #24
 ; CHECK-NEXT:    csel x9, x9, x10, lo
 ; CHECK-NEXT:    ptrue p0.d
-; CHECK-NEXT:    addvl x10, x8, #1
+; CHECK-NEXT:    addvl x8, x8, #1
 ; CHECK-NEXT:    st1d { z0.d }, p0, [sp]
-; CHECK-NEXT:    sub x9, x10, x9
-; CHECK-NEXT:    st1d { z1.d }, p0, [x8, #1, mul vl]
-; CHECK-NEXT:    ld1d { z0.d }, p0/z, [x9]
+; CHECK-NEXT:    sub x8, x8, x9
+; CHECK-NEXT:    st1d { z1.d }, p0, [sp, #1, mul vl]
+; CHECK-NEXT:    ld1d { z0.d }, p0/z, [x8]
 ; CHECK-NEXT:    addvl sp, sp, #2
 ; CHECK-NEXT:    ldr x29, [sp], #16 // 8-byte Folded Reload
 ; CHECK-NEXT:    ret
   %res = call <vscale x 2 x double> @llvm.experimental.vector.splice.nxv2f64(<vscale x 2 x double> %a, <vscale x 2 x double> %b, i32 -3)
   ret <vscale x 2 x double> %res
 }
 
 ; Ensure predicate based splice is promoted to use ZPRs.

 ; CHECK-LABEL: splice_nxv2i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    str x29, [sp, #-16]! // 8-byte Folded Spill
 ; CHECK-NEXT:    addvl sp, sp, #-2
 ; CHECK-NEXT:    mov x8, sp
 ; CHECK-NEXT:    mov x9, #-2
 ; CHECK-NEXT:    ptrue p0.d
 ; CHECK-NEXT:    st1d { z0.d }, p0, [sp]
-; CHECK-NEXT:    st1d { z1.d }, p0, [x8, #1, mul vl]
+; CHECK-NEXT:    st1d { z1.d }, p0, [sp, #1, mul vl]
 ; CHECK-NEXT:    addvl x8, x8, #1
 ; CHECK-NEXT:    ld1d { z0.d }, p0/z, [x8, x9, lsl #3]
 ; CHECK-NEXT:    addvl sp, sp, #2
 ; CHECK-NEXT:    ldr x29, [sp], #16 // 8-byte Folded Reload
 ; CHECK-NEXT:    ret
   %res = call <vscale x 2 x i8> @llvm.experimental.vector.splice.nxv2i8(<vscale x 2 x i8> %a, <vscale x 2 x i8> %b, i32 -2)
   ret <vscale x 2 x i8> %res
 }
 
 ; Verify splitvec type legalisation works as expected.
 define <vscale x 8 x i32> @splice_nxv8i32(<vscale x 8 x i32> %a, <vscale x 8 x i32> %b) #0 {
 ; CHECK-LABEL: splice_nxv8i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    str x29, [sp, #-16]! // 8-byte Folded Spill
 ; CHECK-NEXT:    addvl sp, sp, #-4
 ; CHECK-NEXT:    mov x8, sp
-; CHECK-NEXT:    mov x10, #-8
+; CHECK-NEXT:    mov x9, #-8
 ; CHECK-NEXT:    ptrue p0.s
-; CHECK-NEXT:    addvl x9, x8, #2
-; CHECK-NEXT:    st1w { z1.s }, p0, [x8, #1, mul vl]
-; CHECK-NEXT:    sub x11, x9, #32
+; CHECK-NEXT:    st1w { z1.s }, p0, [sp, #1, mul vl]
 ; CHECK-NEXT:    st1w { z0.s }, p0, [sp]
-; CHECK-NEXT:    st1w { z3.s }, p0, [x8, #3, mul vl]
-; CHECK-NEXT:    st1w { z2.s }, p0, [x8, #2, mul vl]
-; CHECK-NEXT:    ld1w { z0.s }, p0/z, [x9, x10, lsl #2]
-; CHECK-NEXT:    ld1w { z1.s }, p0/z, [x11, #1, mul vl]
+; CHECK-NEXT:    addvl x8, x8, #2
+; CHECK-NEXT:    st1w { z3.s }, p0, [sp, #3, mul vl]
+; CHECK-NEXT:    sub x10, x8, #32
+; CHECK-NEXT:    st1w { z2.s }, p0, [sp, #2, mul vl]
+; CHECK-NEXT:    ld1w { z0.s }, p0/z, [x8, x9, lsl #2]
+; CHECK-NEXT:    ld1w { z1.s }, p0/z, [x10, #1, mul vl]
 ; CHECK-NEXT:    addvl sp, sp, #4
 ; CHECK-NEXT:    ldr x29, [sp], #16 // 8-byte Folded Reload
 ; CHECK-NEXT:    ret
   %res = call <vscale x 8 x i32> @llvm.experimental.vector.splice.nxv8i32(<vscale x 8 x i32> %a, <vscale x 8 x i32> %b, i32 -8)
   ret <vscale x 8 x i32> %res
 }
 
 ; Verify splitvec type legalisation works as expected.
 define <vscale x 16 x float> @splice_nxv16f32_clamped(<vscale x 16 x float> %a, <vscale x 16 x float> %b) #0 {
 ; CHECK-LABEL: splice_nxv16f32_clamped:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    str x29, [sp, #-16]! // 8-byte Folded Spill
 ; CHECK-NEXT:    addvl sp, sp, #-8
-; CHECK-NEXT:    mov x8, sp
-; CHECK-NEXT:    rdvl x9, #4
-; CHECK-NEXT:    cmp x9, #68
-; CHECK-NEXT:    mov w10, #68
-; CHECK-NEXT:    csel x9, x9, x10, lo
+; CHECK-NEXT:    mov x10, sp
+; CHECK-NEXT:    rdvl x8, #4
+; CHECK-NEXT:    cmp x8, #68
+; CHECK-NEXT:    mov w9, #68
+; CHECK-NEXT:    csel x8, x8, x9, lo
 ; CHECK-NEXT:    ptrue p0.s
-; CHECK-NEXT:    addvl x10, x8, #4
-; CHECK-NEXT:    st1w { z3.s }, p0, [x8, #3, mul vl]
-; CHECK-NEXT:    sub x9, x10, x9
-; CHECK-NEXT:    st1w { z2.s }, p0, [x8, #2, mul vl]
-; CHECK-NEXT:    st1w { z1.s }, p0, [x8, #1, mul vl]
+; CHECK-NEXT:    addvl x9, x10, #4
+; CHECK-NEXT:    st1w { z3.s }, p0, [sp, #3, mul vl]
+; CHECK-NEXT:    sub x8, x9, x8
+; CHECK-NEXT:    st1w { z2.s }, p0, [sp, #2, mul vl]
+; CHECK-NEXT:    st1w { z1.s }, p0, [sp, #1, mul vl]
 ; CHECK-NEXT:    st1w { z0.s }, p0, [sp]
-; CHECK-NEXT:    st1w { z7.s }, p0, [x8, #7, mul vl]
-; CHECK-NEXT:    st1w { z4.s }, p0, [x8, #4, mul vl]
-; CHECK-NEXT:    st1w { z5.s }, p0, [x8, #5, mul vl]
-; CHECK-NEXT:    st1w { z6.s }, p0, [x8, #6, mul vl]
-; CHECK-NEXT:    ld1w { z0.s }, p0/z, [x9]
-; CHECK-NEXT:    ld1w { z1.s }, p0/z, [x9, #1, mul vl]
-; CHECK-NEXT:    ld1w { z2.s }, p0/z, [x9, #2, mul vl]
-; CHECK-NEXT:    ld1w { z3.s }, p0/z, [x9, #3, mul vl]
+; CHECK-NEXT:    st1w { z7.s }, p0, [sp, #7, mul vl]
+; CHECK-NEXT:    st1w { z4.s }, p0, [sp, #4, mul vl]
+; CHECK-NEXT:    st1w { z5.s }, p0, [sp, #5, mul vl]
+; CHECK-NEXT:    st1w { z6.s }, p0, [sp, #6, mul vl]
+; CHECK-NEXT:    ld1w { z0.s }, p0/z, [x8]
+; CHECK-NEXT:    ld1w { z1.s }, p0/z, [x8, #1, mul vl]
+; CHECK-NEXT:    ld1w { z2.s }, p0/z, [x8, #2, mul vl]
+; CHECK-NEXT:    ld1w { z3.s }, p0/z, [x8, #3, mul vl]
 ; CHECK-NEXT:    addvl sp, sp, #8
 ; CHECK-NEXT:    ldr x29, [sp], #16 // 8-byte Folded Reload
 ; CHECK-NEXT:    ret
   %res = call <vscale x 16 x float> @llvm.experimental.vector.splice.nxv16f32(<vscale x 16 x float> %a, <vscale x 16 x float> %b, i32 -17)
   ret <vscale x 16 x float> %res
 }
 
 declare <vscale x 2 x i1> @llvm.experimental.vector.splice.nxv2i1(<vscale x 2 x i1>, <vscale x 2 x i1>, i32)

llvm/test/CodeGen/AArch64/sve-calling-convention-mixed.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple aarch64-linux-gnu -mattr=+sve | FileCheck %s
 
 target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
 target triple = "aarch64-unknown-linux-gnu"
 
 ; Make sure callers set up the arguments correctly - tests AArch64ISelLowering::LowerCALL
 
 define float @foo1(double* %x0, double* %x1, double* %x2) nounwind {
 ; CHECK-LABEL: foo1:
 ; CHECK:       // %bb.0: // %entry
 ; CHECK-NEXT:    stp x29, x30, [sp, #-16]! // 16-byte Folded Spill
 ; CHECK-NEXT:    addvl sp, sp, #-4
 ; CHECK-NEXT:    ptrue p0.b
-; CHECK-NEXT:    mov x8, sp
+; CHECK-NEXT:    fmov s0, #1.00000000
 ; CHECK-NEXT:    ld4d { z1.d, z2.d, z3.d, z4.d }, p0/z, [x0]
 ; CHECK-NEXT:    ld4d { z16.d, z17.d, z18.d, z19.d }, p0/z, [x1]
 ; CHECK-NEXT:    ld1d { z5.d }, p0/z, [x2]
-; CHECK-NEXT:    fmov s0, #1.00000000
 ; CHECK-NEXT:    mov x0, sp
 ; CHECK-NEXT:    ptrue p0.d
 ; CHECK-NEXT:    st1d { z16.d }, p0, [sp]
-; CHECK-NEXT:    st1d { z17.d }, p0, [x8, #1, mul vl]
-; CHECK-NEXT:    st1d { z18.d }, p0, [x8, #2, mul vl]
-; CHECK-NEXT:    st1d { z19.d }, p0, [x8, #3, mul vl]
+; CHECK-NEXT:    st1d { z17.d }, p0, [sp, #1, mul vl]
+; CHECK-NEXT:    st1d { z18.d }, p0, [sp, #2, mul vl]
+; CHECK-NEXT:    st1d { z19.d }, p0, [sp, #3, mul vl]
 ; CHECK-NEXT:    bl callee1
 ; CHECK-NEXT:    addvl sp, sp, #4
 ; CHECK-NEXT:    ldp x29, x30, [sp], #16 // 16-byte Folded Reload
 ; CHECK-NEXT:    ret
 entry:
   %0 = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 31)
   %1 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
   %2 = call <vscale x 8 x double> @llvm.aarch64.sve.ld4.nxv8f64.nxv2i1(<vscale x 2 x i1> %1, double* %x0)
   %3 = call <vscale x 8 x double> @llvm.aarch64.sve.ld4.nxv8f64.nxv2i1(<vscale x 2 x i1> %1, double* %x1)
   %4 = call <vscale x 2 x double> @llvm.aarch64.sve.ld1.nxv2f64(<vscale x 2 x i1> %1, double* %x2)
   %call = call float @callee1(float 1.000000e+00, <vscale x 8 x double> %2, <vscale x 8 x double> %3, <vscale x 2 x double> %4)
   ret float %call
 }
 
 define float @foo2(double* %x0, double* %x1) nounwind {
 ; CHECK-LABEL: foo2:
 ; CHECK:       // %bb.0: // %entry
 ; CHECK-NEXT:    stp x29, x30, [sp, #-16]! // 16-byte Folded Spill
 ; CHECK-NEXT:    addvl sp, sp, #-4
 ; CHECK-NEXT:    sub sp, sp, #16
 ; CHECK-NEXT:    ptrue p0.b
-; CHECK-NEXT:    add x8, sp, #16
+; CHECK-NEXT:    add x9, sp, #16
 ; CHECK-NEXT:    ld4d { z1.d, z2.d, z3.d, z4.d }, p0/z, [x0]
 ; CHECK-NEXT:    ld4d { z16.d, z17.d, z18.d, z19.d }, p0/z, [x1]
+; CHECK-NEXT:    ptrue p0.d
+; CHECK-NEXT:    add x8, sp, #16
 ; CHECK-NEXT:    fmov s0, #1.00000000
 ; CHECK-NEXT:    mov w0, wzr
 ; CHECK-NEXT:    mov w1, #1
 ; CHECK-NEXT:    mov w2, #2
+; CHECK-NEXT:    st1d { z16.d }, p0, [x9]
+; CHECK-NEXT:    add x9, sp, #16
 ; CHECK-NEXT:    mov w3, #3
 ; CHECK-NEXT:    mov w4, #4
 ; CHECK-NEXT:    mov w5, #5
 ; CHECK-NEXT:    mov w6, #6
+; CHECK-NEXT:    st1d { z17.d }, p0, [x9, #1, mul vl]
+; CHECK-NEXT:    add x9, sp, #16
 ; CHECK-NEXT:    mov w7, #7
+; CHECK-NEXT:    st1d { z18.d }, p0, [x9, #2, mul vl]
 ; CHECK-NEXT:    add x9, sp, #16
-; CHECK-NEXT:    ptrue p0.d
-; CHECK-NEXT:    st1d { z16.d }, p0, [x9]
-; CHECK-NEXT:    st1d { z17.d }, p0, [x8, #1, mul vl]
-; CHECK-NEXT:    st1d { z18.d }, p0, [x8, #2, mul vl]
-; CHECK-NEXT:    st1d { z19.d }, p0, [x8, #3, mul vl]
+; CHECK-NEXT:    st1d { z19.d }, p0, [x9, #3, mul vl]
 ; CHECK-NEXT:    str x8, [sp]
 ; CHECK-NEXT:    bl callee2
 ; CHECK-NEXT:    addvl sp, sp, #4
 ; CHECK-NEXT:    add sp, sp, #16
 ; CHECK-NEXT:    ldp x29, x30, [sp], #16 // 16-byte Folded Reload
 ; CHECK-NEXT:    ret
 entry:
   %0 = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 31)
   %1 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
   %2 = call <vscale x 8 x double> @llvm.aarch64.sve.ld4.nxv8f64.nxv2i1(<vscale x 2 x i1> %1, double* %x0)
   %3 = call <vscale x 8 x double> @llvm.aarch64.sve.ld4.nxv8f64.nxv2i1(<vscale x 2 x i1> %1, double* %x1)
   %call = call float @callee2(i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, float 1.000000e+00, <vscale x 8 x double> %2, <vscale x 8 x double> %3)
   ret float %call
 }
 
 define float @foo3(double* %x0, double* %x1, double* %x2) nounwind {
 ; CHECK-LABEL: foo3:
 ; CHECK:       // %bb.0: // %entry
 ; CHECK-NEXT:    stp x29, x30, [sp, #-16]! // 16-byte Folded Spill
 ; CHECK-NEXT:    addvl sp, sp, #-3
 ; CHECK-NEXT:    ptrue p0.b
-; CHECK-NEXT:    mov x8, sp
+; CHECK-NEXT:    fmov s0, #1.00000000
 ; CHECK-NEXT:    ld4d { z2.d, z3.d, z4.d, z5.d }, p0/z, [x0]
 ; CHECK-NEXT:    ld3d { z16.d, z17.d, z18.d }, p0/z, [x1]
 ; CHECK-NEXT:    ld1d { z6.d }, p0/z, [x2]
-; CHECK-NEXT:    fmov s0, #1.00000000
 ; CHECK-NEXT:    fmov s1, #2.00000000
 ; CHECK-NEXT:    mov x0, sp
 ; CHECK-NEXT:    ptrue p0.d
 ; CHECK-NEXT:    st1d { z16.d }, p0, [sp]
-; CHECK-NEXT:    st1d { z17.d }, p0, [x8, #1, mul vl]
-; CHECK-NEXT:    st1d { z18.d }, p0, [x8, #2, mul vl]
+; CHECK-NEXT:    st1d { z17.d }, p0, [sp, #1, mul vl]
+; CHECK-NEXT:    st1d { z18.d }, p0, [sp, #2, mul vl]
 ; CHECK-NEXT:    bl callee3
 ; CHECK-NEXT:    addvl sp, sp, #3
 ; CHECK-NEXT:    ldp x29, x30, [sp], #16 // 16-byte Folded Reload
 ; CHECK-NEXT:    ret
 entry:
   %0 = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 31)
   %1 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %0)
   %2 = call <vscale x 8 x double> @llvm.aarch64.sve.ld4.nxv8f64.nxv2i1(<vscale x 2 x i1> %1, double* %x0)

llvm/test/CodeGen/AArch64/sve-fixed-length-fp-vselect.ll

 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    stp x29, x30, [sp, #-16]! // 16-byte Folded Spill
 ; CHECK-NEXT:    sub x9, sp, #48
 ; CHECK-NEXT:    mov x29, sp
 ; CHECK-NEXT:    and sp, x9, #0xffffffffffffffe0
 ; CHECK-NEXT:    .cfi_def_cfa w29, 16
 ; CHECK-NEXT:    .cfi_offset w30, -8
 ; CHECK-NEXT:    .cfi_offset w29, -16
-; CHECK-NEXT:    ldrh w9, [x2]
-; CHECK-NEXT:    mov x8, sp
+; CHECK-NEXT:    ldrh w8, [x2]
 ; CHECK-NEXT:    ptrue p0.h, vl16
 ; CHECK-NEXT:    ptrue p1.h
-; CHECK-NEXT:    sbfx w10, w9, #15, #1
-; CHECK-NEXT:    sbfx w11, w9, #14, #1
-; CHECK-NEXT:    sbfx w12, w9, #13, #1
-; CHECK-NEXT:    strh w10, [sp, #30]
-; CHECK-NEXT:    sbfx w10, w9, #12, #1
-; CHECK-NEXT:    strh w11, [sp, #28]
-; CHECK-NEXT:    sbfx w11, w9, #11, #1
-; CHECK-NEXT:    strh w12, [sp, #26]
-; CHECK-NEXT:    sbfx w12, w9, #10, #1
-; CHECK-NEXT:    strh w10, [sp, #24]
-; CHECK-NEXT:    sbfx w10, w9, #9, #1
-; CHECK-NEXT:    strh w11, [sp, #22]
-; CHECK-NEXT:    sbfx w11, w9, #8, #1
-; CHECK-NEXT:    strh w12, [sp, #20]
-; CHECK-NEXT:    sbfx w12, w9, #7, #1
-; CHECK-NEXT:    strh w10, [sp, #18]
-; CHECK-NEXT:    sbfx w10, w9, #6, #1
-; CHECK-NEXT:    strh w11, [sp, #16]
-; CHECK-NEXT:    sbfx w11, w9, #5, #1
-; CHECK-NEXT:    strh w12, [sp, #14]
-; CHECK-NEXT:    sbfx w12, w9, #4, #1
-; CHECK-NEXT:    strh w10, [sp, #12]
-; CHECK-NEXT:    sbfx w10, w9, #3, #1
-; CHECK-NEXT:    strh w11, [sp, #10]
-; CHECK-NEXT:    sbfx w11, w9, #2, #1
-; CHECK-NEXT:    strh w12, [sp, #8]
-; CHECK-NEXT:    sbfx w12, w9, #1, #1
-; CHECK-NEXT:    sbfx w9, w9, #0, #1
-; CHECK-NEXT:    strh w10, [sp, #6]
-; CHECK-NEXT:    strh w11, [sp, #4]
-; CHECK-NEXT:    strh w12, [sp, #2]
-; CHECK-NEXT:    strh w9, [sp]
-; CHECK-NEXT:    ld1h { z0.h }, p0/z, [x8]
+; CHECK-NEXT:    sbfx w9, w8, #15, #1
+; CHECK-NEXT:    sbfx w10, w8, #14, #1
+; CHECK-NEXT:    sbfx w11, w8, #13, #1
+; CHECK-NEXT:    strh w9, [sp, #30]
+; CHECK-NEXT:    sbfx w9, w8, #12, #1
+; CHECK-NEXT:    strh w10, [sp, #28]
+; CHECK-NEXT:    sbfx w10, w8, #11, #1
+; CHECK-NEXT:    strh w11, [sp, #26]
+; CHECK-NEXT:    sbfx w11, w8, #10, #1
+; CHECK-NEXT:    strh w9, [sp, #24]
+; CHECK-NEXT:    sbfx w9, w8, #9, #1
+; CHECK-NEXT:    strh w10, [sp, #22]
+; CHECK-NEXT:    sbfx w10, w8, #8, #1
+; CHECK-NEXT:    strh w11, [sp, #20]
+; CHECK-NEXT:    sbfx w11, w8, #7, #1
+; CHECK-NEXT:    strh w9, [sp, #18]
+; CHECK-NEXT:    sbfx w9, w8, #6, #1
+; CHECK-NEXT:    strh w10, [sp, #16]
+; CHECK-NEXT:    sbfx w10, w8, #5, #1
+; CHECK-NEXT:    strh w11, [sp, #14]
+; CHECK-NEXT:    sbfx w11, w8, #4, #1
+; CHECK-NEXT:    strh w9, [sp, #12]
+; CHECK-NEXT:    sbfx w9, w8, #3, #1
+; CHECK-NEXT:    strh w10, [sp, #10]
+; CHECK-NEXT:    sbfx w10, w8, #2, #1
+; CHECK-NEXT:    strh w11, [sp, #8]
+; CHECK-NEXT:    sbfx w11, w8, #1, #1
+; CHECK-NEXT:    sbfx w8, w8, #0, #1
+; CHECK-NEXT:    strh w9, [sp, #6]
+; CHECK-NEXT:    strh w10, [sp, #4]
+; CHECK-NEXT:    strh w11, [sp, #2]
+; CHECK-NEXT:    strh w8, [sp]
+; CHECK-NEXT:    ld1h { z0.h }, p0/z, [sp]
 ; CHECK-NEXT:    ld1h { z1.h }, p0/z, [x0]
 ; CHECK-NEXT:    ld1h { z2.h }, p0/z, [x1]
 ; CHECK-NEXT:    and z0.h, z0.h, #0x1
 ; CHECK-NEXT:    cmpne p1.h, p1/z, z0.h, #0
 ; CHECK-NEXT:    sel z0.h, p1, z1.h, z2.h
 ; CHECK-NEXT:    st1h { z0.h }, p0, [x0]
 ; CHECK-NEXT:    mov sp, x29
 ; CHECK-NEXT:    ldp x29, x30, [sp], #16 // 16-byte Folded Reload

 ; VBITS_GE_512:       // %bb.0:
 ; VBITS_GE_512-NEXT:    stp x29, x30, [sp, #-16]! // 16-byte Folded Spill
 ; VBITS_GE_512-NEXT:    sub x9, sp, #112
 ; VBITS_GE_512-NEXT:    mov x29, sp
 ; VBITS_GE_512-NEXT:    and sp, x9, #0xffffffffffffffc0
 ; VBITS_GE_512-NEXT:    .cfi_def_cfa w29, 16
 ; VBITS_GE_512-NEXT:    .cfi_offset w30, -8
 ; VBITS_GE_512-NEXT:    .cfi_offset w29, -16
-; VBITS_GE_512-NEXT:    ldr w9, [x2]
-; VBITS_GE_512-NEXT:    mov x8, sp
+; VBITS_GE_512-NEXT:    ldr w8, [x2]
 ; VBITS_GE_512-NEXT:    ptrue p0.h, vl32
 ; VBITS_GE_512-NEXT:    ptrue p1.h
-; VBITS_GE_512-NEXT:    asr w10, w9, #31
-; VBITS_GE_512-NEXT:    sbfx w11, w9, #30, #1
-; VBITS_GE_512-NEXT:    sbfx w12, w9, #29, #1
-; VBITS_GE_512-NEXT:    strh w10, [sp, #62]
-; VBITS_GE_512-NEXT:    sbfx w10, w9, #28, #1
-; VBITS_GE_512-NEXT:    strh w11, [sp, #60]
-; VBITS_GE_512-NEXT:    sbfx w11, w9, #27, #1
-; VBITS_GE_512-NEXT:    strh w12, [sp, #58]
-; VBITS_GE_512-NEXT:    sbfx w12, w9, #26, #1
-; VBITS_GE_512-NEXT:    strh w10, [sp, #56]
-; VBITS_GE_512-NEXT:    sbfx w10, w9, #25, #1
-; VBITS_GE_512-NEXT:    strh w11, [sp, #54]
-; VBITS_GE_512-NEXT:    sbfx w11, w9, #24, #1
-; VBITS_GE_512-NEXT:    strh w12, [sp, #52]
-; VBITS_GE_512-NEXT:    sbfx w12, w9, #23, #1
-; VBITS_GE_512-NEXT:    strh w10, [sp, #50]
-; VBITS_GE_512-NEXT:    sbfx w10, w9, #22, #1
-; VBITS_GE_512-NEXT:    strh w11, [sp, #48]
-; VBITS_GE_512-NEXT:    sbfx w11, w9, #21, #1
-; VBITS_GE_512-NEXT:    strh w12, [sp, #46]
-; VBITS_GE_512-NEXT:    sbfx w12, w9, #20, #1
-; VBITS_GE_512-NEXT:    strh w10, [sp, #44]
-; VBITS_GE_512-NEXT:    sbfx w10, w9, #19, #1
-; VBITS_GE_512-NEXT:    strh w11, [sp, #42]
-; VBITS_GE_512-NEXT:    sbfx w11, w9, #18, #1
-; VBITS_GE_512-NEXT:    strh w12, [sp, #40]
-; VBITS_GE_512-NEXT:    sbfx w12, w9, #17, #1
-; VBITS_GE_512-NEXT:    strh w10, [sp, #38]
-; VBITS_GE_512-NEXT:    sbfx w10, w9, #16, #1
-; VBITS_GE_512-NEXT:    strh w11, [sp, #36]
-; VBITS_GE_512-NEXT:    sbfx w11, w9, #15, #1
-; VBITS_GE_512-NEXT:    strh w12, [sp, #34]
-; VBITS_GE_512-NEXT:    sbfx w12, w9, #14, #1
-; VBITS_GE_512-NEXT:    strh w10, [sp, #32]
-; VBITS_GE_512-NEXT:    sbfx w10, w9, #13, #1
-; VBITS_GE_512-NEXT:    strh w11, [sp, #30]
-; VBITS_GE_512-NEXT:    sbfx w11, w9, #12, #1
-; VBITS_GE_512-NEXT:    strh w12, [sp, #28]
-; VBITS_GE_512-NEXT:    sbfx w12, w9, #11, #1
-; VBITS_GE_512-NEXT:    strh w10, [sp, #26]
-; VBITS_GE_512-NEXT:    sbfx w10, w9, #10, #1
-; VBITS_GE_512-NEXT:    strh w11, [sp, #24]
-; VBITS_GE_512-NEXT:    sbfx w11, w9, #9, #1
-; VBITS_GE_512-NEXT:    strh w12, [sp, #22]
-; VBITS_GE_512-NEXT:    sbfx w12, w9, #8, #1
-; VBITS_GE_512-NEXT:    strh w10, [sp, #20]
-; VBITS_GE_512-NEXT:    sbfx w10, w9, #7, #1
-; VBITS_GE_512-NEXT:    strh w11, [sp, #18]
-; VBITS_GE_512-NEXT:    sbfx w11, w9, #6, #1
-; VBITS_GE_512-NEXT:    strh w12, [sp, #16]
-; VBITS_GE_512-NEXT:    sbfx w12, w9, #5, #1
-; VBITS_GE_512-NEXT:    strh w10, [sp, #14]
-; VBITS_GE_512-NEXT:    sbfx w10, w9, #4, #1
-; VBITS_GE_512-NEXT:    strh w11, [sp, #12]
-; VBITS_GE_512-NEXT:    sbfx w11, w9, #3, #1
-; VBITS_GE_512-NEXT:    strh w12, [sp, #10]
-; VBITS_GE_512-NEXT:    sbfx w12, w9, #2, #1
-; VBITS_GE_512-NEXT:    strh w10, [sp, #8]
-; VBITS_GE_512-NEXT:    sbfx w10, w9, #1, #1
-; VBITS_GE_512-NEXT:    sbfx w9, w9, #0, #1
-; VBITS_GE_512-NEXT:    strh w11, [sp, #6]
-; VBITS_GE_512-NEXT:    strh w12, [sp, #4]
-; VBITS_GE_512-NEXT:    strh w10, [sp, #2]
-; VBITS_GE_512-NEXT:    strh w9, [sp]
-; VBITS_GE_512-NEXT:    ld1h { z0.h }, p0/z, [x8]
+; VBITS_GE_512-NEXT:    asr w9, w8, #31
+; VBITS_GE_512-NEXT:    sbfx w10, w8, #30, #1
+; VBITS_GE_512-NEXT:    sbfx w11, w8, #29, #1
+; VBITS_GE_512-NEXT:    strh w9, [sp, #62]
+; VBITS_GE_512-NEXT:    sbfx w9, w8, #28, #1
+; VBITS_GE_512-NEXT:    strh w10, [sp, #60]
+; VBITS_GE_512-NEXT:    sbfx w10, w8, #27, #1
+; VBITS_GE_512-NEXT:    strh w11, [sp, #58]
+; VBITS_GE_512-NEXT:    sbfx w11, w8, #26, #1
+; VBITS_GE_512-NEXT:    strh w9, [sp, #56]
+; VBITS_GE_512-NEXT:    sbfx w9, w8, #25, #1
+; VBITS_GE_512-NEXT:    strh w10, [sp, #54]
+; VBITS_GE_512-NEXT:    sbfx w10, w8, #24, #1
+; VBITS_GE_512-NEXT:    strh w11, [sp, #52]
+; VBITS_GE_512-NEXT:    sbfx w11, w8, #23, #1
+; VBITS_GE_512-NEXT:    strh w9, [sp, #50]
+; VBITS_GE_512-NEXT:    sbfx w9, w8, #22, #1
+; VBITS_GE_512-NEXT:    strh w10, [sp, #48]
+; VBITS_GE_512-NEXT:    sbfx w10, w8, #21, #1
+; VBITS_GE_512-NEXT:    strh w11, [sp, #46]
+; VBITS_GE_512-NEXT:    sbfx w11, w8, #20, #1
+; VBITS_GE_512-NEXT:    strh w9, [sp, #44]
+; VBITS_GE_512-NEXT:    sbfx w9, w8, #19, #1
+; VBITS_GE_512-NEXT:    strh w10, [sp, #42]
+; VBITS_GE_512-NEXT:    sbfx w10, w8, #18, #1
+; VBITS_GE_512-NEXT:    strh w11, [sp, #40]
+; VBITS_GE_512-NEXT:    sbfx w11, w8, #17, #1
+; VBITS_GE_512-NEXT:    strh w9, [sp, #38]
+; VBITS_GE_512-NEXT:    sbfx w9, w8, #16, #1
+; VBITS_GE_512-NEXT:    strh w10, [sp, #36]
+; VBITS_GE_512-NEXT:    sbfx w10, w8, #15, #1
+; VBITS_GE_512-NEXT:    strh w11, [sp, #34]
+; VBITS_GE_512-NEXT:    sbfx w11, w8, #14, #1
+; VBITS_GE_512-NEXT:    strh w9, [sp, #32]
+; VBITS_GE_512-NEXT:    sbfx w9, w8, #13, #1
+; VBITS_GE_512-NEXT:    strh w10, [sp, #30]
+; VBITS_GE_512-NEXT:    sbfx w10, w8, #12, #1
+; VBITS_GE_512-NEXT:    strh w11, [sp, #28]
+; VBITS_GE_512-NEXT:    sbfx w11, w8, #11, #1
+; VBITS_GE_512-NEXT:    strh w9, [sp, #26]
+; VBITS_GE_512-NEXT:    sbfx w9, w8, #10, #1
+; VBITS_GE_512-NEXT:    strh w10, [sp, #24]
+; VBITS_GE_512-NEXT:    sbfx w10, w8, #9, #1
+; VBITS_GE_512-NEXT:    strh w11, [sp, #22]
+; VBITS_GE_512-NEXT:    sbfx w11, w8, #8, #1
+; VBITS_GE_512-NEXT:    strh w9, [sp, #20]
+; VBITS_GE_512-NEXT:    sbfx w9, w8, #7, #1
+; VBITS_GE_512-NEXT:    strh w10, [sp, #18]
+; VBITS_GE_512-NEXT:    sbfx w10, w8, #6, #1
+; VBITS_GE_512-NEXT:    strh w11, [sp, #16]
+; VBITS_GE_512-NEXT:    sbfx w11, w8, #5, #1
+; VBITS_GE_512-NEXT:    strh w9, [sp, #14]
+; VBITS_GE_512-NEXT:    sbfx w9, w8, #4, #1
+; VBITS_GE_512-NEXT:    strh w10, [sp, #12]
+; VBITS_GE_512-NEXT:    sbfx w10, w8, #3, #1
+; VBITS_GE_512-NEXT:    strh w11, [sp, #10]
+; VBITS_GE_512-NEXT:    sbfx w11, w8, #2, #1
+; VBITS_GE_512-NEXT:    strh w9, [sp, #8]
+; VBITS_GE_512-NEXT:    sbfx w9, w8, #1, #1
+; VBITS_GE_512-NEXT:    sbfx w8, w8, #0, #1
+; VBITS_GE_512-NEXT:    strh w10, [sp, #6]
+; VBITS_GE_512-NEXT:    strh w11, [sp, #4]
+; VBITS_GE_512-NEXT:    strh w9, [sp, #2]
+; VBITS_GE_512-NEXT:    strh w8, [sp]
+; VBITS_GE_512-NEXT:    ld1h { z0.h }, p0/z, [sp]
 ; VBITS_GE_512-NEXT:    ld1h { z1.h }, p0/z, [x0]
 ; VBITS_GE_512-NEXT:    ld1h { z2.h }, p0/z, [x1]
 ; VBITS_GE_512-NEXT:    and z0.h, z0.h, #0x1
 ; VBITS_GE_512-NEXT:    cmpne p1.h, p1/z, z0.h, #0
 ; VBITS_GE_512-NEXT:    sel z0.h, p1, z1.h, z2.h
 ; VBITS_GE_512-NEXT:    st1h { z0.h }, p0, [x0]
 ; VBITS_GE_512-NEXT:    mov sp, x29
 ; VBITS_GE_512-NEXT:    ldp x29, x30, [sp], #16 // 16-byte Folded Reload

 ; VBITS_GE_1024:       // %bb.0:
 ; VBITS_GE_1024-NEXT:    stp x29, x30, [sp, #-16]! // 16-byte Folded Spill
 ; VBITS_GE_1024-NEXT:    sub x9, sp, #240
 ; VBITS_GE_1024-NEXT:    mov x29, sp
 ; VBITS_GE_1024-NEXT:    and sp, x9, #0xffffffffffffff80
 ; VBITS_GE_1024-NEXT:    .cfi_def_cfa w29, 16
 ; VBITS_GE_1024-NEXT:    .cfi_offset w30, -8
 ; VBITS_GE_1024-NEXT:    .cfi_offset w29, -16
-; VBITS_GE_1024-NEXT:    ldr x9, [x2]
-; VBITS_GE_1024-NEXT:    mov x8, sp
+; VBITS_GE_1024-NEXT:    ldr x8, [x2]
 ; VBITS_GE_1024-NEXT:    ptrue p0.h, vl64
 ; VBITS_GE_1024-NEXT:    ptrue p1.h
-; VBITS_GE_1024-NEXT:    asr x10, x9, #63
-; VBITS_GE_1024-NEXT:    sbfx x11, x9, #62, #1
-; VBITS_GE_1024-NEXT:    sbfx x12, x9, #61, #1
-; VBITS_GE_1024-NEXT:    strh w10, [sp, #126]
-; VBITS_GE_1024-NEXT:    sbfx x10, x9, #60, #1
-; VBITS_GE_1024-NEXT:    strh w11, [sp, #124]
-; VBITS_GE_1024-NEXT:    sbfx x11, x9, #59, #1
-; VBITS_GE_1024-NEXT:    strh w12, [sp, #122]
-; VBITS_GE_1024-NEXT:    sbfx x12, x9, #58, #1
-; VBITS_GE_1024-NEXT:    strh w10, [sp, #120]
-; VBITS_GE_1024-NEXT:    sbfx x10, x9, #57, #1
-; VBITS_GE_1024-NEXT:    strh w11, [sp, #118]
-; VBITS_GE_1024-NEXT:    sbfx x11, x9, #56, #1
-; VBITS_GE_1024-NEXT:    strh w12, [sp, #116]
-; VBITS_GE_1024-NEXT:    sbfx x12, x9, #55, #1
-; VBITS_GE_1024-NEXT:    strh w10, [sp, #114]
-; VBITS_GE_1024-NEXT:    sbfx x10, x9, #54, #1
-; VBITS_GE_1024-NEXT:    strh w11, [sp, #112]
-; VBITS_GE_1024-NEXT:    sbfx x11, x9, #53, #1
-; VBITS_GE_1024-NEXT:    strh w12, [sp, #110]
-; VBITS_GE_1024-NEXT:    sbfx x12, x9, #52, #1
-; VBITS_GE_1024-NEXT:    strh w10, [sp, #108]
-; VBITS_GE_1024-NEXT:    sbfx x10, x9, #51, #1
-; VBITS_GE_1024-NEXT:    strh w11, [sp, #106]
-; VBITS_GE_1024-NEXT:    sbfx x11, x9, #50, #1
-; VBITS_GE_1024-NEXT:    strh w12, [sp, #104]
-; VBITS_GE_1024-NEXT:    sbfx x12, x9, #49, #1
-; VBITS_GE_1024-NEXT:    strh w10, [sp, #102]
-; VBITS_GE_1024-NEXT:    sbfx x10, x9, #48, #1
-; VBITS_GE_1024-NEXT:    strh w11, [sp, #100]
-; VBITS_GE_1024-NEXT:    sbfx x11, x9, #47, #1
-; VBITS_GE_1024-NEXT:    strh w12, [sp, #98]
-; VBITS_GE_1024-NEXT:    sbfx x12, x9, #46, #1
-; VBITS_GE_1024-NEXT:    strh w10, [sp, #96]
-; VBITS_GE_1024-NEXT:    sbfx x10, x9, #45, #1
-; VBITS_GE_1024-NEXT:    strh w11, [sp, #94]
-; VBITS_GE_1024-NEXT:    sbfx x11, x9, #44, #1
-; VBITS_GE_1024-NEXT:    strh w12, [sp, #92]
-; VBITS_GE_1024-NEXT:    sbfx x12, x9, #43, #1
-; VBITS_GE_1024-NEXT:    strh w10, [sp, #90]
-; VBITS_GE_1024-NEXT:    sbfx x10, x9, #42, #1
-; VBITS_GE_1024-NEXT:    strh w11, [sp, #88]
-; VBITS_GE_1024-NEXT:    sbfx x11, x9, #41, #1
-; VBITS_GE_1024-NEXT:    strh w12, [sp, #86]
-; VBITS_GE_1024-NEXT:    sbfx x12, x9, #40, #1
-; VBITS_GE_1024-NEXT:    strh w10, [sp, #84]
-; VBITS_GE_1024-NEXT:    sbfx x10, x9, #39, #1
-; VBITS_GE_1024-NEXT:    strh w11, [sp, #82]
-; VBITS_GE_1024-NEXT:    sbfx x11, x9, #38, #1
-; VBITS_GE_1024-NEXT:    strh w12, [sp, #80]
-; VBITS_GE_1024-NEXT:    sbfx x12, x9, #37, #1
-; VBITS_GE_1024-NEXT:    strh w10, [sp, #78]
-; VBITS_GE_1024-NEXT:    sbfx x10, x9, #36, #1
-; VBITS_GE_1024-NEXT:    strh w11, [sp, #76]
-; VBITS_GE_1024-NEXT:    sbfx x11, x9, #35, #1
-; VBITS_GE_1024-NEXT:    strh w12, [sp, #74]
-; VBITS_GE_1024-NEXT:    sbfx x12, x9, #34, #1
-; VBITS_GE_1024-NEXT:    strh w10, [sp, #72]
-; VBITS_GE_1024-NEXT:    sbfx x10, x9, #33, #1
-; VBITS_GE_1024-NEXT:    strh w11, [sp, #70]
-; VBITS_GE_1024-NEXT:    sbfx x11, x9, #32, #1
-; VBITS_GE_1024-NEXT:    strh w12, [sp, #68]
-; VBITS_GE_1024-NEXT:    asr w12, w9, #31
-; VBITS_GE_1024-NEXT:    strh w10, [sp, #66]
-; VBITS_GE_1024-NEXT:    sbfx w10, w9, #30, #1
-; VBITS_GE_1024-NEXT:    strh w11, [sp, #64]
-; VBITS_GE_1024-NEXT:    sbfx w11, w9, #29, #1
-; VBITS_GE_1024-NEXT:    strh w12, [sp, #62]
-; VBITS_GE_1024-NEXT:    sbfx w12, w9, #28, #1
-; VBITS_GE_1024-NEXT:    strh w10, [sp, #60]
-; VBITS_GE_1024-NEXT:    sbfx w10, w9, #27, #1
-; VBITS_GE_1024-NEXT:    strh w11, [sp, #58]
-; VBITS_GE_1024-NEXT:    sbfx w11, w9, #26, #1
-; VBITS_GE_1024-NEXT:    strh w12, [sp, #56]
-; VBITS_GE_1024-NEXT:    sbfx w12, w9, #25, #1
-; VBITS_GE_1024-NEXT:    strh w10, [sp, #54]
-; VBITS_GE_1024-NEXT:    sbfx w10, w9, #24, #1
-; VBITS_GE_1024-NEXT:    strh w11, [sp, #52]
-; VBITS_GE_1024-NEXT:    sbfx w11, w9, #23, #1
-; VBITS_GE_1024-NEXT:    strh w12, [sp, #50]
-; VBITS_GE_1024-NEXT:    sbfx w12, w9, #22, #1
-; VBITS_GE_1024-NEXT:    strh w10, [sp, #48]
-; VBITS_GE_1024-NEXT:    sbfx w10, w9, #21, #1
-; VBITS_GE_1024-NEXT:    strh w11, [sp, #46]
-; VBITS_GE_1024-NEXT:    sbfx w11, w9, #20, #1
-; VBITS_GE_1024-NEXT:    strh w12, [sp, #44]
-; VBITS_GE_1024-NEXT:    sbfx w12, w9, #19, #1
-; VBITS_GE_1024-NEXT:    strh w10, [sp, #42]
-; VBITS_GE_1024-NEXT:    sbfx w10, w9, #18, #1
-; VBITS_GE_1024-NEXT:    strh w11, [sp, #40]
-; VBITS_GE_1024-NEXT:    sbfx w11, w9, #17, #1
-; VBITS_GE_1024-NEXT:    strh w12, [sp, #38]
-; VBITS_GE_1024-NEXT:    sbfx w12, w9, #16, #1
-; VBITS_GE_1024-NEXT:    strh w10, [sp, #36]
-; VBITS_GE_1024-NEXT:    sbfx w10, w9, #15, #1
-; VBITS_GE_1024-NEXT:    strh w11, [sp, #34]
-; VBITS_GE_1024-NEXT:    sbfx w11, w9, #14, #1
-; VBITS_GE_1024-NEXT:    strh w12, [sp, #32]
-; VBITS_GE_1024-NEXT:    sbfx w12, w9, #13, #1
-; VBITS_GE_1024-NEXT:    strh w10, [sp, #30]
-; VBITS_GE_1024-NEXT:    sbfx w10, w9, #12, #1
-; VBITS_GE_1024-NEXT:    strh w11, [sp, #28]
-; VBITS_GE_1024-NEXT:    sbfx w11, w9, #11, #1
-; VBITS_GE_1024-NEXT:    strh w12, [sp, #26]
-; VBITS_GE_1024-NEXT:    sbfx w12, w9, #10, #1
-; VBITS_GE_1024-NEXT:    strh w10, [sp, #24]
-; VBITS_GE_1024-NEXT:    sbfx w10, w9, #9, #1
-; VBITS_GE_1024-NEXT:    strh w11, [sp, #22]
-; VBITS_GE_1024-NEXT:    sbfx w11, w9, #8, #1
-; VBITS_GE_1024-NEXT:    strh w12, [sp, #20]
-; VBITS_GE_1024-NEXT:    sbfx w12, w9, #7, #1
-; VBITS_GE_1024-NEXT:    strh w10, [sp, #18]
-; VBITS_GE_1024-NEXT:    sbfx w10, w9, #6, #1
-; VBITS_GE_1024-NEXT:    strh w11, [sp, #16]
-; VBITS_GE_1024-NEXT:    sbfx w11, w9, #5, #1
-; VBITS_GE_1024-NEXT:    strh w12, [sp, #14]
-; VBITS_GE_1024-NEXT:    sbfx w12, w9, #4, #1
-; VBITS_GE_1024-NEXT:    strh w10, [sp, #12]
-; VBITS_GE_1024-NEXT:    sbfx w10, w9, #3, #1
-; VBITS_GE_1024-NEXT:    strh w11, [sp, #10]
-; VBITS_GE_1024-NEXT:    sbfx w11, w9, #2, #1
-; VBITS_GE_1024-NEXT:    strh w12, [sp, #8]
-; VBITS_GE_1024-NEXT:    sbfx w12, w9, #1, #1
-; VBITS_GE_1024-NEXT:    sbfx w9, w9, #0, #1
-; VBITS_GE_1024-NEXT:    strh w10, [sp, #6]
-; VBITS_GE_1024-NEXT:    strh w11, [sp, #4]
-; VBITS_GE_1024-NEXT:    strh w12, [sp, #2]
-; VBITS_GE_1024-NEXT:    strh w9, [sp]
-; VBITS_GE_1024-NEXT:    ld1h { z0.h }, p0/z, [x8]
+; VBITS_GE_1024-NEXT:    asr x9, x8, #63
+; VBITS_GE_1024-NEXT:    sbfx x10, x8, #62, #1
+; VBITS_GE_1024-NEXT:    sbfx x11, x8, #61, #1
+; VBITS_GE_1024-NEXT:    strh w9, [sp, #126]
+; VBITS_GE_1024-NEXT:    sbfx x9, x8, #60, #1
+; VBITS_GE_1024-NEXT:    strh w10, [sp, #124]
+; VBITS_GE_1024-NEXT:    sbfx x10, x8, #59, #1
+; VBITS_GE_1024-NEXT:    strh w11, [sp, #122]
+; VBITS_GE_1024-NEXT:    sbfx x11, x8, #58, #1
+; VBITS_GE_1024-NEXT:    strh w9, [sp, #120]
+; VBITS_GE_1024-NEXT:    sbfx x9, x8, #57, #1
+; VBITS_GE_1024-NEXT:    strh w10, [sp, #118]
+; VBITS_GE_1024-NEXT:    sbfx x10, x8, #56, #1
+; VBITS_GE_1024-NEXT:    strh w11, [sp, #116]
+; VBITS_GE_1024-NEXT:    sbfx x11, x8, #55, #1
+; VBITS_GE_1024-NEXT:    strh w9, [sp, #114]
+; VBITS_GE_1024-NEXT:    sbfx x9, x8, #54, #1
+; VBITS_GE_1024-NEXT:    strh w10, [sp, #112]
+; VBITS_GE_1024-NEXT:    sbfx x10, x8, #53, #1
+; VBITS_GE_1024-NEXT:    strh w11, [sp, #110]
+; VBITS_GE_1024-NEXT:    sbfx x11, x8, #52, #1
+; VBITS_GE_1024-NEXT:    strh w9, [sp, #108]
+; VBITS_GE_1024-NEXT:    sbfx x9, x8, #51, #1
+; VBITS_GE_1024-NEXT:    strh w10, [sp, #106]
+; VBITS_GE_1024-NEXT:    sbfx x10, x8, #50, #1
+; VBITS_GE_1024-NEXT:    strh w11, [sp, #104]
+; VBITS_GE_1024-NEXT:    sbfx x11, x8, #49, #1
+; VBITS_GE_1024-NEXT:    strh w9, [sp, #102]
+; VBITS_GE_1024-NEXT:    sbfx x9, x8, #48, #1
+; VBITS_GE_1024-NEXT:    strh w10, [sp, #100]
+; VBITS_GE_1024-NEXT:    sbfx x10, x8, #47, #1
+; VBITS_GE_1024-NEXT:    strh w11, [sp, #98]
+; VBITS_GE_1024-NEXT:    sbfx x11, x8, #46, #1
+; VBITS_GE_1024-NEXT:    strh w9, [sp, #96]
+; VBITS_GE_1024-NEXT:    sbfx x9, x8, #45, #1
+; VBITS_GE_1024-NEXT:    strh w10, [sp, #94]
+; VBITS_GE_1024-NEXT:    sbfx x10, x8, #44, #1
+; VBITS_GE_1024-NEXT:    strh w11, [sp, #92]
+; VBITS_GE_1024-NEXT:    sbfx x11, x8, #43, #1
+; VBITS_GE_1024-NEXT:    strh w9, [sp, #90]
+; VBITS_GE_1024-NEXT:    sbfx x9, x8, #42, #1
+; VBITS_GE_1024-NEXT:    strh w10, [sp, #88]
+; VBITS_GE_1024-NEXT:    sbfx x10, x8, #41, #1
+; VBITS_GE_1024-NEXT:    strh w11, [sp, #86]
+; VBITS_GE_1024-NEXT:    sbfx x11, x8, #40, #1
+; VBITS_GE_1024-NEXT:    strh w9, [sp, #84]
+; VBITS_GE_1024-NEXT:    sbfx x9, x8, #39, #1
+; VBITS_GE_1024-NEXT:    strh w10, [sp, #82]
+; VBITS_GE_1024-NEXT:    sbfx x10, x8, #38, #1
+; VBITS_GE_1024-NEXT:    strh w11, [sp, #80]
+; VBITS_GE_1024-NEXT:    sbfx x11, x8, #37, #1
+; VBITS_GE_1024-NEXT:    strh w9, [sp, #78]
+; VBITS_GE_1024-NEXT:    sbfx x9, x8, #36, #1
+; VBITS_GE_1024-NEXT:    strh w10, [sp, #76]
+; VBITS_GE_1024-NEXT:    sbfx x10, x8, #35, #1
+; VBITS_GE_1024-NEXT:    strh w11, [sp, #74]
+; VBITS_GE_1024-NEXT:    sbfx x11, x8, #34, #1
+; VBITS_GE_1024-NEXT:    strh w9, [sp, #72]
+; VBITS_GE_1024-NEXT:    sbfx x9, x8, #33, #1
+; VBITS_GE_1024-NEXT:    strh w10, [sp, #70]
+; VBITS_GE_1024-NEXT:    sbfx x10, x8, #32, #1
+; VBITS_GE_1024-NEXT:    strh w11, [sp, #68]
+; VBITS_GE_1024-NEXT:    asr w11, w8, #31
+; VBITS_GE_1024-NEXT:    strh w9, [sp, #66]
+; VBITS_GE_1024-NEXT:    sbfx w9, w8, #30, #1
+; VBITS_GE_1024-NEXT:    strh w10, [sp, #64]
+; VBITS_GE_1024-NEXT:    sbfx w10, w8, #29, #1
+; VBITS_GE_1024-NEXT:    strh w11, [sp, #62]
+; VBITS_GE_1024-NEXT:    sbfx w11, w8, #28, #1
+; VBITS_GE_1024-NEXT:    strh w9, [sp, #60]
+; VBITS_GE_1024-NEXT:    sbfx w9, w8, #27, #1
+; VBITS_GE_1024-NEXT:    strh w10, [sp, #58]
+; VBITS_GE_1024-NEXT:    sbfx w10, w8, #26, #1
+; VBITS_GE_1024-NEXT:    strh w11, [sp, #56]
+; VBITS_GE_1024-NEXT:    sbfx w11, w8, #25, #1
+; VBITS_GE_1024-NEXT:    strh w9, [sp, #54]
+; VBITS_GE_1024-NEXT:    sbfx w9, w8, #24, #1
+; VBITS_GE_1024-NEXT:    strh w10, [sp, #52]
+; VBITS_GE_1024-NEXT:    sbfx w10, w8, #23, #1
+; VBITS_GE_1024-NEXT:    strh w11, [sp, #50]
+; VBITS_GE_1024-NEXT:    sbfx w11, w8, #22, #1
+; VBITS_GE_1024-NEXT:    strh w9, [sp, #48]
+; VBITS_GE_1024-NEXT:    sbfx w9, w8, #21, #1
+; VBITS_GE_1024-NEXT:    strh w10, [sp, #46]
+; VBITS_GE_1024-NEXT:    sbfx w10, w8, #20, #1
+; VBITS_GE_1024-NEXT:    strh w11, [sp, #44]
+; VBITS_GE_1024-NEXT:    sbfx w11, w8, #19, #1
+; VBITS_GE_1024-NEXT:    strh w9, [sp, #42]
+; VBITS_GE_1024-NEXT:    sbfx w9, w8, #18, #1
+; VBITS_GE_1024-NEXT:    strh w10, [sp, #40]
+; VBITS_GE_1024-NEXT:    sbfx w10, w8, #17, #1
+; VBITS_GE_1024-NEXT:    strh w11, [sp, #38]
+; VBITS_GE_1024-NEXT:    sbfx w11, w8, #16, #1
+; VBITS_GE_1024-NEXT:    strh w9, [sp, #36]
+; VBITS_GE_1024-NEXT:    sbfx w9, w8, #15, #1
+; VBITS_GE_1024-NEXT:    strh w10, [sp, #34]
+; VBITS_GE_1024-NEXT:    sbfx w10, w8, #14, #1
+; VBITS_GE_1024-NEXT:    strh w11, [sp, #32]
+; VBITS_GE_1024-NEXT:    sbfx w11, w8, #13, #1
+; VBITS_GE_1024-NEXT:    strh w9, [sp, #30]
+; VBITS_GE_1024-NEXT:    sbfx w9, w8, #12, #1
+; VBITS_GE_1024-NEXT:    strh w10, [sp, #28]
+; VBITS_GE_1024-NEXT:    sbfx w10, w8, #11, #1
+; VBITS_GE_1024-NEXT:    strh w11, [sp, #26]
+; VBITS_GE_1024-NEXT:    sbfx w11, w8, #10, #1
+; VBITS_GE_1024-NEXT:    strh w9, [sp, #24]
+; VBITS_GE_1024-NEXT:    sbfx w9, w8, #9, #1
+; VBITS_GE_1024-NEXT:    strh w10, [sp, #22]
+; VBITS_GE_1024-NEXT:    sbfx w10, w8, #8, #1
+; VBITS_GE_1024-NEXT:    strh w11, [sp, #20]
+; VBITS_GE_1024-NEXT:    sbfx w11, w8, #7, #1
+; VBITS_GE_1024-NEXT:    strh w9, [sp, #18]
+; VBITS_GE_1024-NEXT:    sbfx w9, w8, #6, #1
+; VBITS_GE_1024-NEXT:    strh w10, [sp, #16]
+; VBITS_GE_1024-NEXT:    sbfx w10, w8, #5, #1
+; VBITS_GE_1024-NEXT:    strh w11, [sp, #14]
+; VBITS_GE_1024-NEXT:    sbfx w11, w8, #4, #1
+; VBITS_GE_1024-NEXT:    strh w9, [sp, #12]
+; VBITS_GE_1024-NEXT:    sbfx w9, w8, #3, #1
+; VBITS_GE_1024-NEXT:    strh w10, [sp, #10]
+; VBITS_GE_1024-NEXT:    sbfx w10, w8, #2, #1
+; VBITS_GE_1024-NEXT:    strh w11, [sp, #8]
+; VBITS_GE_1024-NEXT:    sbfx w11, w8, #1, #1
+; VBITS_GE_1024-NEXT:    sbfx w8, w8, #0, #1
+; VBITS_GE_1024-NEXT:    strh w9, [sp, #6]
+; VBITS_GE_1024-NEXT:    strh w10, [sp, #4]
+; VBITS_GE_1024-NEXT:    strh w11, [sp, #2]
+; VBITS_GE_1024-NEXT:    strh w8, [sp]
+; VBITS_GE_1024-NEXT:    ld1h { z0.h }, p0/z, [sp]
 ; VBITS_GE_1024-NEXT:    ld1h { z1.h }, p0/z, [x0]
 ; VBITS_GE_1024-NEXT:    ld1h { z2.h }, p0/z, [x1]
 ; VBITS_GE_1024-NEXT:    and z0.h, z0.h, #0x1
 ; VBITS_GE_1024-NEXT:    cmpne p1.h, p1/z, z0.h, #0
 ; VBITS_GE_1024-NEXT:    sel z0.h, p1, z1.h, z2.h
 ; VBITS_GE_1024-NEXT:    st1h { z0.h }, p0, [x0]
 ; VBITS_GE_1024-NEXT:    mov sp, x29
 ; VBITS_GE_1024-NEXT:    ldp x29, x30, [sp], #16 // 16-byte Folded Reload

 ; VBITS_GE_2048:       // %bb.0:
 ; VBITS_GE_2048-NEXT:    stp x29, x30, [sp, #-16]! // 16-byte Folded Spill
 ; VBITS_GE_2048-NEXT:    sub x9, sp, #496
 ; VBITS_GE_2048-NEXT:    mov x29, sp
 ; VBITS_GE_2048-NEXT:    and sp, x9, #0xffffffffffffff00
 ; VBITS_GE_2048-NEXT:    .cfi_def_cfa w29, 16
 ; VBITS_GE_2048-NEXT:    .cfi_offset w30, -8
 ; VBITS_GE_2048-NEXT:    .cfi_offset w29, -16
-; VBITS_GE_2048-NEXT:    ldr x9, [x2, #8]
-; VBITS_GE_2048-NEXT:    mov x8, sp
+; VBITS_GE_2048-NEXT:    ldr x8, [x2, #8]
 ; VBITS_GE_2048-NEXT:    ptrue p0.h, vl128
 ; VBITS_GE_2048-NEXT:    ptrue p1.h
-; VBITS_GE_2048-NEXT:    asr x10, x9, #63
-; VBITS_GE_2048-NEXT:    sbfx x11, x9, #62, #1
-; VBITS_GE_2048-NEXT:    sbfx x12, x9, #61, #1
-; VBITS_GE_2048-NEXT:    strh w10, [sp, #254]
-; VBITS_GE_2048-NEXT:    sbfx x10, x9, #60, #1
-; VBITS_GE_2048-NEXT:    strh w11, [sp, #252]
-; VBITS_GE_2048-NEXT:    sbfx x11, x9, #59, #1
-; VBITS_GE_2048-NEXT:    strh w12, [sp, #250]
-; VBITS_GE_2048-NEXT:    sbfx x12, x9, #58, #1
-; VBITS_GE_2048-NEXT:    strh w10, [sp, #248]
-; VBITS_GE_2048-NEXT:    sbfx x10, x9, #57, #1
-; VBITS_GE_2048-NEXT:    strh w11, [sp, #246]
-; VBITS_GE_2048-NEXT:    sbfx x11, x9, #56, #1
-; VBITS_GE_2048-NEXT:    strh w12, [sp, #244]
-; VBITS_GE_2048-NEXT:    sbfx x12, x9, #55, #1
-; VBITS_GE_2048-NEXT:    strh w10, [sp, #242]
-; VBITS_GE_2048-NEXT:    sbfx x10, x9, #54, #1
-; VBITS_GE_2048-NEXT:    strh w11, [sp, #240]
-; VBITS_GE_2048-NEXT:    sbfx x11, x9, #53, #1
-; VBITS_GE_2048-NEXT:    strh w12, [sp, #238]
-; VBITS_GE_2048-NEXT:    sbfx x12, x9, #52, #1
-; VBITS_GE_2048-NEXT:    strh w10, [sp, #236]
-; VBITS_GE_2048-NEXT:    sbfx x10, x9, #51, #1
-; VBITS_GE_2048-NEXT:    strh w11, [sp, #234]
-; VBITS_GE_2048-NEXT:    sbfx x11, x9, #50, #1
-; VBITS_GE_2048-NEXT:    strh w12, [sp, #232]
-; VBITS_GE_2048-NEXT:    sbfx x12, x9, #49, #1
-; VBITS_GE_2048-NEXT:    strh w10, [sp, #230]
-; VBITS_GE_2048-NEXT:    sbfx x10, x9, #48, #1
-; VBITS_GE_2048-NEXT:    strh w11, [sp, #228]
-; VBITS_GE_2048-NEXT:    sbfx x11, x9, #47, #1
-; VBITS_GE_2048-NEXT:    strh w12, [sp, #226]
-; VBITS_GE_2048-NEXT:    sbfx x12, x9, #46, #1
-; VBITS_GE_2048-NEXT:    strh w10, [sp, #224]
-; VBITS_GE_2048-NEXT:    sbfx x10, x9, #45, #1
-; VBITS_GE_2048-NEXT:    strh w11, [sp, #222]
-; VBITS_GE_2048-NEXT:    sbfx x11, x9, #44, #1
-; VBITS_GE_2048-NEXT:    strh w12, [sp, #220]
-; VBITS_GE_2048-NEXT:    sbfx x12, x9, #43, #1
-; VBITS_GE_2048-NEXT:    strh w10, [sp, #218]
-; VBITS_GE_2048-NEXT:    sbfx x10, x9, #42, #1
-; VBITS_GE_2048-NEXT:    strh w11, [sp, #216]
-; VBITS_GE_2048-NEXT:    sbfx x11, x9, #41, #1
-; VBITS_GE_2048-NEXT:    strh w12, [sp, #214]
-; VBITS_GE_2048-NEXT:    sbfx x12, x9, #40, #1
-; VBITS_GE_2048-NEXT:    strh w10, [sp, #212]
-; VBITS_GE_2048-NEXT:    sbfx x10, x9, #39, #1
-; VBITS_GE_2048-NEXT:    strh w11, [sp, #210]
-; VBITS_GE_2048-NEXT:    sbfx x11, x9, #38, #1
-; VBITS_GE_2048-NEXT:    strh w12, [sp, #208]
-; VBITS_GE_2048-NEXT:    sbfx x12, x9, #37, #1
-; VBITS_GE_2048-NEXT:    strh w10, [sp, #206]
-; VBITS_GE_2048-NEXT:    sbfx x10, x9, #36, #1
-; VBITS_GE_2048-NEXT:    strh w11, [sp, #204]
-; VBITS_GE_2048-NEXT:    sbfx x11, x9, #35, #1
-; VBITS_GE_2048-NEXT:    strh w12, [sp, #202]
-; VBITS_GE_2048-NEXT:    sbfx x12, x9, #34, #1
-; VBITS_GE_2048-NEXT:    strh w10, [sp, #200]
-; VBITS_GE_2048-NEXT:    sbfx x10, x9, #33, #1
-; VBITS_GE_2048-NEXT:    strh w11, [sp, #198]
-; VBITS_GE_2048-NEXT:    sbfx x11, x9, #32, #1
-; VBITS_GE_2048-NEXT:    strh w12, [sp, #196]
-; VBITS_GE_2048-NEXT:    asr w12, w9, #31
-; VBITS_GE_2048-NEXT:    strh w10, [sp, #194]
-; VBITS_GE_2048-NEXT:    sbfx w10, w9, #30, #1
-; VBITS_GE_2048-NEXT:    strh w11, [sp, #192]
-; VBITS_GE_2048-NEXT:    sbfx w11, w9, #29, #1
-; VBITS_GE_2048-NEXT:    strh w12, [sp, #190]
-; VBITS_GE_2048-NEXT:    sbfx w12, w9, #28, #1
-; VBITS_GE_2048-NEXT:    strh w10, [sp, #188]
-; VBITS_GE_2048-NEXT:    sbfx w10, w9, #27, #1
-; VBITS_GE_2048-NEXT:    strh w11, [sp, #186]
-; VBITS_GE_2048-NEXT:    sbfx w11, w9, #26, #1
-; VBITS_GE_2048-NEXT:    strh w12, [sp, #184]
-; VBITS_GE_2048-NEXT:    sbfx w12, w9, #25, #1
-; VBITS_GE_2048-NEXT:    strh w10, [sp, #182]
-; VBITS_GE_2048-NEXT:    sbfx w10, w9, #24, #1
-; VBITS_GE_2048-NEXT:    strh w11, [sp, #180]
-; VBITS_GE_2048-NEXT:    sbfx w11, w9, #23, #1
-; VBITS_GE_2048-NEXT:    strh w12, [sp, #178]
-; VBITS_GE_2048-NEXT:    sbfx w12, w9, #22, #1
-; VBITS_GE_2048-NEXT:    strh w10, [sp, #176]
-; VBITS_GE_2048-NEXT:    sbfx w10, w9, #21, #1
-; VBITS_GE_2048-NEXT:    strh w11, [sp, #174]
-; VBITS_GE_2048-NEXT:    sbfx w11, w9, #20, #1
-; VBITS_GE_2048-NEXT:    strh w12, [sp, #172]
-; VBITS_GE_2048-NEXT:    sbfx w12, w9, #19, #1
-; VBITS_GE_2048-NEXT:    strh w10, [sp, #170]
-; VBITS_GE_2048-NEXT:    sbfx w10, w9, #18, #1
-; VBITS_GE_2048-NEXT:    strh w11, [sp, #168]
-; VBITS_GE_2048-NEXT:    sbfx w11, w9, #17, #1
-; VBITS_GE_2048-NEXT:    strh w12, [sp, #166]
-; VBITS_GE_2048-NEXT:    sbfx w12, w9, #16, #1
-; VBITS_GE_2048-NEXT:    strh w10, [sp, #164]
-; VBITS_GE_2048-NEXT:    sbfx w10, w9, #15, #1
-; VBITS_GE_2048-NEXT:    strh w11, [sp, #162]
-; VBITS_GE_2048-NEXT:    sbfx w11, w9, #14, #1
-; VBITS_GE_2048-NEXT:    strh w12, [sp, #160]
-; VBITS_GE_2048-NEXT:    sbfx w12, w9, #13, #1
-; VBITS_GE_2048-NEXT:    strh w10, [sp, #158]
-; VBITS_GE_2048-NEXT:    sbfx w10, w9, #12, #1
-; VBITS_GE_2048-NEXT:    strh w11, [sp, #156]
-; VBITS_GE_2048-NEXT:    sbfx w11, w9, #11, #1
-; VBITS_GE_2048-NEXT:    strh w12, [sp, #154]
-; VBITS_GE_2048-NEXT:    sbfx w12, w9, #10, #1
-; VBITS_GE_2048-NEXT:    strh w10, [sp, #152]
-; VBITS_GE_2048-NEXT:    sbfx w10, w9, #9, #1
-; VBITS_GE_2048-NEXT:    strh w11, [sp, #150]
-; VBITS_GE_2048-NEXT:    sbfx w11, w9, #8, #1
-; VBITS_GE_2048-NEXT:    strh w12, [sp, #148]
-; VBITS_GE_2048-NEXT:    sbfx w12, w9, #7, #1
-; VBITS_GE_2048-NEXT:    strh w10, [sp, #146]
-; VBITS_GE_2048-NEXT:    sbfx w10, w9, #6, #1
-; VBITS_GE_2048-NEXT:    strh w11, [sp, #144]
-; VBITS_GE_2048-NEXT:    sbfx w11, w9, #5, #1
-; VBITS_GE_2048-NEXT:    strh w12, [sp, #142]
-; VBITS_GE_2048-NEXT:    sbfx w12, w9, #4, #1
-; VBITS_GE_2048-NEXT:    strh w10, [sp, #140]
-; VBITS_GE_2048-NEXT:    sbfx w10, w9, #3, #1
-; VBITS_GE_2048-NEXT:    strh w11, [sp, #138]
-; VBITS_GE_2048-NEXT:    sbfx w11, w9, #2, #1
-; VBITS_GE_2048-NEXT:    strh w12, [sp, #136]
-; VBITS_GE_2048-NEXT:    sbfx w12, w9, #1, #1
-; VBITS_GE_2048-NEXT:    sbfx w9, w9, #0, #1
-; VBITS_GE_2048-NEXT:    strh w10, [sp, #134]
-; VBITS_GE_2048-NEXT:    strh w11, [sp, #132]
-; VBITS_GE_2048-NEXT:    strh w12, [sp, #130]
-; VBITS_GE_2048-NEXT:    strh w9, [sp, #128]
-; VBITS_GE_2048-NEXT:    ldr x9, [x2]
-; VBITS_GE_2048-NEXT:    asr x10, x9, #63
-; VBITS_GE_2048-NEXT:    sbfx x11, x9, #62, #1
-; VBITS_GE_2048-NEXT:    sbfx x12, x9, #61, #1
-; VBITS_GE_2048-NEXT:    strh w10, [sp, #126]
-; VBITS_GE_2048-NEXT:    sbfx x10, x9, #60, #1
-; VBITS_GE_2048-NEXT:    strh w11, [sp, #124]
-; VBITS_GE_2048-NEXT:    sbfx x11, x9, #59, #1
-; VBITS_GE_2048-NEXT:    strh w12, [sp, #122]
-; VBITS_GE_2048-NEXT:    sbfx x12, x9, #58, #1
-; VBITS_GE_2048-NEXT:    strh w10, [sp, #120]
-; VBITS_GE_2048-NEXT:    sbfx x10, x9, #57, #1
-; VBITS_GE_2048-NEXT:    strh w11, [sp, #118]
-; VBITS_GE_2048-NEXT:    sbfx x11, x9, #56, #1
-; VBITS_GE_2048-NEXT:    strh w12, [sp, #116]
-; VBITS_GE_2048-NEXT:    sbfx x12, x9, #55, #1
-; VBITS_GE_2048-NEXT:    strh w10, [sp, #114]
-; VBITS_GE_2048-NEXT:    sbfx x10, x9, #54, #1
-; VBITS_GE_2048-NEXT:    strh w11, [sp, #112]
-; VBITS_GE_2048-NEXT:    sbfx x11, x9, #53, #1
-; VBITS_GE_2048-NEXT:    strh w12, [sp, #110]
-; VBITS_GE_2048-NEXT:    sbfx x12, x9, #52, #1
-; VBITS_GE_2048-NEXT:    strh w10, [sp, #108]
-; VBITS_GE_2048-NEXT:    sbfx x10, x9, #51, #1
-; VBITS_GE_2048-NEXT:    strh w11, [sp, #106]
-; VBITS_GE_2048-NEXT:    sbfx x11, x9, #50, #1
-; VBITS_GE_2048-NEXT:    strh w12, [sp, #104]
-; VBITS_GE_2048-NEXT:    sbfx x12, x9, #49, #1
-; VBITS_GE_2048-NEXT:    strh w10, [sp, #102]
-; VBITS_GE_2048-NEXT:    sbfx x10, x9, #48, #1
-; VBITS_GE_2048-NEXT:    strh w11, [sp, #100]
-; VBITS_GE_2048-NEXT:    sbfx x11, x9, #47, #1
-; VBITS_GE_2048-NEXT:    strh w12, [sp, #98]
-; VBITS_GE_2048-NEXT:    sbfx x12, x9, #46, #1
-; VBITS_GE_2048-NEXT:    strh w10, [sp, #96]
-; VBITS_GE_2048-NEXT:    sbfx x10, x9, #45, #1
-; VBITS_GE_2048-NEXT:    strh w11, [sp, #94]
-; VBITS_GE_2048-NEXT:    sbfx x11, x9, #44, #1
-; VBITS_GE_2048-NEXT:    strh w12, [sp, #92]
-; VBITS_GE_2048-NEXT:    sbfx x12, x9, #43, #1
-; VBITS_GE_2048-NEXT:    strh w10, [sp, #90]
-; VBITS_GE_2048-NEXT:    sbfx x10, x9, #42, #1
-; VBITS_GE_2048-NEXT:    strh w11, [sp, #88]
-; VBITS_GE_2048-NEXT:    sbfx x11, x9, #41, #1
-; VBITS_GE_2048-NEXT:    strh w12, [sp, #86]
-; VBITS_GE_2048-NEXT:    sbfx x12, x9, #40, #1
-; VBITS_GE_2048-NEXT:    strh w10, [sp, #84]
-; VBITS_GE_2048-NEXT:    sbfx x10, x9, #39, #1
-; VBITS_GE_2048-NEXT:    strh w11, [sp, #82]
-; VBITS_GE_2048-NEXT:    sbfx x11, x9, #38, #1
-; VBITS_GE_2048-NEXT:    strh w12, [sp, #80]
-; VBITS_GE_2048-NEXT:    sbfx x12, x9, #37, #1
-; VBITS_GE_2048-NEXT:    strh w10, [sp, #78]
-; VBITS_GE_2048-NEXT:    sbfx x10, x9, #36, #1
-; VBITS_GE_2048-NEXT:    strh w11, [sp, #76]
-; VBITS_GE_2048-NEXT:    sbfx x11, x9, #35, #1
-; VBITS_GE_2048-NEXT:    strh w12, [sp, #74]
-; VBITS_GE_2048-NEXT:    sbfx x12, x9, #34, #1
-; VBITS_GE_2048-NEXT:    strh w10, [sp, #72]
-; VBITS_GE_2048-NEXT:    sbfx x10, x9, #33, #1
-; VBITS_GE_2048-NEXT:    strh w11, [sp, #70]
-; VBITS_GE_2048-NEXT:    sbfx x11, x9, #32, #1
-; VBITS_GE_2048-NEXT:    strh w12, [sp, #68]
-; VBITS_GE_2048-NEXT:    asr w12, w9, #31
-; VBITS_GE_2048-NEXT:    strh w10, [sp, #66]
-; VBITS_GE_2048-NEXT:    sbfx w10, w9, #30, #1
-; VBITS_GE_2048-NEXT:    strh w11, [sp, #64]
-; VBITS_GE_2048-NEXT:    sbfx w11, w9, #29, #1
-; VBITS_GE_2048-NEXT:    strh w12, [sp, #62]
-; VBITS_GE_2048-NEXT:    sbfx w12, w9, #28, #1
-; VBITS_GE_2048-NEXT:    strh w10, [sp, #60]
-; VBITS_GE_2048-NEXT:    sbfx w10, w9, #27, #1
-; VBITS_GE_2048-NEXT:    strh w11, [sp, #58]
-; VBITS_GE_2048-NEXT:    sbfx w11, w9, #26, #1
-; VBITS_GE_2048-NEXT:    strh w12, [sp, #56]
-; VBITS_GE_2048-NEXT:    sbfx w12, w9, #25, #1
-; VBITS_GE_2048-NEXT:    strh w10, [sp, #54]
-; VBITS_GE_2048-NEXT:    sbfx w10, w9, #24, #1
-; VBITS_GE_2048-NEXT:    strh w11, [sp, #52]
-; VBITS_GE_2048-NEXT:    sbfx w11, w9, #23, #1
-; VBITS_GE_2048-NEXT:    strh w12, [sp, #50]
-; VBITS_GE_2048-NEXT:    sbfx w12, w9, #22, #1
-; VBITS_GE_2048-NEXT:    strh w10, [sp, #48]
-; VBITS_GE_2048-NEXT:    sbfx w10, w9, #21, #1
-; VBITS_GE_2048-NEXT:    strh w11, [sp, #46]
-; VBITS_GE_2048-NEXT:    sbfx w11, w9, #20, #1
-; VBITS_GE_2048-NEXT:    strh w12, [sp, #44]
-; VBITS_GE_2048-NEXT:    sbfx w12, w9, #19, #1
-; VBITS_GE_2048-NEXT:    strh w10, [sp, #42]
-; VBITS_GE_2048-NEXT:    sbfx w10, w9, #18, #1
-; VBITS_GE_2048-NEXT:    strh w11, [sp, #40]
-; VBITS_GE_2048-NEXT:    sbfx w11, w9, #17, #1
-; VBITS_GE_2048-NEXT:    strh w12, [sp, #38]
-; VBITS_GE_2048-NEXT:    sbfx w12, w9, #16, #1
-; VBITS_GE_2048-NEXT:    strh w10, [sp, #36]
-; VBITS_GE_2048-NEXT:    sbfx w10, w9, #15, #1
-; VBITS_GE_2048-NEXT:    strh w11, [sp, #34]
-; VBITS_GE_2048-NEXT:    sbfx w11, w9, #14, #1
-; VBITS_GE_2048-NEXT:    strh w12, [sp, #32]
-; VBITS_GE_2048-NEXT:    sbfx w12, w9, #13, #1
-; VBITS_GE_2048-NEXT:    strh w10, [sp, #30]
-; VBITS_GE_2048-NEXT:    sbfx w10, w9, #12, #1
-; VBITS_GE_2048-NEXT:    strh w11, [sp, #28]
-; VBITS_GE_2048-NEXT:    sbfx w11, w9, #11, #1
-; VBITS_GE_2048-NEXT:    strh w12, [sp, #26]
-; VBITS_GE_2048-NEXT:    sbfx w12, w9, #10, #1
-; VBITS_GE_2048-NEXT:    strh w10, [sp, #24]
-; VBITS_GE_2048-NEXT:    sbfx w10, w9, #9, #1
-; VBITS_GE_2048-NEXT:    strh w11, [sp, #22]
-; VBITS_GE_2048-NEXT:    sbfx w11, w9, #8, #1
-; VBITS_GE_2048-NEXT:    strh w12, [sp, #20]
-; VBITS_GE_2048-NEXT:    sbfx w12, w9, #7, #1
-; VBITS_GE_2048-NEXT:    strh w10, [sp, #18]
-; VBITS_GE_2048-NEXT:    sbfx w10, w9, #6, #1
-; VBITS_GE_2048-NEXT:    strh w11, [sp, #16]
-; VBITS_GE_2048-NEXT:    sbfx w11, w9, #5, #1
-; VBITS_GE_2048-NEXT:    strh w12, [sp, #14]
-; VBITS_GE_2048-NEXT:    sbfx w12, w9, #4, #1
-; VBITS_GE_2048-NEXT:    strh w10, [sp, #12]
-; VBITS_GE_2048-NEXT:    sbfx w10, w9, #3, #1
-; VBITS_GE_2048-NEXT:    strh w11, [sp, #10]
-; VBITS_GE_2048-NEXT:    sbfx w11, w9, #2, #1
-; VBITS_GE_2048-NEXT:    strh w12, [sp, #8]
-; VBITS_GE_2048-NEXT:    sbfx w12, w9, #1, #1
-; VBITS_GE_2048-NEXT:    sbfx w9, w9, #0, #1
-; VBITS_GE_2048-NEXT:    strh w10, [sp, #6]
-; VBITS_GE_2048-NEXT:    strh w11, [sp, #4]
-; VBITS_GE_2048-NEXT:    strh w12, [sp, #2]
-; VBITS_GE_2048-NEXT:    strh w9, [sp]
-; VBITS_GE_2048-NEXT:    ld1h { z0.h }, p0/z, [x8]
+; VBITS_GE_2048-NEXT:    asr x9, x8, #63
+; VBITS_GE_2048-NEXT:    sbfx x10, x8, #62, #1
+; VBITS_GE_2048-NEXT:    sbfx x11, x8, #61, #1
+; VBITS_GE_2048-NEXT:    strh w9, [sp, #254]
+; VBITS_GE_2048-NEXT:    sbfx x9, x8, #60, #1
+; VBITS_GE_2048-NEXT:    strh w10, [sp, #252]
+; VBITS_GE_2048-NEXT:    sbfx x10, x8, #59, #1
+; VBITS_GE_2048-NEXT:    strh w11, [sp, #250]
+; VBITS_GE_2048-NEXT:    sbfx x11, x8, #58, #1
+; VBITS_GE_2048-NEXT:    strh w9, [sp, #248]
+; VBITS_GE_2048-NEXT:    sbfx x9, x8, #57, #1
+; VBITS_GE_2048-NEXT:    strh w10, [sp, #246]
+; VBITS_GE_2048-NEXT:    sbfx x10, x8, #56, #1
+; VBITS_GE_2048-NEXT:    strh w11, [sp, #244]
+; VBITS_GE_2048-NEXT:    sbfx x11, x8, #55, #1
+; VBITS_GE_2048-NEXT:    strh w9, [sp, #242]
+; VBITS_GE_2048-NEXT:    sbfx x9, x8, #54, #1
+; VBITS_GE_2048-NEXT:    strh w10, [sp, #240]
+; VBITS_GE_2048-NEXT:    sbfx x10, x8, #53, #1
+; VBITS_GE_2048-NEXT:    strh w11, [sp, #238]
+; VBITS_GE_2048-NEXT:    sbfx x11, x8, #52, #1
+; VBITS_GE_2048-NEXT:    strh w9, [sp, #236]
+; VBITS_GE_2048-NEXT:    sbfx x9, x8, #51, #1
+; VBITS_GE_2048-NEXT:    strh w10, [sp, #234]
+; VBITS_GE_2048-NEXT:    sbfx x10, x8, #50, #1
+; VBITS_GE_2048-NEXT:    strh w11, [sp, #232]
+; VBITS_GE_2048-NEXT:    sbfx x11, x8, #49, #1
+; VBITS_GE_2048-NEXT:    strh w9, [sp, #230]
+; VBITS_GE_2048-NEXT:    sbfx x9, x8, #48, #1
+; VBITS_GE_2048-NEXT:    strh w10, [sp, #228]
+; VBITS_GE_2048-NEXT:    sbfx x10, x8, #47, #1
+; VBITS_GE_2048-NEXT:    strh w11, [sp, #226]
+; VBITS_GE_2048-NEXT:    sbfx x11, x8, #46, #1
+; VBITS_GE_2048-NEXT:    strh w9, [sp, #224]
+; VBITS_GE_2048-NEXT:    sbfx x9, x8, #45, #1
+; VBITS_GE_2048-NEXT:    strh w10, [sp, #222]
+; VBITS_GE_2048-NEXT:    sbfx x10, x8, #44, #1
+; VBITS_GE_2048-NEXT:    strh w11, [sp, #220]
+; VBITS_GE_2048-NEXT:    sbfx x11, x8, #43, #1
+; VBITS_GE_2048-NEXT:    strh w9, [sp, #218]
+; VBITS_GE_2048-NEXT:    sbfx x9, x8, #42, #1
+; VBITS_GE_2048-NEXT:    strh w10, [sp, #216]
+; VBITS_GE_2048-NEXT:    sbfx x10, x8, #41, #1
+; VBITS_GE_2048-NEXT:    strh w11, [sp, #214]
+; VBITS_GE_2048-NEXT:    sbfx x11, x8, #40, #1
+; VBITS_GE_2048-NEXT:    strh w9, [sp, #212]
+; VBITS_GE_2048-NEXT:    sbfx x9, x8, #39, #1
+; VBITS_GE_2048-NEXT:    strh w10, [sp, #210]
+; VBITS_GE_2048-NEXT:    sbfx x10, x8, #38, #1
+; VBITS_GE_2048-NEXT:    strh w11, [sp, #208]
+; VBITS_GE_2048-NEXT:    sbfx x11, x8, #37, #1
+; VBITS_GE_2048-NEXT:    strh w9, [sp, #206]
+; VBITS_GE_2048-NEXT:    sbfx x9, x8, #36, #1
+; VBITS_GE_2048-NEXT:    strh w10, [sp, #204]
+; VBITS_GE_2048-NEXT:    sbfx x10, x8, #35, #1
+; VBITS_GE_2048-NEXT:    strh w11, [sp, #202]
+; VBITS_GE_2048-NEXT:    sbfx x11, x8, #34, #1
+; VBITS_GE_2048-NEXT:    strh w9, [sp, #200]
+; VBITS_GE_2048-NEXT:    sbfx x9, x8, #33, #1
+; VBITS_GE_2048-NEXT:    strh w10, [sp, #198]
+; VBITS_GE_2048-NEXT:    sbfx x10, x8, #32, #1
+; VBITS_GE_2048-NEXT:    strh w11, [sp, #196]
+; VBITS_GE_2048-NEXT:    asr w11, w8, #31
+; VBITS_GE_2048-NEXT:    strh w9, [sp, #194]
+; VBITS_GE_2048-NEXT:    sbfx w9, w8, #30, #1
+; VBITS_GE_2048-NEXT:    strh w10, [sp, #192]
+; VBITS_GE_2048-NEXT:    sbfx w10, w8, #29, #1
+; VBITS_GE_2048-NEXT:    strh w11, [sp, #190]
+; VBITS_GE_2048-NEXT:    sbfx w11, w8, #28, #1
+; VBITS_GE_2048-NEXT:    strh w9, [sp, #188]
+; VBITS_GE_2048-NEXT:    sbfx w9, w8, #27, #1
+; VBITS_GE_2048-NEXT:    strh w10, [sp, #186]
+; VBITS_GE_2048-NEXT:    sbfx w10, w8, #26, #1
+; VBITS_GE_2048-NEXT:    strh w11, [sp, #184]
+; VBITS_GE_2048-NEXT:    sbfx w11, w8, #25, #1
+; VBITS_GE_2048-NEXT:    strh w9, [sp, #182]
+; VBITS_GE_2048-NEXT:    sbfx w9, w8, #24, #1
+; VBITS_GE_2048-NEXT:    strh w10, [sp, #180]
+; VBITS_GE_2048-NEXT:    sbfx w10, w8, #23, #1
+; VBITS_GE_2048-NEXT:    strh w11, [sp, #178]
+; VBITS_GE_2048-NEXT:    sbfx w11, w8, #22, #1
+; VBITS_GE_2048-NEXT:    strh w9, [sp, #176]
+; VBITS_GE_2048-NEXT:    sbfx w9, w8, #21, #1
+; VBITS_GE_2048-NEXT:    strh w10, [sp, #174]
+; VBITS_GE_2048-NEXT:    sbfx w10, w8, #20, #1
+; VBITS_GE_2048-NEXT:    strh w11, [sp, #172]
+; VBITS_GE_2048-NEXT:    sbfx w11, w8, #19, #1
+; VBITS_GE_2048-NEXT:    strh w9, [sp, #170]
+; VBITS_GE_2048-NEXT:    sbfx w9, w8, #18, #1
+; VBITS_GE_2048-NEXT:    strh w10, [sp, #168]
+; VBITS_GE_2048-NEXT:    sbfx w10, w8, #17, #1
+; VBITS_GE_2048-NEXT:    strh w11, [sp, #166]
+; VBITS_GE_2048-NEXT:    sbfx w11, w8, #16, #1
+; VBITS_GE_2048-NEXT:    strh w9, [sp, #164]
+; VBITS_GE_2048-NEXT:    sbfx w9, w8, #15, #1
+; VBITS_GE_2048-NEXT:    strh w10, [sp, #162]
+; VBITS_GE_2048-NEXT:    sbfx w10, w8, #14, #1
+; VBITS_GE_2048-NEXT:    strh w11, [sp, #160]
+; VBITS_GE_2048-NEXT:    sbfx w11, w8, #13, #1
+; VBITS_GE_2048-NEXT:    strh w9, [sp, #158]
+; VBITS_GE_2048-NEXT:    sbfx w9, w8, #12, #1
+; VBITS_GE_2048-NEXT:    strh w10, [sp, #156]
+; VBITS_GE_2048-NEXT:    sbfx w10, w8, #11, #1
+; VBITS_GE_2048-NEXT:    strh w11, [sp, #154]
+; VBITS_GE_2048-NEXT:    sbfx w11, w8, #10, #1
+; VBITS_GE_2048-NEXT:    strh w9, [sp, #152]
+; VBITS_GE_2048-NEXT:    sbfx w9, w8, #9, #1
+; VBITS_GE_2048-NEXT:    strh w10, [sp, #150]
+; VBITS_GE_2048-NEXT:    sbfx w10, w8, #8, #1
+; VBITS_GE_2048-NEXT:    strh w11, [sp, #148]
+; VBITS_GE_2048-NEXT:    sbfx w11, w8, #7, #1
+; VBITS_GE_2048-NEXT:    strh w9, [sp, #146]
+; VBITS_GE_2048-NEXT:    sbfx w9, w8, #6, #1
+; VBITS_GE_2048-NEXT:    strh w10, [sp, #144]
+; VBITS_GE_2048-NEXT:    sbfx w10, w8, #5, #1
+; VBITS_GE_2048-NEXT:    strh w11, [sp, #142]
+; VBITS_GE_2048-NEXT:    sbfx w11, w8, #4, #1
+; VBITS_GE_2048-NEXT:    strh w9, [sp, #140]
+; VBITS_GE_2048-NEXT:    sbfx w9, w8, #3, #1
+; VBITS_GE_2048-NEXT:    strh w10, [sp, #138]
+; VBITS_GE_2048-NEXT:    sbfx w10, w8, #2, #1
+; VBITS_GE_2048-NEXT:    strh w11, [sp, #136]
+; VBITS_GE_2048-NEXT:    sbfx w11, w8, #1, #1
+; VBITS_GE_2048-NEXT:    sbfx w8, w8, #0, #1
+; VBITS_GE_2048-NEXT:    strh w9, [sp, #134]
+; VBITS_GE_2048-NEXT:    strh w10, [sp, #132]
+; VBITS_GE_2048-NEXT:    strh w11, [sp, #130]
+; VBITS_GE_2048-NEXT:    strh w8, [sp, #128]
+; VBITS_GE_2048-NEXT:    ldr x8, [x2]
+; VBITS_GE_2048-NEXT:    asr x9, x8, #63
+; VBITS_GE_2048-NEXT:    sbfx x10, x8, #62, #1
+; VBITS_GE_2048-NEXT:    sbfx x11, x8, #61, #1
+; VBITS_GE_2048-NEXT:    strh w9, [sp, #126]
+; VBITS_GE_2048-NEXT:    sbfx x9, x8, #60, #1
+; VBITS_GE_2048-NEXT:    strh w10, [sp, #124]
+; VBITS_GE_2048-NEXT:    sbfx x10, x8, #59, #1
+; VBITS_GE_2048-NEXT:    strh w11, [sp, #122]
+; VBITS_GE_2048-NEXT:    sbfx x11, x8, #58, #1
+; VBITS_GE_2048-NEXT:    strh w9, [sp, #120]
+; VBITS_GE_2048-NEXT:    sbfx x9, x8, #57, #1
+; VBITS_GE_2048-NEXT:    strh w10, [sp, #118]
+; VBITS_GE_2048-NEXT:    sbfx x10, x8, #56, #1
+; VBITS_GE_2048-NEXT:    strh w11, [sp, #116]
+; VBITS_GE_2048-NEXT:    sbfx x11, x8, #55, #1
+; VBITS_GE_2048-NEXT:    strh w9, [sp, #114]
+; VBITS_GE_2048-NEXT:    sbfx x9, x8, #54, #1
+; VBITS_GE_2048-NEXT:    strh w10, [sp, #112]
+; VBITS_GE_2048-NEXT:    sbfx x10, x8, #53, #1
+; VBITS_GE_2048-NEXT:    strh w11, [sp, #110]
+; VBITS_GE_2048-NEXT:    sbfx x11, x8, #52, #1
+; VBITS_GE_2048-NEXT:    strh w9, [sp, #108]
+; VBITS_GE_2048-NEXT:    sbfx x9, x8, #51, #1
+; VBITS_GE_2048-NEXT:    strh w10, [sp, #106]
+; VBITS_GE_2048-NEXT:    sbfx x10, x8, #50, #1
+; VBITS_GE_2048-NEXT:    strh w11, [sp, #104]
+; VBITS_GE_2048-NEXT:    sbfx x11, x8, #49, #1
+; VBITS_GE_2048-NEXT:    strh w9, [sp, #102]
+; VBITS_GE_2048-NEXT:    sbfx x9, x8, #48, #1
+; VBITS_GE_2048-NEXT:    strh w10, [sp, #100]
+; VBITS_GE_2048-NEXT:    sbfx x10, x8, #47, #1
+; VBITS_GE_2048-NEXT:    strh w11, [sp, #98]
+; VBITS_GE_2048-NEXT:    sbfx x11, x8, #46, #1
+; VBITS_GE_2048-NEXT:    strh w9, [sp, #96]
+; VBITS_GE_2048-NEXT:    sbfx x9, x8, #45, #1
+; VBITS_GE_2048-NEXT:    strh w10, [sp, #94]
+; VBITS_GE_2048-NEXT:    sbfx x10, x8, #44, #1
+; VBITS_GE_2048-NEXT:    strh w11, [sp, #92]
+; VBITS_GE_2048-NEXT:    sbfx x11, x8, #43, #1
+; VBITS_GE_2048-NEXT:    strh w9, [sp, #90]
+; VBITS_GE_2048-NEXT:    sbfx x9, x8, #42, #1
+; VBITS_GE_2048-NEXT:    strh w10, [sp, #88]
+; VBITS_GE_2048-NEXT:    sbfx x10, x8, #41, #1
+; VBITS_GE_2048-NEXT:    strh w11, [sp, #86]
+; VBITS_GE_2048-NEXT:    sbfx x11, x8, #40, #1
+; VBITS_GE_2048-NEXT:    strh w9, [sp, #84]
+; VBITS_GE_2048-NEXT:    sbfx x9, x8, #39, #1
+; VBITS_GE_2048-NEXT:    strh w10, [sp, #82]
+; VBITS_GE_2048-NEXT:    sbfx x10, x8, #38, #1
+; VBITS_GE_2048-NEXT:    strh w11, [sp, #80]
+; VBITS_GE_2048-NEXT:    sbfx x11, x8, #37, #1
+; VBITS_GE_2048-NEXT:    strh w9, [sp, #78]
+; VBITS_GE_2048-NEXT:    sbfx x9, x8, #36, #1
+; VBITS_GE_2048-NEXT:    strh w10, [sp, #76]
+; VBITS_GE_2048-NEXT:    sbfx x10, x8, #35, #1
+; VBITS_GE_2048-NEXT:    strh w11, [sp, #74]
+; VBITS_GE_2048-NEXT:    sbfx x11, x8, #34, #1
+; VBITS_GE_2048-NEXT:    strh w9, [sp, #72]
+; VBITS_GE_2048-NEXT:    sbfx x9, x8, #33, #1
+; VBITS_GE_2048-NEXT:    strh w10, [sp, #70]
+; VBITS_GE_2048-NEXT:    sbfx x10, x8, #32, #1
+; VBITS_GE_2048-NEXT:    strh w11, [sp, #68]
+; VBITS_GE_2048-NEXT:    asr w11, w8, #31
+; VBITS_GE_2048-NEXT:    strh w9, [sp, #66]
+; VBITS_GE_2048-NEXT:    sbfx w9, w8, #30, #1
+; VBITS_GE_2048-NEXT:    strh w10, [sp, #64]
+; VBITS_GE_2048-NEXT:    sbfx w10, w8, #29, #1
+; VBITS_GE_2048-NEXT:    strh w11, [sp, #62]
+; VBITS_GE_2048-NEXT:    sbfx w11, w8, #28, #1
+; VBITS_GE_2048-NEXT:    strh w9, [sp, #60]
+; VBITS_GE_2048-NEXT:    sbfx w9, w8, #27, #1
+; VBITS_GE_2048-NEXT:    strh w10, [sp, #58]
+; VBITS_GE_2048-NEXT:    sbfx w10, w8, #26, #1
+; VBITS_GE_2048-NEXT:    strh w11, [sp, #56]
+; VBITS_GE_2048-NEXT:    sbfx w11, w8, #25, #1
+; VBITS_GE_2048-NEXT:    strh w9, [sp, #54]
+; VBITS_GE_2048-NEXT:    sbfx w9, w8, #24, #1
+; VBITS_GE_2048-NEXT:    strh w10, [sp, #52]
+; VBITS_GE_2048-NEXT:    sbfx w10, w8, #23, #1
+; VBITS_GE_2048-NEXT:    strh w11, [sp, #50]
+; VBITS_GE_2048-NEXT:    sbfx w11, w8, #22, #1
+; VBITS_GE_2048-NEXT:    strh w9, [sp, #48]
+; VBITS_GE_2048-NEXT:    sbfx w9, w8, #21, #1
+; VBITS_GE_2048-NEXT:    strh w10, [sp, #46]
+; VBITS_GE_2048-NEXT:    sbfx w10, w8, #20, #1
+; VBITS_GE_2048-NEXT:    strh w11, [sp, #44]
+; VBITS_GE_2048-NEXT:    sbfx w11, w8, #19, #1
+; VBITS_GE_2048-NEXT:    strh w9, [sp, #42]
+; VBITS_GE_2048-NEXT:    sbfx w9, w8, #18, #1
+; VBITS_GE_2048-NEXT:    strh w10, [sp, #40]
+; VBITS_GE_2048-NEXT:    sbfx w10, w8, #17, #1
+; VBITS_GE_2048-NEXT:    strh w11, [sp, #38]
+; VBITS_GE_2048-NEXT:    sbfx w11, w8, #16, #1
+; VBITS_GE_2048-NEXT:    strh w9, [sp, #36]
+; VBITS_GE_2048-NEXT:    sbfx w9, w8, #15, #1
+; VBITS_GE_2048-NEXT:    strh w10, [sp, #34]
+; VBITS_GE_2048-NEXT:    sbfx w10, w8, #14, #1
+; VBITS_GE_2048-NEXT:    strh w11, [sp, #32]
+; VBITS_GE_2048-NEXT:    sbfx w11, w8, #13, #1
+; VBITS_GE_2048-NEXT:    strh w9, [sp, #30]
+; VBITS_GE_2048-NEXT:    sbfx w9, w8, #12, #1
+; VBITS_GE_2048-NEXT:    strh w10, [sp, #28]
+; VBITS_GE_2048-NEXT:    sbfx w10, w8, #11, #1
+; VBITS_GE_2048-NEXT:    strh w11, [sp, #26]
+; VBITS_GE_2048-NEXT:    sbfx w11, w8, #10, #1
+; VBITS_GE_2048-NEXT:    strh w9, [sp, #24]
+; VBITS_GE_2048-NEXT:    sbfx w9, w8, #9, #1
+; VBITS_GE_2048-NEXT:    strh w10, [sp, #22]
+; VBITS_GE_2048-NEXT:    sbfx w10, w8, #8, #1
+; VBITS_GE_2048-NEXT:    strh w11, [sp, #20]
+; VBITS_GE_2048-NEXT:    sbfx w11, w8, #7, #1
+; VBITS_GE_2048-NEXT:    strh w9, [sp, #18]
+; VBITS_GE_2048-NEXT:    sbfx w9, w8, #6, #1
+; VBITS_GE_2048-NEXT:    strh w10, [sp, #16]
+; VBITS_GE_2048-NEXT:    sbfx w10, w8, #5, #1
+; VBITS_GE_2048-NEXT:    strh w11, [sp, #14]
+; VBITS_GE_2048-NEXT:    sbfx w11, w8, #4, #1
+; VBITS_GE_2048-NEXT:    strh w9, [sp, #12]
+; VBITS_GE_2048-NEXT:    sbfx w9, w8, #3, #1
+; VBITS_GE_2048-NEXT:    strh w10, [sp, #10]
+; VBITS_GE_2048-NEXT:    sbfx w10, w8, #2, #1
+; VBITS_GE_2048-NEXT:    strh w11, [sp, #8]
+; VBITS_GE_2048-NEXT:    sbfx w11, w8, #1, #1
+; VBITS_GE_2048-NEXT:    sbfx w8, w8, #0, #1
+; VBITS_GE_2048-NEXT:    strh w9, [sp, #6]
+; VBITS_GE_2048-NEXT:    strh w10, [sp, #4]
+; VBITS_GE_2048-NEXT:    strh w11, [sp, #2]
+; VBITS_GE_2048-NEXT:    strh w8, [sp]
+; VBITS_GE_2048-NEXT:    ld1h { z0.h }, p0/z, [sp]
 ; VBITS_GE_2048-NEXT:    ld1h { z1.h }, p0/z, [x0]
 ; VBITS_GE_2048-NEXT:    ld1h { z2.h }, p0/z, [x1]
 ; VBITS_GE_2048-NEXT:    and z0.h, z0.h, #0x1
 ; VBITS_GE_2048-NEXT:    cmpne p1.h, p1/z, z0.h, #0
 ; VBITS_GE_2048-NEXT:    sel z0.h, p1, z1.h, z2.h
 ; VBITS_GE_2048-NEXT:    st1h { z0.h }, p0, [x0]
 ; VBITS_GE_2048-NEXT:    mov sp, x29
 ; VBITS_GE_2048-NEXT:    ldp x29, x30, [sp], #16 // 16-byte Folded Reload

 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    stp x29, x30, [sp, #-16]! // 16-byte Folded Spill
 ; CHECK-NEXT:    sub x9, sp, #48
 ; CHECK-NEXT:    mov x29, sp
 ; CHECK-NEXT:    and sp, x9, #0xffffffffffffffe0
 ; CHECK-NEXT:    .cfi_def_cfa w29, 16
 ; CHECK-NEXT:    .cfi_offset w30, -8
 ; CHECK-NEXT:    .cfi_offset w29, -16
-; CHECK-NEXT:    ldrb w9, [x2]
-; CHECK-NEXT:    mov x8, sp
+; CHECK-NEXT:    ldrb w8, [x2]
 ; CHECK-NEXT:    ptrue p0.s, vl8
 ; CHECK-NEXT:    ptrue p1.s
-; CHECK-NEXT:    sbfx w10, w9, #7, #1
-; CHECK-NEXT:    sbfx w11, w9, #6, #1
-; CHECK-NEXT:    sbfx w12, w9, #5, #1
-; CHECK-NEXT:    sbfx w13, w9, #4, #1
-; CHECK-NEXT:    stp w11, w10, [sp, #24]
-; CHECK-NEXT:    sbfx w10, w9, #3, #1
-; CHECK-NEXT:    sbfx w11, w9, #2, #1
-; CHECK-NEXT:    stp w13, w12, [sp, #16]
-; CHECK-NEXT:    sbfx w12, w9, #1, #1
-; CHECK-NEXT:    sbfx w9, w9, #0, #1
-; CHECK-NEXT:    stp w11, w10, [sp, #8]
-; CHECK-NEXT:    stp w9, w12, [sp]
-; CHECK-NEXT:    ld1w { z0.s }, p0/z, [x8]
+; CHECK-NEXT:    sbfx w9, w8, #7, #1
+; CHECK-NEXT:    sbfx w10, w8, #6, #1
+; CHECK-NEXT:    sbfx w11, w8, #5, #1
+; CHECK-NEXT:    sbfx w12, w8, #4, #1
+; CHECK-NEXT:    stp w10, w9, [sp, #24]
+; CHECK-NEXT:    sbfx w9, w8, #3, #1
+; CHECK-NEXT:    sbfx w10, w8, #2, #1
+; CHECK-NEXT:    stp w12, w11, [sp, #16]
+; CHECK-NEXT:    sbfx w11, w8, #1, #1
+; CHECK-NEXT:    sbfx w8, w8, #0, #1
+; CHECK-NEXT:    stp w10, w9, [sp, #8]
+; CHECK-NEXT:    stp w8, w11, [sp]
+; CHECK-NEXT:    ld1w { z0.s }, p0/z, [sp]
 ; CHECK-NEXT:    ld1w { z1.s }, p0/z, [x0]
 ; CHECK-NEXT:    ld1w { z2.s }, p0/z, [x1]
 ; CHECK-NEXT:    and z0.s, z0.s, #0x1
 ; CHECK-NEXT:    cmpne p1.s, p1/z, z0.s, #0
 ; CHECK-NEXT:    sel z0.s, p1, z1.s, z2.s
 ; CHECK-NEXT:    st1w { z0.s }, p0, [x0]
 ; CHECK-NEXT:    mov sp, x29
 ; CHECK-NEXT:    ldp x29, x30, [sp], #16 // 16-byte Folded Reload

 ; VBITS_GE_512:       // %bb.0:
 ; VBITS_GE_512-NEXT:    stp x29, x30, [sp, #-16]! // 16-byte Folded Spill
 ; VBITS_GE_512-NEXT:    sub x9, sp, #112
 ; VBITS_GE_512-NEXT:    mov x29, sp
 ; VBITS_GE_512-NEXT:    and sp, x9, #0xffffffffffffffc0
 ; VBITS_GE_512-NEXT:    .cfi_def_cfa w29, 16
 ; VBITS_GE_512-NEXT:    .cfi_offset w30, -8
 ; VBITS_GE_512-NEXT:    .cfi_offset w29, -16
-; VBITS_GE_512-NEXT:    ldrh w9, [x2]
-; VBITS_GE_512-NEXT:    mov x8, sp
+; VBITS_GE_512-NEXT:    ldrh w8, [x2]
 ; VBITS_GE_512-NEXT:    ptrue p0.s, vl16
 ; VBITS_GE_512-NEXT:    ptrue p1.s
-; VBITS_GE_512-NEXT:    sbfx w10, w9, #15, #1
-; VBITS_GE_512-NEXT:    sbfx w11, w9, #14, #1
-; VBITS_GE_512-NEXT:    sbfx w12, w9, #13, #1
-; VBITS_GE_512-NEXT:    sbfx w13, w9, #12, #1
-; VBITS_GE_512-NEXT:    stp w11, w10, [sp, #56]
-; VBITS_GE_512-NEXT:    sbfx w10, w9, #11, #1
-; VBITS_GE_512-NEXT:    sbfx w11, w9, #10, #1
-; VBITS_GE_512-NEXT:    stp w13, w12, [sp, #48]
-; VBITS_GE_512-NEXT:    sbfx w12, w9, #9, #1
-; VBITS_GE_512-NEXT:    sbfx w13, w9, #8, #1
-; VBITS_GE_512-NEXT:    stp w11, w10, [sp, #40]
-; VBITS_GE_512-NEXT:    sbfx w10, w9, #7, #1
-; VBITS_GE_512-NEXT:    sbfx w11, w9, #6, #1
-; VBITS_GE_512-NEXT:    stp w13, w12, [sp, #32]
-; VBITS_GE_512-NEXT:    sbfx w12, w9, #5, #1
-; VBITS_GE_512-NEXT:    sbfx w13, w9, #4, #1
-; VBITS_GE_512-NEXT:    stp w11, w10, [sp, #24]
-; VBITS_GE_512-NEXT:    sbfx w10, w9, #3, #1
-; VBITS_GE_512-NEXT:    sbfx w11, w9, #2, #1
-; VBITS_GE_512-NEXT:    stp w13, w12, [sp, #16]
-; VBITS_GE_512-NEXT:    sbfx w12, w9, #1, #1
-; VBITS_GE_512-NEXT:    sbfx w9, w9, #0, #1
-; VBITS_GE_512-NEXT:    stp w11, w10, [sp, #8]
-; VBITS_GE_512-NEXT:    stp w9, w12, [sp]
-; VBITS_GE_512-NEXT:    ld1w { z0.s }, p0/z, [x8]
+; VBITS_GE_512-NEXT:    sbfx w9, w8, #15, #1
+; VBITS_GE_512-NEXT:    sbfx w10, w8, #14, #1
+; VBITS_GE_512-NEXT:    sbfx w11, w8, #13, #1
+; VBITS_GE_512-NEXT:    sbfx w12, w8, #12, #1
+; VBITS_GE_512-NEXT:    stp w10, w9, [sp, #56]
+; VBITS_GE_512-NEXT:    sbfx w9, w8, #11, #1
+; VBITS_GE_512-NEXT:    sbfx w10, w8, #10, #1
+; VBITS_GE_512-NEXT:    stp w12, w11, [sp, #48]
+; VBITS_GE_512-NEXT:    sbfx w11, w8, #9, #1
+; VBITS_GE_512-NEXT:    sbfx w12, w8, #8, #1
+; VBITS_GE_512-NEXT:    stp w10, w9, [sp, #40]
+; VBITS_GE_512-NEXT:    sbfx w9, w8, #7, #1
+; VBITS_GE_512-NEXT:    sbfx w10, w8, #6, #1
+; VBITS_GE_512-NEXT:    stp w12, w11, [sp, #32]
+; VBITS_GE_512-NEXT:    sbfx w11, w8, #5, #1
+; VBITS_GE_512-NEXT:    sbfx w12, w8, #4, #1
+; VBITS_GE_512-NEXT:    stp w10, w9, [sp, #24]
+; VBITS_GE_512-NEXT:    sbfx w9, w8, #3, #1
+; VBITS_GE_512-NEXT:    sbfx w10, w8, #2, #1
+; VBITS_GE_512-NEXT:    stp w12, w11, [sp, #16]
+; VBITS_GE_512-NEXT:    sbfx w11, w8, #1, #1
+; VBITS_GE_512-NEXT:    sbfx w8, w8, #0, #1
+; VBITS_GE_512-NEXT:    stp w10, w9, [sp, #8]
+; VBITS_GE_512-NEXT:    stp w8, w11, [sp]
+; VBITS_GE_512-NEXT:    ld1w { z0.s }, p0/z, [sp]
 ; VBITS_GE_512-NEXT:    ld1w { z1.s }, p0/z, [x0]
 ; VBITS_GE_512-NEXT:    ld1w { z2.s }, p0/z, [x1]
 ; VBITS_GE_512-NEXT:    and z0.s, z0.s, #0x1
 ; VBITS_GE_512-NEXT:    cmpne p1.s, p1/z, z0.s, #0
 ; VBITS_GE_512-NEXT:    sel z0.s, p1, z1.s, z2.s
 ; VBITS_GE_512-NEXT:    st1w { z0.s }, p0, [x0]
 ; VBITS_GE_512-NEXT:    mov sp, x29
 ; VBITS_GE_512-NEXT:    ldp x29, x30, [sp], #16 // 16-byte Folded Reload

 ; VBITS_GE_1024:       // %bb.0:
 ; VBITS_GE_1024-NEXT:    stp x29, x30, [sp, #-16]! // 16-byte Folded Spill
 ; VBITS_GE_1024-NEXT:    sub x9, sp, #240
 ; VBITS_GE_1024-NEXT:    mov x29, sp
 ; VBITS_GE_1024-NEXT:    and sp, x9, #0xffffffffffffff80
 ; VBITS_GE_1024-NEXT:    .cfi_def_cfa w29, 16
 ; VBITS_GE_1024-NEXT:    .cfi_offset w30, -8
 ; VBITS_GE_1024-NEXT:    .cfi_offset w29, -16
-; VBITS_GE_1024-NEXT:    ldr w9, [x2]
-; VBITS_GE_1024-NEXT:    mov x8, sp
+; VBITS_GE_1024-NEXT:    ldr w8, [x2]
 ; VBITS_GE_1024-NEXT:    ptrue p0.s, vl32
 ; VBITS_GE_1024-NEXT:    ptrue p1.s
-; VBITS_GE_1024-NEXT:    asr w10, w9, #31
-; VBITS_GE_1024-NEXT:    sbfx w11, w9, #30, #1
-; VBITS_GE_1024-NEXT:    sbfx w12, w9, #29, #1
-; VBITS_GE_1024-NEXT:    sbfx w13, w9, #28, #1
-; VBITS_GE_1024-NEXT:    stp w11, w10, [sp, #120]
-; VBITS_GE_1024-NEXT:    sbfx w10, w9, #27, #1
-; VBITS_GE_1024-NEXT:    sbfx w11, w9, #26, #1
-; VBITS_GE_1024-NEXT:    stp w13, w12, [sp, #112]
-; VBITS_GE_1024-NEXT:    sbfx w12, w9, #25, #1
-; VBITS_GE_1024-NEXT:    sbfx w13, w9, #24, #1
-; VBITS_GE_1024-NEXT:    stp w11, w10, [sp, #104]
-; VBITS_GE_1024-NEXT:    sbfx w10, w9, #23, #1
-; VBITS_GE_1024-NEXT:    sbfx w11, w9, #22, #1
-; VBITS_GE_1024-NEXT:    stp w13, w12, [sp, #96]
-; VBITS_GE_1024-NEXT:    sbfx w12, w9, #21, #1
-; VBITS_GE_1024-NEXT:    sbfx w13, w9, #20, #1
-; VBITS_GE_1024-NEXT:    stp w11, w10, [sp, #88]
-; VBITS_GE_1024-NEXT:    sbfx w10, w9, #19, #1
-; VBITS_GE_1024-NEXT:    sbfx w11, w9, #18, #1
-; VBITS_GE_1024-NEXT:    stp w13, w12, [sp, #80]
-; VBITS_GE_1024-NEXT:    sbfx w12, w9, #17, #1
-; VBITS_GE_1024-NEXT:    sbfx w13, w9, #16, #1
-; VBITS_GE_1024-NEXT:    stp w11, w10, [sp, #72]
-; VBITS_GE_1024-NEXT:    sbfx w10, w9, #15, #1
-; VBITS_GE_1024-NEXT:    sbfx w11, w9, #14, #1
-; VBITS_GE_1024-NEXT:    stp w13, w12, [sp, #64]
-; VBITS_GE_1024-NEXT:    sbfx w12, w9, #13, #1
-; VBITS_GE_1024-NEXT:    sbfx w13, w9, #12, #1
-; VBITS_GE_1024-NEXT:    stp w11, w10, [sp, #56]
-; VBITS_GE_1024-NEXT:    sbfx w10, w9, #11, #1
-; VBITS_GE_1024-NEXT:    sbfx w11, w9, #10, #1
-; VBITS_GE_1024-NEXT:    stp w13, w12, [sp, #48]
-; VBITS_GE_1024-NEXT:    sbfx w12, w9, #9, #1
-; VBITS_GE_1024-NEXT:    sbfx w13, w9, #8, #1
-; VBITS_GE_1024-NEXT:    stp w11, w10, [sp, #40]
-; VBITS_GE_1024-NEXT:    sbfx w10, w9, #7, #1
-; VBITS_GE_1024-NEXT:    sbfx w11, w9, #6, #1
-; VBITS_GE_1024-NEXT:    stp w13, w12, [sp, #32]
-; VBITS_GE_1024-NEXT:    sbfx w12, w9, #5, #1
-; VBITS_GE_1024-NEXT:    sbfx w13, w9, #4, #1
-; VBITS_GE_1024-NEXT:    stp w11, w10, [sp, #24]
-; VBITS_GE_1024-NEXT:    sbfx w10, w9, #3, #1
-; VBITS_GE_1024-NEXT:    sbfx w11, w9, #2, #1
-; VBITS_GE_1024-NEXT:    stp w13, w12, [sp, #16]
-; VBITS_GE_1024-NEXT:    sbfx w12, w9, #1, #1
-; VBITS_GE_1024-NEXT:    sbfx w9, w9, #0, #1
-; VBITS_GE_1024-NEXT:    stp w11, w10, [sp, #8]
-; VBITS_GE_1024-NEXT:    stp w9, w12, [sp]
-; VBITS_GE_1024-NEXT:    ld1w { z0.s }, p0/z, [x8]
+; VBITS_GE_1024-NEXT:    asr w9, w8, #31
+; VBITS_GE_1024-NEXT:    sbfx w10, w8, #30, #1
+; VBITS_GE_1024-NEXT:    sbfx w11, w8, #29, #1
+; VBITS_GE_1024-NEXT:    sbfx w12, w8, #28, #1
+; VBITS_GE_1024-NEXT:    stp w10, w9, [sp, #120]
+; VBITS_GE_1024-NEXT:    sbfx w9, w8, #27, #1
+; VBITS_GE_1024-NEXT:    sbfx w10, w8, #26, #1
+; VBITS_GE_1024-NEXT:    stp w12, w11, [sp, #112]
+; VBITS_GE_1024-NEXT:    sbfx w11, w8, #25, #1
+; VBITS_GE_1024-NEXT:    sbfx w12, w8, #24, #1
+; VBITS_GE_1024-NEXT:    stp w10, w9, [sp, #104]
+; VBITS_GE_1024-NEXT:    sbfx w9, w8, #23, #1
+; VBITS_GE_1024-NEXT:    sbfx w10, w8, #22, #1
+; VBITS_GE_1024-NEXT:    stp w12, w11, [sp, #96]
+; VBITS_GE_1024-NEXT:    sbfx w11, w8, #21, #1
+; VBITS_GE_1024-NEXT:    sbfx w12, w8, #20, #1
+; VBITS_GE_1024-NEXT:    stp w10, w9, [sp, #88]
+; VBITS_GE_1024-NEXT:    sbfx w9, w8, #19, #1
+; VBITS_GE_1024-NEXT:    sbfx w10, w8, #18, #1
+; VBITS_GE_1024-NEXT:    stp w12, w11, [sp, #80]
+; VBITS_GE_1024-NEXT:    sbfx w11, w8, #17, #1
+; VBITS_GE_1024-NEXT:    sbfx w12, w8, #16, #1
+; VBITS_GE_1024-NEXT:    stp w10, w9, [sp, #72]
+; VBITS_GE_1024-NEXT:    sbfx w9, w8, #15, #1
+; VBITS_GE_1024-NEXT:    sbfx w10, w8, #14, #1
+; VBITS_GE_1024-NEXT:    stp w12, w11, [sp, #64]
+; VBITS_GE_1024-NEXT:    sbfx w11, w8, #13, #1
+; VBITS_GE_1024-NEXT:    sbfx w12, w8, #12, #1
+; VBITS_GE_1024-NEXT:    stp w10, w9, [sp, #56]
+; VBITS_GE_1024-NEXT:    sbfx w9, w8, #11, #1
+; VBITS_GE_1024-NEXT:    sbfx w10, w8, #10, #1
+; VBITS_GE_1024-NEXT:    stp w12, w11, [sp, #48]
+; VBITS_GE_1024-NEXT:    sbfx w11, w8, #9, #1
+; VBITS_GE_1024-NEXT:    sbfx w12, w8, #8, #1
+; VBITS_GE_1024-NEXT:    stp w10, w9, [sp, #40]
+; VBITS_GE_1024-NEXT:    sbfx w9, w8, #7, #1
+; VBITS_GE_1024-NEXT:    sbfx w10, w8, #6, #1
+; VBITS_GE_1024-NEXT:    stp w12, w11, [sp, #32]
+; VBITS_GE_1024-NEXT:    sbfx w11, w8, #5, #1
+; VBITS_GE_1024-NEXT:    sbfx w12, w8, #4, #1
+; VBITS_GE_1024-NEXT:    stp w10, w9, [sp, #24]
+; VBITS_GE_1024-NEXT:    sbfx w9, w8, #3, #1
+; VBITS_GE_1024-NEXT:    sbfx w10, w8, #2, #1
+; VBITS_GE_1024-NEXT:    stp w12, w11, [sp, #16]
+; VBITS_GE_1024-NEXT:    sbfx w11, w8, #1, #1
+; VBITS_GE_1024-NEXT:    sbfx w8, w8, #0, #1
+; VBITS_GE_1024-NEXT:    stp w10, w9, [sp, #8]
+; VBITS_GE_1024-NEXT:    stp w8, w11, [sp]
+; VBITS_GE_1024-NEXT:    ld1w { z0.s }, p0/z, [sp]
 ; VBITS_GE_1024-NEXT:    ld1w { z1.s }, p0/z, [x0]
 ; VBITS_GE_1024-NEXT:    ld1w { z2.s }, p0/z, [x1]
 ; VBITS_GE_1024-NEXT:    and z0.s, z0.s, #0x1
 ; VBITS_GE_1024-NEXT:    cmpne p1.s, p1/z, z0.s, #0
 ; VBITS_GE_1024-NEXT:    sel z0.s, p1, z1.s, z2.s
 ; VBITS_GE_1024-NEXT:    st1w { z0.s }, p0, [x0]
 ; VBITS_GE_1024-NEXT:    mov sp, x29
 ; VBITS_GE_1024-NEXT:    ldp x29, x30, [sp], #16 // 16-byte Folded Reload

 ; VBITS_GE_2048:       // %bb.0:
 ; VBITS_GE_2048-NEXT:    stp x29, x30, [sp, #-16]! // 16-byte Folded Spill
 ; VBITS_GE_2048-NEXT:    sub x9, sp, #496
 ; VBITS_GE_2048-NEXT:    mov x29, sp
 ; VBITS_GE_2048-NEXT:    and sp, x9, #0xffffffffffffff00
 ; VBITS_GE_2048-NEXT:    .cfi_def_cfa w29, 16
 ; VBITS_GE_2048-NEXT:    .cfi_offset w30, -8
 ; VBITS_GE_2048-NEXT:    .cfi_offset w29, -16
-; VBITS_GE_2048-NEXT:    ldr x9, [x2]
-; VBITS_GE_2048-NEXT:    mov x8, sp
+; VBITS_GE_2048-NEXT:    ldr x8, [x2]
 ; VBITS_GE_2048-NEXT:    ptrue p0.s, vl64
 ; VBITS_GE_2048-NEXT:    ptrue p1.s
-; VBITS_GE_2048-NEXT:    asr x10, x9, #63
-; VBITS_GE_2048-NEXT:    sbfx x11, x9, #62, #1
-; VBITS_GE_2048-NEXT:    sbfx x12, x9, #61, #1
-; VBITS_GE_2048-NEXT:    sbfx x13, x9, #60, #1
-; VBITS_GE_2048-NEXT:    stp w11, w10, [sp, #248]
-; VBITS_GE_2048-NEXT:    sbfx x10, x9, #59, #1
-; VBITS_GE_2048-NEXT:    sbfx x11, x9, #58, #1
-; VBITS_GE_2048-NEXT:    stp w13, w12, [sp, #240]
-; VBITS_GE_2048-NEXT:    sbfx x12, x9, #57, #1
-; VBITS_GE_2048-NEXT:    sbfx x13, x9, #56, #1
-; VBITS_GE_2048-NEXT:    stp w11, w10, [sp, #232]
-; VBITS_GE_2048-NEXT:    sbfx x10, x9, #55, #1
-; VBITS_GE_2048-NEXT:    sbfx x11, x9, #54, #1
-; VBITS_GE_2048-NEXT:    stp w13, w12, [sp, #224]
-; VBITS_GE_2048-NEXT:    sbfx x12, x9, #53, #1
-; VBITS_GE_2048-NEXT:    sbfx x13, x9, #52, #1
-; VBITS_GE_2048-NEXT:    stp w11, w10, [sp, #216]
-; VBITS_GE_2048-NEXT:    sbfx x10, x9, #51, #1
-; VBITS_GE_2048-NEXT:    sbfx x11, x9, #50, #1
-; VBITS_GE_2048-NEXT:    stp w13, w12, [sp, #208]
-; VBITS_GE_2048-NEXT:    sbfx x12, x9, #49, #1
-; VBITS_GE_2048-NEXT:    sbfx x13, x9, #48, #1
-; VBITS_GE_2048-NEXT:    stp w11, w10, [sp, #200]
-; VBITS_GE_2048-NEXT:    sbfx x10, x9, #47, #1
-; VBITS_GE_2048-NEXT:    sbfx x11, x9, #46, #1
-; VBITS_GE_2048-NEXT:    stp w13, w12, [sp, #192]
-; VBITS_GE_2048-NEXT:    sbfx x12, x9, #45, #1
-; VBITS_GE_2048-NEXT:    sbfx x13, x9, #44, #1
-; VBITS_GE_2048-NEXT:    stp w11, w10, [sp, #184]
-; VBITS_GE_2048-NEXT:    sbfx x10, x9, #43, #1
-; VBITS_GE_2048-NEXT:    sbfx x11, x9, #42, #1
-; VBITS_GE_2048-NEXT:    stp w13, w12, [sp, #176]
-; VBITS_GE_2048-NEXT:    sbfx x12, x9, #41, #1
-; VBITS_GE_2048-NEXT:    sbfx x13, x9, #40, #1
-; VBITS_GE_2048-NEXT:    stp w11, w10, [sp, #168]
-; VBITS_GE_2048-NEXT:    sbfx x10, x9, #39, #1
-; VBITS_GE_2048-NEXT:    sbfx x11, x9, #38, #1
-; VBITS_GE_2048-NEXT:    stp w13, w12, [sp, #160]
-; VBITS_GE_2048-NEXT:    sbfx x12, x9, #37, #1
-; VBITS_GE_2048-NEXT:    sbfx x13, x9, #36, #1
-; VBITS_GE_2048-NEXT:    stp w11, w10, [sp, #152]
-; VBITS_GE_2048-NEXT:    sbfx x10, x9, #35, #1
-; VBITS_GE_2048-NEXT:    sbfx x11, x9, #34, #1
-; VBITS_GE_2048-NEXT:    stp w13, w12, [sp, #144]
-; VBITS_GE_2048-NEXT:    sbfx x12, x9, #33, #1
-; VBITS_GE_2048-NEXT:    sbfx x13, x9, #32, #1
-; VBITS_GE_2048-NEXT:    stp w11, w10, [sp, #136]
-; VBITS_GE_2048-NEXT:    asr w10, w9, #31
-; VBITS_GE_2048-NEXT:    sbfx w11, w9, #30, #1
-; VBITS_GE_2048-NEXT:    stp w13, w12, [sp, #128]
-; VBITS_GE_2048-NEXT:    sbfx w12, w9, #29, #1
-; VBITS_GE_2048-NEXT:    sbfx w13, w9, #28, #1
-; VBITS_GE_2048-NEXT:    stp w11, w10, [sp, #120]
-; VBITS_GE_2048-NEXT:    sbfx w10, w9, #27, #1
-; VBITS_GE_2048-NEXT:    sbfx w11, w9, #26, #1
-; VBITS_GE_2048-NEXT:    stp w13, w12, [sp, #112]
-; VBITS_GE_2048-NEXT:    sbfx w12, w9, #25, #1
-; VBITS_GE_2048-NEXT:    sbfx w13, w9, #24, #1
-; VBITS_GE_2048-NEXT:    stp w11, w10, [sp, #104]
-; VBITS_GE_2048-NEXT:    sbfx w10, w9, #23, #1
-; VBITS_GE_2048-NEXT:    sbfx w11, w9, #22, #1
-; VBITS_GE_2048-NEXT:    stp w13, w12, [sp, #96]
-; VBITS_GE_2048-NEXT:    sbfx w12, w9, #21, #1
-; VBITS_GE_2048-NEXT:    sbfx w13, w9, #20, #1
-; VBITS_GE_2048-NEXT:    stp w11, w10, [sp, #88]
-; VBITS_GE_2048-NEXT:    sbfx w10, w9, #19, #1
-; VBITS_GE_2048-NEXT:    sbfx w11, w9, #18, #1
-; VBITS_GE_2048-NEXT:    stp w13, w12, [sp, #80]
-; VBITS_GE_2048-NEXT:    sbfx w12, w9, #17, #1
-; VBITS_GE_2048-NEXT:    sbfx w13, w9, #16, #1
-; VBITS_GE_2048-NEXT:    stp w11, w10, [sp, #72]
-; VBITS_GE_2048-NEXT:    sbfx w10, w9, #15, #1
-; VBITS_GE_2048-NEXT:    sbfx w11, w9, #14, #1
-; VBITS_GE_2048-NEXT:    stp w13, w12, [sp, #64]
-; VBITS_GE_2048-NEXT:    sbfx w12, w9, #13, #1
-; VBITS_GE_2048-NEXT:    sbfx w13, w9, #12, #1
-; VBITS_GE_2048-NEXT:    stp w11, w10, [sp, #56]
-; VBITS_GE_2048-NEXT:    sbfx w10, w9, #11, #1
-; VBITS_GE_2048-NEXT:    sbfx w11, w9, #10, #1
-; VBITS_GE_2048-NEXT:    stp w13, w12, [sp, #48]
-; VBITS_GE_2048-NEXT:    sbfx w12, w9, #9, #1
-; VBITS_GE_2048-NEXT:    sbfx w13, w9, #8, #1
-; VBITS_GE_2048-NEXT:    stp w11, w10, [sp, #40]
-; VBITS_GE_2048-NEXT:    sbfx w10, w9, #7, #1
-; VBITS_GE_2048-NEXT:    sbfx w11, w9, #6, #1
-; VBITS_GE_2048-NEXT:    stp w13, w12, [sp, #32]
-; VBITS_GE_2048-NEXT:    sbfx w12, w9, #5, #1
-; VBITS_GE_2048-NEXT:    sbfx w13, w9, #4, #1
-; VBITS_GE_2048-NEXT:    stp w11, w10, [sp, #24]
-; VBITS_GE_2048-NEXT:    sbfx w10, w9, #3, #1
-; VBITS_GE_2048-NEXT:    sbfx w11, w9, #2, #1
-; VBITS_GE_2048-NEXT:    stp w13, w12, [sp, #16]
-; VBITS_GE_2048-NEXT:    sbfx w12, w9, #1, #1
-; VBITS_GE_2048-NEXT:    sbfx w9, w9, #0, #1
-; VBITS_GE_2048-NEXT:    stp w11, w10, [sp, #8]
-; VBITS_GE_2048-NEXT:    stp w9, w12, [sp]
-; VBITS_GE_2048-NEXT:    ld1w { z0.s }, p0/z, [x8]
+; VBITS_GE_2048-NEXT:    asr x9, x8, #63
+; VBITS_GE_2048-NEXT:    sbfx x10, x8, #62, #1
+; VBITS_GE_2048-NEXT:    sbfx x11, x8, #61, #1
+; VBITS_GE_2048-NEXT:    sbfx x12, x8, #60, #1
+; VBITS_GE_2048-NEXT:    stp w10, w9, [sp, #248]
+; VBITS_GE_2048-NEXT:    sbfx x9, x8, #59, #1
+; VBITS_GE_2048-NEXT:    sbfx x10, x8, #58, #1
+; VBITS_GE_2048-NEXT:    stp w12, w11, [sp, #240]
+; VBITS_GE_2048-NEXT:    sbfx x11, x8, #57, #1
+; VBITS_GE_2048-NEXT:    sbfx x12, x8, #56, #1
+; VBITS_GE_2048-NEXT:    stp w10, w9, [sp, #232]
+; VBITS_GE_2048-NEXT:    sbfx x9, x8, #55, #1
+; VBITS_GE_2048-NEXT:    sbfx x10, x8, #54, #1
+; VBITS_GE_2048-NEXT:    stp w12, w11, [sp, #224]
+; VBITS_GE_2048-NEXT:    sbfx x11, x8, #53, #1
+; VBITS_GE_2048-NEXT:    sbfx x12, x8, #52, #1
+; VBITS_GE_2048-NEXT:    stp w10, w9, [sp, #216]
+; VBITS_GE_2048-NEXT:    sbfx x9, x8, #51, #1
+; VBITS_GE_2048-NEXT:    sbfx x10, x8, #50, #1
+; VBITS_GE_2048-NEXT:    stp w12, w11, [sp, #208]
+; VBITS_GE_2048-NEXT:    sbfx x11, x8, #49, #1
+; VBITS_GE_2048-NEXT:    sbfx x12, x8, #48, #1
+; VBITS_GE_2048-NEXT:    stp w10, w9, [sp, #200]
+; VBITS_GE_2048-NEXT:    sbfx x9, x8, #47, #1
+; VBITS_GE_2048-NEXT:    sbfx x10, x8, #46, #1
+; VBITS_GE_2048-NEXT:    stp w12, w11, [sp, #192]
+; VBITS_GE_2048-NEXT:    sbfx x11, x8, #45, #1
+; VBITS_GE_2048-NEXT:    sbfx x12, x8, #44, #1
+; VBITS_GE_2048-NEXT:    stp w10, w9, [sp, #184]
+; VBITS_GE_2048-NEXT:    sbfx x9, x8, #43, #1
+; VBITS_GE_2048-NEXT:    sbfx x10, x8, #42, #1
+; VBITS_GE_2048-NEXT:    stp w12, w11, [sp, #176]
+; VBITS_GE_2048-NEXT:    sbfx x11, x8, #41, #1
+; VBITS_GE_2048-NEXT:    sbfx x12, x8, #40, #1
+; VBITS_GE_2048-NEXT:    stp w10, w9, [sp, #168]
+; VBITS_GE_2048-NEXT:    sbfx x9, x8, #39, #1
+; VBITS_GE_2048-NEXT:    sbfx x10, x8, #38, #1
+; VBITS_GE_2048-NEXT:    stp w12, w11, [sp, #160]
+; VBITS_GE_2048-NEXT:    sbfx x11, x8, #37, #1
+; VBITS_GE_2048-NEXT:    sbfx x12, x8, #36, #1
+; VBITS_GE_2048-NEXT:    stp w10, w9, [sp, #152]
+; VBITS_GE_2048-NEXT:    sbfx x9, x8, #35, #1
+; VBITS_GE_2048-NEXT:    sbfx x10, x8, #34, #1
+; VBITS_GE_2048-NEXT:    stp w12, w11, [sp, #144]
+; VBITS_GE_2048-NEXT:    sbfx x11, x8, #33, #1
+; VBITS_GE_2048-NEXT:    sbfx x12, x8, #32, #1
+; VBITS_GE_2048-NEXT:    stp w10, w9, [sp, #136]
+; VBITS_GE_2048-NEXT:    asr w9, w8, #31
+; VBITS_GE_2048-NEXT:    sbfx w10, w8, #30, #1
+; VBITS_GE_2048-NEXT:    stp w12, w11, [sp, #128]
+; VBITS_GE_2048-NEXT:    sbfx w11, w8, #29, #1
+; VBITS_GE_2048-NEXT:    sbfx w12, w8, #28, #1
+; VBITS_GE_2048-NEXT:    stp w10, w9, [sp, #120]
+; VBITS_GE_2048-NEXT:    sbfx w9, w8, #27, #1
+; VBITS_GE_2048-NEXT:    sbfx w10, w8, #26, #1
+; VBITS_GE_2048-NEXT:    stp w12, w11, [sp, #112]
+; VBITS_GE_2048-NEXT:    sbfx w11, w8, #25, #1
+; VBITS_GE_2048-NEXT:    sbfx w12, w8, #24, #1
+; VBITS_GE_2048-NEXT:    stp w10, w9, [sp, #104]
+; VBITS_GE_2048-NEXT:    sbfx w9, w8, #23, #1
+; VBITS_GE_2048-NEXT:    sbfx w10, w8, #22, #1
+; VBITS_GE_2048-NEXT:    stp w12, w11, [sp, #96]
+; VBITS_GE_2048-NEXT:    sbfx w11, w8, #21, #1
+; VBITS_GE_2048-NEXT:    sbfx w12, w8, #20, #1
+; VBITS_GE_2048-NEXT:    stp w10, w9, [sp, #88]
+; VBITS_GE_2048-NEXT:    sbfx w9, w8, #19, #1
+; VBITS_GE_2048-NEXT:    sbfx w10, w8, #18, #1
+; VBITS_GE_2048-NEXT:    stp w12, w11, [sp, #80]
+; VBITS_GE_2048-NEXT:    sbfx w11, w8, #17, #1
+; VBITS_GE_2048-NEXT:    sbfx w12, w8, #16, #1
+; VBITS_GE_2048-NEXT:    stp w10, w9, [sp, #72]
+; VBITS_GE_2048-NEXT:    sbfx w9, w8, #15, #1
+; VBITS_GE_2048-NEXT:    sbfx w10, w8, #14, #1
+; VBITS_GE_2048-NEXT:    stp w12, w11, [sp, #64]
+; VBITS_GE_2048-NEXT:    sbfx w11, w8, #13, #1
+; VBITS_GE_2048-NEXT:    sbfx w12, w8, #12, #1
+; VBITS_GE_2048-NEXT:    stp w10, w9, [sp, #56]
+; VBITS_GE_2048-NEXT:    sbfx w9, w8, #11, #1
+; VBITS_GE_2048-NEXT:    sbfx w10, w8, #10, #1
+; VBITS_GE_2048-NEXT:    stp w12, w11, [sp, #48]
+; VBITS_GE_2048-NEXT:    sbfx w11, w8, #9, #1
+; VBITS_GE_2048-NEXT:    sbfx w12, w8, #8, #1
+; VBITS_GE_2048-NEXT:    stp w10, w9, [sp, #40]
+; VBITS_GE_2048-NEXT:    sbfx w9, w8, #7, #1
+; VBITS_GE_2048-NEXT:    sbfx w10, w8, #6, #1
+; VBITS_GE_2048-NEXT:    stp w12, w11, [sp, #32]
+; VBITS_GE_2048-NEXT:    sbfx w11, w8, #5, #1
+; VBITS_GE_2048-NEXT:    sbfx w12, w8, #4, #1
+; VBITS_GE_2048-NEXT:    stp w10, w9, [sp, #24]
+; VBITS_GE_2048-NEXT:    sbfx w9, w8, #3, #1
+; VBITS_GE_2048-NEXT:    sbfx w10, w8, #2, #1
+; VBITS_GE_2048-NEXT:    stp w12, w11, [sp, #16]
+; VBITS_GE_2048-NEXT:    sbfx w11, w8, #1, #1
+; VBITS_GE_2048-NEXT:    sbfx w8, w8, #0, #1
+; VBITS_GE_2048-NEXT:    stp w10, w9, [sp, #8]
+; VBITS_GE_2048-NEXT:    stp w8, w11, [sp]
+; VBITS_GE_2048-NEXT:    ld1w { z0.s }, p0/z, [sp]
 ; VBITS_GE_2048-NEXT:    ld1w { z1.s }, p0/z, [x0]
 ; VBITS_GE_2048-NEXT:    ld1w { z2.s }, p0/z, [x1]
 ; VBITS_GE_2048-NEXT:    and z0.s, z0.s, #0x1
 ; VBITS_GE_2048-NEXT:    cmpne p1.s, p1/z, z0.s, #0
 ; VBITS_GE_2048-NEXT:    sel z0.s, p1, z1.s, z2.s
 ; VBITS_GE_2048-NEXT:    st1w { z0.s }, p0, [x0]
 ; VBITS_GE_2048-NEXT:    mov sp, x29
 ; VBITS_GE_2048-NEXT:    ldp x29, x30, [sp], #16 // 16-byte Folded Reload

 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    stp x29, x30, [sp, #-16]! // 16-byte Folded Spill
 ; CHECK-NEXT:    sub x9, sp, #48
 ; CHECK-NEXT:    mov x29, sp
 ; CHECK-NEXT:    and sp, x9, #0xffffffffffffffe0
 ; CHECK-NEXT:    .cfi_def_cfa w29, 16
 ; CHECK-NEXT:    .cfi_offset w30, -8
 ; CHECK-NEXT:    .cfi_offset w29, -16
-; CHECK-NEXT:    ldrb w9, [x2]
-; CHECK-NEXT:    mov x8, sp
+; CHECK-NEXT:    ldrb w8, [x2]
 ; CHECK-NEXT:    ptrue p0.d, vl4
 ; CHECK-NEXT:    ptrue p1.d
-; CHECK-NEXT:    lsr w10, w9, #3
-; CHECK-NEXT:    lsr w11, w9, #2
-; CHECK-NEXT:    sbfx x12, x9, #0, #1
-; CHECK-NEXT:    lsr w9, w9, #1
-; CHECK-NEXT:    sbfx x10, x10, #0, #1
-; CHECK-NEXT:    sbfx x11, x11, #0, #1
+; CHECK-NEXT:    lsr w9, w8, #3
+; CHECK-NEXT:    lsr w10, w8, #2
+; CHECK-NEXT:    sbfx x11, x8, #0, #1
+; CHECK-NEXT:    lsr w8, w8, #1
 ; CHECK-NEXT:    sbfx x9, x9, #0, #1
-; CHECK-NEXT:    stp x11, x10, [sp, #16]
-; CHECK-NEXT:    stp x12, x9, [sp]
-; CHECK-NEXT:    ld1d { z0.d }, p0/z, [x8]
+; CHECK-NEXT:    sbfx x10, x10, #0, #1
+; CHECK-NEXT:    sbfx x8, x8, #0, #1
+; CHECK-NEXT:    stp x10, x9, [sp, #16]
+; CHECK-NEXT:    stp x11, x8, [sp]
+; CHECK-NEXT:    ld1d { z0.d }, p0/z, [sp]
 ; CHECK-NEXT:    ld1d { z1.d }, p0/z, [x0]
 ; CHECK-NEXT:    ld1d { z2.d }, p0/z, [x1]
 ; CHECK-NEXT:    and z0.d, z0.d, #0x1
 ; CHECK-NEXT:    cmpne p1.d, p1/z, z0.d, #0
 ; CHECK-NEXT:    sel z0.d, p1, z1.d, z2.d
 ; CHECK-NEXT:    st1d { z0.d }, p0, [x0]
 ; CHECK-NEXT:    mov sp, x29
 ; CHECK-NEXT:    ldp x29, x30, [sp], #16 // 16-byte Folded Reload

 ; VBITS_GE_512:       // %bb.0:
 ; VBITS_GE_512-NEXT:    stp x29, x30, [sp, #-16]! // 16-byte Folded Spill
 ; VBITS_GE_512-NEXT:    sub x9, sp, #112
 ; VBITS_GE_512-NEXT:    mov x29, sp
 ; VBITS_GE_512-NEXT:    and sp, x9, #0xffffffffffffffc0
 ; VBITS_GE_512-NEXT:    .cfi_def_cfa w29, 16
 ; VBITS_GE_512-NEXT:    .cfi_offset w30, -8
 ; VBITS_GE_512-NEXT:    .cfi_offset w29, -16
-; VBITS_GE_512-NEXT:    ldrb w9, [x2]
-; VBITS_GE_512-NEXT:    mov x8, sp
+; VBITS_GE_512-NEXT:    ldrb w8, [x2]
 ; VBITS_GE_512-NEXT:    ptrue p0.d, vl8
 ; VBITS_GE_512-NEXT:    ptrue p1.d
-; VBITS_GE_512-NEXT:    lsr w10, w9, #7
-; VBITS_GE_512-NEXT:    lsr w11, w9, #6
-; VBITS_GE_512-NEXT:    lsr w12, w9, #5
-; VBITS_GE_512-NEXT:    lsr w13, w9, #4
+; VBITS_GE_512-NEXT:    lsr w9, w8, #7
+; VBITS_GE_512-NEXT:    lsr w10, w8, #6
+; VBITS_GE_512-NEXT:    lsr w11, w8, #5
+; VBITS_GE_512-NEXT:    lsr w12, w8, #4
+; VBITS_GE_512-NEXT:    sbfx x9, x9, #0, #1
 ; VBITS_GE_512-NEXT:    sbfx x10, x10, #0, #1
 ; VBITS_GE_512-NEXT:    sbfx x11, x11, #0, #1
 ; VBITS_GE_512-NEXT:    sbfx x12, x12, #0, #1
-; VBITS_GE_512-NEXT:    sbfx x13, x13, #0, #1
-; VBITS_GE_512-NEXT:    lsr w14, w9, #3
-; VBITS_GE_512-NEXT:    stp x11, x10, [sp, #48]
-; VBITS_GE_512-NEXT:    lsr w10, w9, #2
-; VBITS_GE_512-NEXT:    stp x13, x12, [sp, #32]
-; VBITS_GE_512-NEXT:    sbfx x12, x9, #0, #1
-; VBITS_GE_512-NEXT:    lsr w9, w9, #1
-; VBITS_GE_512-NEXT:    sbfx x11, x14, #0, #1
-; VBITS_GE_512-NEXT:    sbfx x10, x10, #0, #1
+; VBITS_GE_512-NEXT:    lsr w13, w8, #3
+; VBITS_GE_512-NEXT:    stp x10, x9, [sp, #48]
+; VBITS_GE_512-NEXT:    lsr w9, w8, #2
+; VBITS_GE_512-NEXT:    stp x12, x11, [sp, #32]
+; VBITS_GE_512-NEXT:    sbfx x11, x8, #0, #1
+; VBITS_GE_512-NEXT:    lsr w8, w8, #1
+; VBITS_GE_512-NEXT:    sbfx x10, x13, #0, #1
 ; VBITS_GE_512-NEXT:    sbfx x9, x9, #0, #1
-; VBITS_GE_512-NEXT:    stp x10, x11, [sp, #16]
-; VBITS_GE_512-NEXT:    stp x12, x9, [sp]
-; VBITS_GE_512-NEXT:    ld1d { z0.d }, p0/z, [x8]
+; VBITS_GE_512-NEXT:    sbfx x8, x8, #0, #1
+; VBITS_GE_512-NEXT:    stp x9, x10, [sp, #16]
+; VBITS_GE_512-NEXT:    stp x11, x8, [sp]
+; VBITS_GE_512-NEXT:    ld1d { z0.d }, p0/z, [sp]
 ; VBITS_GE_512-NEXT:    ld1d { z1.d }, p0/z, [x0]
 ; VBITS_GE_512-NEXT:    ld1d { z2.d }, p0/z, [x1]
 ; VBITS_GE_512-NEXT:    and z0.d, z0.d, #0x1
 ; VBITS_GE_512-NEXT:    cmpne p1.d, p1/z, z0.d, #0
 ; VBITS_GE_512-NEXT:    sel z0.d, p1, z1.d, z2.d
 ; VBITS_GE_512-NEXT:    st1d { z0.d }, p0, [x0]
 ; VBITS_GE_512-NEXT:    mov sp, x29
 ; VBITS_GE_512-NEXT:    ldp x29, x30, [sp], #16 // 16-byte Folded Reload

 ; VBITS_GE_1024:       // %bb.0:
 ; VBITS_GE_1024-NEXT:    stp x29, x30, [sp, #-16]! // 16-byte Folded Spill
 ; VBITS_GE_1024-NEXT:    sub x9, sp, #240
 ; VBITS_GE_1024-NEXT:    mov x29, sp
 ; VBITS_GE_1024-NEXT:    and sp, x9, #0xffffffffffffff80
 ; VBITS_GE_1024-NEXT:    .cfi_def_cfa w29, 16
 ; VBITS_GE_1024-NEXT:    .cfi_offset w30, -8
 ; VBITS_GE_1024-NEXT:    .cfi_offset w29, -16
-; VBITS_GE_1024-NEXT:    ldrh w9, [x2]
-; VBITS_GE_1024-NEXT:    mov x8, sp
+; VBITS_GE_1024-NEXT:    ldrh w8, [x2]
 ; VBITS_GE_1024-NEXT:    ptrue p0.d, vl16
 ; VBITS_GE_1024-NEXT:    ptrue p1.d
-; VBITS_GE_1024-NEXT:    lsr w10, w9, #15
-; VBITS_GE_1024-NEXT:    lsr w11, w9, #14
-; VBITS_GE_1024-NEXT:    lsr w12, w9, #13
-; VBITS_GE_1024-NEXT:    lsr w13, w9, #12
+; VBITS_GE_1024-NEXT:    lsr w9, w8, #15
+; VBITS_GE_1024-NEXT:    lsr w10, w8, #14
+; VBITS_GE_1024-NEXT:    lsr w11, w8, #13
+; VBITS_GE_1024-NEXT:    lsr w12, w8, #12
+; VBITS_GE_1024-NEXT:    sbfx x9, x9, #0, #1
 ; VBITS_GE_1024-NEXT:    sbfx x10, x10, #0, #1
 ; VBITS_GE_1024-NEXT:    sbfx x11, x11, #0, #1
 ; VBITS_GE_1024-NEXT:    sbfx x12, x12, #0, #1
-; VBITS_GE_1024-NEXT:    sbfx x13, x13, #0, #1
-; VBITS_GE_1024-NEXT:    lsr w14, w9, #11
-; VBITS_GE_1024-NEXT:    lsr w15, w9, #10
-; VBITS_GE_1024-NEXT:    stp x11, x10, [sp, #112]
-; VBITS_GE_1024-NEXT:    lsr w10, w9, #9
-; VBITS_GE_1024-NEXT:    stp x13, x12, [sp, #96]
-; VBITS_GE_1024-NEXT:    lsr w13, w9, #8
+; VBITS_GE_1024-NEXT:    lsr w13, w8, #11
+; VBITS_GE_1024-NEXT:    lsr w14, w8, #10
+; VBITS_GE_1024-NEXT:    stp x10, x9, [sp, #112]
+; VBITS_GE_1024-NEXT:    lsr w9, w8, #9
+; VBITS_GE_1024-NEXT:    stp x12, x11, [sp, #96]
+; VBITS_GE_1024-NEXT:    lsr w12, w8, #8
+; VBITS_GE_1024-NEXT:    sbfx x10, x13, #0, #1
 ; VBITS_GE_1024-NEXT:    sbfx x11, x14, #0, #1
-; VBITS_GE_1024-NEXT:    sbfx x12, x15, #0, #1
-; VBITS_GE_1024-NEXT:    sbfx x10, x10, #0, #1
-; VBITS_GE_1024-NEXT:    sbfx x13, x13, #0, #1
-; VBITS_GE_1024-NEXT:    lsr w14, w9, #3
-; VBITS_GE_1024-NEXT:    stp x12, x11, [sp, #80]
-; VBITS_GE_1024-NEXT:    lsr w11, w9, #6
-; VBITS_GE_1024-NEXT:    stp x13, x10, [sp, #64]
-; VBITS_GE_1024-NEXT:    lsr w10, w9, #7
-; VBITS_GE_1024-NEXT:    lsr w12, w9, #5
-; VBITS_GE_1024-NEXT:    lsr w13, w9, #4
+; VBITS_GE_1024-NEXT:    sbfx x9, x9, #0, #1
+; VBITS_GE_1024-NEXT:    sbfx x12, x12, #0, #1
+; VBITS_GE_1024-NEXT:    lsr w13, w8, #3
+; VBITS_GE_1024-NEXT:    stp x11, x10, [sp, #80]
+; VBITS_GE_1024-NEXT:    lsr w10, w8, #6
+; VBITS_GE_1024-NEXT:    stp x12, x9, [sp, #64]
+; VBITS_GE_1024-NEXT:    lsr w9, w8, #7
+; VBITS_GE_1024-NEXT:    lsr w11, w8, #5
+; VBITS_GE_1024-NEXT:    lsr w12, w8, #4
+; VBITS_GE_1024-NEXT:    sbfx x9, x9, #0, #1
 ; VBITS_GE_1024-NEXT:    sbfx x10, x10, #0, #1
 ; VBITS_GE_1024-NEXT:    sbfx x11, x11, #0, #1
 ; VBITS_GE_1024-NEXT:    sbfx x12, x12, #0, #1
-; VBITS_GE_1024-NEXT:    sbfx x13, x13, #0, #1
-; VBITS_GE_1024-NEXT:    stp x11, x10, [sp, #48]
-; VBITS_GE_1024-NEXT:    lsr w11, w9, #2
-; VBITS_GE_1024-NEXT:    stp x13, x12, [sp, #32]
-; VBITS_GE_1024-NEXT:    sbfx x12, x9, #0, #1
-; VBITS_GE_1024-NEXT:    lsr w9, w9, #1
-; VBITS_GE_1024-NEXT:    sbfx x10, x14, #0, #1
-; VBITS_GE_1024-NEXT:    sbfx x11, x11, #0, #1
-; VBITS_GE_1024-NEXT:    sbfx x9, x9, #0, #1
-; VBITS_GE_1024-NEXT:    stp x11, x10, [sp, #16]
-; VBITS_GE_1024-NEXT:    stp x12, x9, [sp]
-; VBITS_GE_1024-NEXT:    ld1d { z0.d }, p0/z, [x8]
+; VBITS_GE_1024-NEXT:    stp x10, x9, [sp, #48]
+; VBITS_GE_1024-NEXT:    lsr w10, w8, #2
+; VBITS_GE_1024-NEXT:    stp x12, x11, [sp, #32]
+; VBITS_GE_1024-NEXT:    sbfx x11, x8, #0, #1
+; VBITS_GE_1024-NEXT:    lsr w8, w8, #1
+; VBITS_GE_1024-NEXT:    sbfx x9, x13, #0, #1
+; VBITS_GE_1024-NEXT:    sbfx x10, x10, #0, #1
+; VBITS_GE_1024-NEXT:    sbfx x8, x8, #0, #1
+; VBITS_GE_1024-NEXT:    stp x10, x9, [sp, #16]
+; VBITS_GE_1024-NEXT:    stp x11, x8, [sp]
+; VBITS_GE_1024-NEXT:    ld1d { z0.d }, p0/z, [sp]
 ; VBITS_GE_1024-NEXT:    ld1d { z1.d }, p0/z, [x0]
 ; VBITS_GE_1024-NEXT:    ld1d { z2.d }, p0/z, [x1]
 ; VBITS_GE_1024-NEXT:    and z0.d, z0.d, #0x1
 ; VBITS_GE_1024-NEXT:    cmpne p1.d, p1/z, z0.d, #0
 ; VBITS_GE_1024-NEXT:    sel z0.d, p1, z1.d, z2.d
 ; VBITS_GE_1024-NEXT:    st1d { z0.d }, p0, [x0]
 ; VBITS_GE_1024-NEXT:    mov sp, x29
 ; VBITS_GE_1024-NEXT:    ldp x29, x30, [sp], #16 // 16-byte Folded Reload

 ; VBITS_GE_2048:       // %bb.0:
 ; VBITS_GE_2048-NEXT:    stp x29, x30, [sp, #-16]! // 16-byte Folded Spill
 ; VBITS_GE_2048-NEXT:    sub x9, sp, #496
 ; VBITS_GE_2048-NEXT:    mov x29, sp
 ; VBITS_GE_2048-NEXT:    and sp, x9, #0xffffffffffffff00
 ; VBITS_GE_2048-NEXT:    .cfi_def_cfa w29, 16
 ; VBITS_GE_2048-NEXT:    .cfi_offset w30, -8
 ; VBITS_GE_2048-NEXT:    .cfi_offset w29, -16
-; VBITS_GE_2048-NEXT:    ldr w9, [x2]
-; VBITS_GE_2048-NEXT:    mov x8, sp
+; VBITS_GE_2048-NEXT:    ldr w8, [x2]
 ; VBITS_GE_2048-NEXT:    ptrue p0.d, vl32
 ; VBITS_GE_2048-NEXT:    ptrue p1.d
-; VBITS_GE_2048-NEXT:    ubfx x10, x9, #31, #1
-; VBITS_GE_2048-NEXT:    ubfx x11, x9, #30, #2
+; VBITS_GE_2048-NEXT:    ubfx x9, x8, #31, #1
+; VBITS_GE_2048-NEXT:    ubfx x10, x8, #30, #2
+; VBITS_GE_2048-NEXT:    // kill: def $w9 killed $w9 killed $x9 def $x9
 ; VBITS_GE_2048-NEXT:    // kill: def $w10 killed $w10 killed $x10 def $x10
-; VBITS_GE_2048-NEXT:    // kill: def $w11 killed $w11 killed $x11 def $x11
-; VBITS_GE_2048-NEXT:    ubfx x12, x9, #29, #3
-; VBITS_GE_2048-NEXT:    ubfx x13, x9, #28, #4
+; VBITS_GE_2048-NEXT:    ubfx x11, x8, #29, #3
+; VBITS_GE_2048-NEXT:    ubfx x12, x8, #28, #4
+; VBITS_GE_2048-NEXT:    sbfx x9, x9, #0, #1
 ; VBITS_GE_2048-NEXT:    sbfx x10, x10, #0, #1
-; VBITS_GE_2048-NEXT:    sbfx x11, x11, #0, #1
+; VBITS_GE_2048-NEXT:    // kill: def $w11 killed $w11 killed $x11 def $x11
 ; VBITS_GE_2048-NEXT:    // kill: def $w12 killed $w12 killed $x12 def $x12
+; VBITS_GE_2048-NEXT:    ubfx x13, x8, #27, #5
+; VBITS_GE_2048-NEXT:    ubfx x14, x8, #26, #6
 ; VBITS_GE_2048-NEXT:    // kill: def $w13 killed $w13 killed $x13 def $x13
-; VBITS_GE_2048-NEXT:    ubfx x14, x9, #27, #5
-; VBITS_GE_2048-NEXT:    ubfx x15, x9, #26, #6
 ; VBITS_GE_2048-NEXT:    // kill: def $w14 killed $w14 killed $x14 def $x14
-; VBITS_GE_2048-NEXT:    // kill: def $w15 killed $w15 killed $x15 def $x15
-; VBITS_GE_2048-NEXT:    stp x11, x10, [sp, #240]
-; VBITS_GE_2048-NEXT:    sbfx x10, x12, #0, #1
+; VBITS_GE_2048-NEXT:    stp x10, x9, [sp, #240]
+; VBITS_GE_2048-NEXT:    sbfx x9, x11, #0, #1
+; VBITS_GE_2048-NEXT:    sbfx x11, x12, #0, #1
 ; VBITS_GE_2048-NEXT:    sbfx x12, x13, #0, #1
-; VBITS_GE_2048-NEXT:    sbfx x13, x14, #0, #1
-; VBITS_GE_2048-NEXT:    ubfx x11, x9, #25, #7
-; VBITS_GE_2048-NEXT:    ubfx x14, x9, #23, #9
-; VBITS_GE_2048-NEXT:    // kill: def $w11 killed $w11 killed $x11 def $x11
-; VBITS_GE_2048-NEXT:    // kill: def $w14 killed $w14 killed $x14 def $x14
-; VBITS_GE_2048-NEXT:    stp x12, x10, [sp, #224]
-; VBITS_GE_2048-NEXT:    sbfx x10, x15, #0, #1
-; VBITS_GE_2048-NEXT:    ubfx x12, x9, #24, #8
-; VBITS_GE_2048-NEXT:    // kill: def $w12 killed $w12 killed $x12 def $x12
-; VBITS_GE_2048-NEXT:    stp x10, x13, [sp, #208]
-; VBITS_GE_2048-NEXT:    sbfx x10, x11, #0, #1
-; VBITS_GE_2048-NEXT:    sbfx x12, x12, #0, #1
-; VBITS_GE_2048-NEXT:    ubfx x11, x9, #22, #10
-; VBITS_GE_2048-NEXT:    sbfx x13, x14, #0, #1
-; VBITS_GE_2048-NEXT:    // kill: def $w11 killed $w11 killed $x11 def $x11
-; VBITS_GE_2048-NEXT:    ubfx x14, x9, #21, #11
-; VBITS_GE_2048-NEXT:    // kill: def $w14 killed $w14 killed $x14 def $x14
-; VBITS_GE_2048-NEXT:    stp x12, x10, [sp, #192]
-; VBITS_GE_2048-NEXT:    sbfx x10, x11, #0, #1
-; VBITS_GE_2048-NEXT:    ubfx x11, x9, #20, #12
-; VBITS_GE_2048-NEXT:    ubfx x12, x9, #19, #13
+; VBITS_GE_2048-NEXT:    ubfx x10, x8, #25, #7
+; VBITS_GE_2048-NEXT:    ubfx x13, x8, #23, #9
+; VBITS_GE_2048-NEXT:    // kill: def $w10 killed $w10 killed $x10 def $x10
+; VBITS_GE_2048-NEXT:    // kill: def $w13 killed $w13 killed $x13 def $x13
+; VBITS_GE_2048-NEXT:    stp x11, x9, [sp, #224]
+; VBITS_GE_2048-NEXT:    sbfx x9, x14, #0, #1
+; VBITS_GE_2048-NEXT:    ubfx x11, x8, #24, #8
 ; VBITS_GE_2048-NEXT:    // kill: def $w11 killed $w11 killed $x11 def $x11
-; VBITS_GE_2048-NEXT:    // kill: def $w12 killed $w12 killed $x12 def $x12
-; VBITS_GE_2048-NEXT:    stp x10, x13, [sp, #176]
-; VBITS_GE_2048-NEXT:    sbfx x10, x14, #0, #1
+; VBITS_GE_2048-NEXT:    stp x9, x12, [sp, #208]
+; VBITS_GE_2048-NEXT:    sbfx x9, x10, #0, #1
 ; VBITS_GE_2048-NEXT:    sbfx x11, x11, #0, #1
-; VBITS_GE_2048-NEXT:    ubfx x13, x9, #18, #14
-; VBITS_GE_2048-NEXT:    sbfx x12, x12, #0, #1
+; VBITS_GE_2048-NEXT:    ubfx x10, x8, #22, #10
+; VBITS_GE_2048-NEXT:    sbfx x12, x13, #0, #1
+; VBITS_GE_2048-NEXT:    // kill: def $w10 killed $w10 killed $x10 def $x10
+; VBITS_GE_2048-NEXT:    ubfx x13, x8, #21, #11
 ; VBITS_GE_2048-NEXT:    // kill: def $w13 killed $w13 killed $x13 def $x13
-; VBITS_GE_2048-NEXT:    ubfx x14, x9, #17, #15
-; VBITS_GE_2048-NEXT:    // kill: def $w14 killed $w14 killed $x14 def $x14
-; VBITS_GE_2048-NEXT:    stp x11, x10, [sp, #160]
-; VBITS_GE_2048-NEXT:    sbfx x10, x13, #0, #1
-; VBITS_GE_2048-NEXT:    ubfx x11, x9, #16, #16
-; VBITS_GE_2048-NEXT:    ubfx x13, x9, #15, #17
+; VBITS_GE_2048-NEXT:    stp x11, x9, [sp, #192]
+; VBITS_GE_2048-NEXT:    sbfx x9, x10, #0, #1
+; VBITS_GE_2048-NEXT:    ubfx x10, x8, #20, #12
+; VBITS_GE_2048-NEXT:    ubfx x11, x8, #19, #13
+; VBITS_GE_2048-NEXT:    // kill: def $w10 killed $w10 killed $x10 def $x10
 ; VBITS_GE_2048-NEXT:    // kill: def $w11 killed $w11 killed $x11 def $x11
-; VBITS_GE_2048-NEXT:    // kill: def $w13 killed $w13 killed $x13 def $x13
-; VBITS_GE_2048-NEXT:    stp x10, x12, [sp, #144]
-; VBITS_GE_2048-NEXT:    sbfx x10, x14, #0, #1
+; VBITS_GE_2048-NEXT:    stp x9, x12, [sp, #176]
+; VBITS_GE_2048-NEXT:    sbfx x9, x13, #0, #1
+; VBITS_GE_2048-NEXT:    sbfx x10, x10, #0, #1
+; VBITS_GE_2048-NEXT:    ubfx x12, x8, #18, #14
 ; VBITS_GE_2048-NEXT:    sbfx x11, x11, #0, #1
-; VBITS_GE_2048-NEXT:    ubfx x12, x9, #14, #18
-; VBITS_GE_2048-NEXT:    sbfx x13, x13, #0, #1
 ; VBITS_GE_2048-NEXT:    // kill: def $w12 killed $w12 killed $x12 def $x12
-; VBITS_GE_2048-NEXT:    ubfx x14, x9, #13, #19
-; VBITS_GE_2048-NEXT:    // kill: def $w14 killed $w14 killed $x14 def $x14
-; VBITS_GE_2048-NEXT:    stp x11, x10, [sp, #128]
-; VBITS_GE_2048-NEXT:    sbfx x10, x12, #0, #1
-; VBITS_GE_2048-NEXT:    ubfx x11, x9, #12, #20
-; VBITS_GE_2048-NEXT:    ubfx x12, x9, #11, #21
-; VBITS_GE_2048-NEXT:    // kill: def $w11 killed $w11 killed $x11 def $x11
+; VBITS_GE_2048-NEXT:    ubfx x13, x8, #17, #15
+; VBITS_GE_2048-NEXT:    // kill: def $w13 killed $w13 killed $x13 def $x13
+; VBITS_GE_2048-NEXT:    stp x10, x9, [sp, #160]
+; VBITS_GE_2048-NEXT:    sbfx x9, x12, #0, #1
+; VBITS_GE_2048-NEXT:    ubfx x10, x8, #16, #16
+; VBITS_GE_2048-NEXT:    ubfx x12, x8, #15, #17
+; VBITS_GE_2048-NEXT:    // kill: def $w10 killed $w10 killed $x10 def $x10
 ; VBITS_GE_2048-NEXT:    // kill: def $w12 killed $w12 killed $x12 def $x12
-; VBITS_GE_2048-NEXT:    stp x10, x13, [sp, #112]
-; VBITS_GE_2048-NEXT:    sbfx x10, x14, #0, #1
-; VBITS_GE_2048-NEXT:    sbfx x11, x11, #0, #1
-; VBITS_GE_2048-NEXT:    ubfx x13, x9, #10, #22
+; VBITS_GE_2048-NEXT:    stp x9, x11, [sp, #144]
+; VBITS_GE_2048-NEXT:    sbfx x9, x13, #0, #1
+; VBITS_GE_2048-NEXT:    sbfx x10, x10, #0, #1
+; VBITS_GE_2048-NEXT:    ubfx x11, x8, #14, #18
 ; VBITS_GE_2048-NEXT:    sbfx x12, x12, #0, #1
-; VBITS_GE_2048-NEXT:    // kill: def $w13 killed $w13 killed $x13 def $x13
-; VBITS_GE_2048-NEXT:    ubfx x14, x9, #9, #23
-; VBITS_GE_2048-NEXT:    // kill: def $w14 killed $w14 killed $x14 def $x14
-; VBITS_GE_2048-NEXT:    stp x11, x10, [sp, #96]
-; VBITS_GE_2048-NEXT:    sbfx x10, x13, #0, #1
-; VBITS_GE_2048-NEXT:    ubfx x11, x9, #8, #24
-; VBITS_GE_2048-NEXT:    ubfx x13, x9, #7, #25
 ; VBITS_GE_2048-NEXT:    // kill: def $w11 killed $w11 killed $x11 def $x11
+; VBITS_GE_2048-NEXT:    ubfx x13, x8, #13, #19
 ; VBITS_GE_2048-NEXT:    // kill: def $w13 killed $w13 killed $x13 def $x13
-; VBITS_GE_2048-NEXT:    stp x10, x12, [sp, #80]
-; VBITS_GE_2048-NEXT:    sbfx x10, x14, #0, #1
+; VBITS_GE_2048-NEXT:    stp x10, x9, [sp, #128]
+; VBITS_GE_2048-NEXT:    sbfx x9, x11, #0, #1
+; VBITS_GE_2048-NEXT:    ubfx x10, x8, #12, #20
+; VBITS_GE_2048-NEXT:    ubfx x11, x8, #11, #21
+; VBITS_GE_2048-NEXT:    // kill: def $w10 killed $w10 killed $x10 def $x10
+; VBITS_GE_2048-NEXT:    // kill: def $w11 killed $w11 killed $x11 def $x11
+; VBITS_GE_2048-NEXT:    stp x9, x12, [sp, #112]
+; VBITS_GE_2048-NEXT:    sbfx x9, x13, #0, #1
+; VBITS_GE_2048-NEXT:    sbfx x10, x10, #0, #1
+; VBITS_GE_2048-NEXT:    ubfx x12, x8, #10, #22
 ; VBITS_GE_2048-NEXT:    sbfx x11, x11, #0, #1
-; VBITS_GE_2048-NEXT:    ubfx x12, x9, #6, #26
-; VBITS_GE_2048-NEXT:    sbfx x13, x13, #0, #1
 ; VBITS_GE_2048-NEXT:    // kill: def $w12 killed $w12 killed $x12 def $x12
-; VBITS_GE_2048-NEXT:    ubfx x14, x9, #5, #27
-; VBITS_GE_2048-NEXT:    // kill: def $w14 killed $w14 killed $x14 def $x14
-; VBITS_GE_2048-NEXT:    stp x11, x10, [sp, #64]
-; VBITS_GE_2048-NEXT:    sbfx x10, x12, #0, #1
-; VBITS_GE_2048-NEXT:    ubfx x11, x9, #4, #28
-; VBITS_GE_2048-NEXT:    ubfx x12, x9, #3, #29
-; VBITS_GE_2048-NEXT:    // kill: def $w11 killed $w11 killed $x11 def $x11
+; VBITS_GE_2048-NEXT:    ubfx x13, x8, #9, #23
+; VBITS_GE_2048-NEXT:    // kill: def $w13 killed $w13 killed $x13 def $x13
+; VBITS_GE_2048-NEXT:    stp x10, x9, [sp, #96]
+; VBITS_GE_2048-NEXT:    sbfx x9, x12, #0, #1
+; VBITS_GE_2048-NEXT:    ubfx x10, x8, #8, #24
+; VBITS_GE_2048-NEXT:    ubfx x12, x8, #7, #25
+; VBITS_GE_2048-NEXT:    // kill: def $w10 killed $w10 killed $x10 def $x10
 ; VBITS_GE_2048-NEXT:    // kill: def $w12 killed $w12 killed $x12 def $x12
-; VBITS_GE_2048-NEXT:    stp x10, x13, [sp, #48]
-; VBITS_GE_2048-NEXT:    sbfx x10, x14, #0, #1
-; VBITS_GE_2048-NEXT:    sbfx x11, x11, #0, #1
-; VBITS_GE_2048-NEXT:    ubfx x13, x9, #2, #30
-; VBITS_GE_2048-NEXT:    ubfx x14, x9, #1, #31
+; VBITS_GE_2048-NEXT:    stp x9, x11, [sp, #80]
+; VBITS_GE_2048-NEXT:    sbfx x9, x13, #0, #1
+; VBITS_GE_2048-NEXT:    sbfx x10, x10, #0, #1
+; VBITS_GE_2048-NEXT:    ubfx x11, x8, #6, #26
 ; VBITS_GE_2048-NEXT:    sbfx x12, x12, #0, #1
+; VBITS_GE_2048-NEXT:    // kill: def $w11 killed $w11 killed $x11 def $x11
+; VBITS_GE_2048-NEXT:    ubfx x13, x8, #5, #27
 ; VBITS_GE_2048-NEXT:    // kill: def $w13 killed $w13 killed $x13 def $x13
-; VBITS_GE_2048-NEXT:    sbfx x9, x9, #0, #1
-; VBITS_GE_2048-NEXT:    // kill: def $w14 killed $w14 killed $x14 def $x14
-; VBITS_GE_2048-NEXT:    stp x11, x10, [sp, #32]
+; VBITS_GE_2048-NEXT:    stp x10, x9, [sp, #64]
+; VBITS_GE_2048-NEXT:    sbfx x9, x11, #0, #1
+; VBITS_GE_2048-NEXT:    ubfx x10, x8, #4, #28
+; VBITS_GE_2048-NEXT:    ubfx x11, x8, #3, #29
+; VBITS_GE_2048-NEXT:    // kill: def $w10 killed $w10 killed $x10 def $x10
+; VBITS_GE_2048-NEXT:    // kill: def $w11 killed $w11 killed $x11 def $x11
+; VBITS_GE_2048-NEXT:    stp x9, x12, [sp, #48]
+; VBITS_GE_2048-NEXT:    sbfx x9, x13, #0, #1
+; VBITS_GE_2048-NEXT:    sbfx x10, x10, #0, #1
+; VBITS_GE_2048-NEXT:    ubfx x12, x8, #2, #30
+; VBITS_GE_2048-NEXT:    ubfx x13, x8, #1, #31
+; VBITS_GE_2048-NEXT:    sbfx x11, x11, #0, #1
+; VBITS_GE_2048-NEXT:    // kill: def $w12 killed $w12 killed $x12 def $x12
+; VBITS_GE_2048-NEXT:    sbfx x8, x8, #0, #1
+; VBITS_GE_2048-NEXT:    // kill: def $w13 killed $w13 killed $x13 def $x13
+; VBITS_GE_2048-NEXT:    stp x10, x9, [sp, #32]
+; VBITS_GE_2048-NEXT:    sbfx x9, x12, #0, #1
 ; VBITS_GE_2048-NEXT:    sbfx x10, x13, #0, #1
-; VBITS_GE_2048-NEXT:    sbfx x11, x14, #0, #1
-; VBITS_GE_2048-NEXT:    stp x10, x12, [sp, #16]
-; VBITS_GE_2048-NEXT:    stp x9, x11, [sp]
-; VBITS_GE_2048-NEXT:    ld1d { z0.d }, p0/z, [x8]
+; VBITS_GE_2048-NEXT:    stp x9, x11, [sp, #16]
+; VBITS_GE_2048-NEXT:    stp x8, x10, [sp]
+; VBITS_GE_2048-NEXT:    ld1d { z0.d }, p0/z, [sp]
 ; VBITS_GE_2048-NEXT:    ld1d { z1.d }, p0/z, [x0]
 ; VBITS_GE_2048-NEXT:    ld1d { z2.d }, p0/z, [x1]
 ; VBITS_GE_2048-NEXT:    and z0.d, z0.d, #0x1
 ; VBITS_GE_2048-NEXT:    cmpne p1.d, p1/z, z0.d, #0
 ; VBITS_GE_2048-NEXT:    sel z0.d, p1, z1.d, z2.d
 ; VBITS_GE_2048-NEXT:    st1d { z0.d }, p0, [x0]
 ; VBITS_GE_2048-NEXT:    mov sp, x29
 ; VBITS_GE_2048-NEXT:    ldp x29, x30, [sp], #16 // 16-byte Folded Reload

llvm/test/CodeGen/AArch64/sve-fixed-length-int-vselect.ll

 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    stp x29, x30, [sp, #-16]! // 16-byte Folded Spill
 ; CHECK-NEXT:    sub x9, sp, #48
 ; CHECK-NEXT:    mov x29, sp
 ; CHECK-NEXT:    and sp, x9, #0xffffffffffffffe0
 ; CHECK-NEXT:    .cfi_def_cfa w29, 16
 ; CHECK-NEXT:    .cfi_offset w30, -8
 ; CHECK-NEXT:    .cfi_offset w29, -16
-; CHECK-NEXT:    ldr w9, [x2]
-; CHECK-NEXT:    mov x8, sp
+; CHECK-NEXT:    ldr w8, [x2]
 ; CHECK-NEXT:    ptrue p0.b, vl32
 ; CHECK-NEXT:    ptrue p1.b
-; CHECK-NEXT:    asr w10, w9, #31
-; CHECK-NEXT:    sbfx w11, w9, #30, #1
-; CHECK-NEXT:    sbfx w12, w9, #29, #1
-; CHECK-NEXT:    strb w10, [sp, #31]
-; CHECK-NEXT:    sbfx w10, w9, #28, #1
-; CHECK-NEXT:    strb w11, [sp, #30]
-; CHECK-NEXT:    sbfx w11, w9, #27, #1
-; CHECK-NEXT:    strb w12, [sp, #29]
-; CHECK-NEXT:    sbfx w12, w9, #26, #1
-; CHECK-NEXT:    strb w10, [sp, #28]
-; CHECK-NEXT:    sbfx w10, w9, #25, #1
-; CHECK-NEXT:    strb w11, [sp, #27]
-; CHECK-NEXT:    sbfx w11, w9, #24, #1
-; CHECK-NEXT:    strb w12, [sp, #26]
-; CHECK-NEXT:    sbfx w12, w9, #23, #1
-; CHECK-NEXT:    strb w10, [sp, #25]
-; CHECK-NEXT:    sbfx w10, w9, #22, #1
-; CHECK-NEXT:    strb w11, [sp, #24]
-; CHECK-NEXT:    sbfx w11, w9, #21, #1
-; CHECK-NEXT:    strb w12, [sp, #23]
-; CHECK-NEXT:    sbfx w12, w9, #20, #1
-; CHECK-NEXT:    strb w10, [sp, #22]
-; CHECK-NEXT:    sbfx w10, w9, #19, #1
-; CHECK-NEXT:    strb w11, [sp, #21]
-; CHECK-NEXT:    sbfx w11, w9, #18, #1
-; CHECK-NEXT:    strb w12, [sp, #20]
-; CHECK-NEXT:    sbfx w12, w9, #17, #1
-; CHECK-NEXT:    strb w10, [sp, #19]
-; CHECK-NEXT:    sbfx w10, w9, #16, #1
-; CHECK-NEXT:    strb w11, [sp, #18]
-; CHECK-NEXT:    sbfx w11, w9, #15, #1
-; CHECK-NEXT:    strb w12, [sp, #17]
-; CHECK-NEXT:    sbfx w12, w9, #14, #1
-; CHECK-NEXT:    strb w10, [sp, #16]
-; CHECK-NEXT:    sbfx w10, w9, #13, #1
-; CHECK-NEXT:    strb w11, [sp, #15]
-; CHECK-NEXT:    sbfx w11, w9, #12, #1
-; CHECK-NEXT:    strb w12, [sp, #14]
-; CHECK-NEXT:    sbfx w12, w9, #11, #1
-; CHECK-NEXT:    strb w10, [sp, #13]
-; CHECK-NEXT:    sbfx w10, w9, #10, #1
-; CHECK-NEXT:    strb w11, [sp, #12]
-; CHECK-NEXT:    sbfx w11, w9, #9, #1
-; CHECK-NEXT:    strb w12, [sp, #11]
-; CHECK-NEXT:    sbfx w12, w9, #8, #1
-; CHECK-NEXT:    strb w10, [sp, #10]
-; CHECK-NEXT:    sbfx w10, w9, #7, #1
-; CHECK-NEXT:    strb w11, [sp, #9]
-; CHECK-NEXT:    sbfx w11, w9, #6, #1
-; CHECK-NEXT:    strb w12, [sp, #8]
-; CHECK-NEXT:    sbfx w12, w9, #5, #1
-; CHECK-NEXT:    strb w10, [sp, #7]
-; CHECK-NEXT:    sbfx w10, w9, #4, #1
-; CHECK-NEXT:    strb w11, [sp, #6]
-; CHECK-NEXT:    sbfx w11, w9, #3, #1
-; CHECK-NEXT:    strb w12, [sp, #5]
-; CHECK-NEXT:    sbfx w12, w9, #2, #1
-; CHECK-NEXT:    strb w10, [sp, #4]
-; CHECK-NEXT:    sbfx w10, w9, #1, #1
-; CHECK-NEXT:    sbfx w9, w9, #0, #1
-; CHECK-NEXT:    strb w11, [sp, #3]
-; CHECK-NEXT:    strb w12, [sp, #2]
-; CHECK-NEXT:    strb w10, [sp, #1]
-; CHECK-NEXT:    strb w9, [sp]
-; CHECK-NEXT:    ld1b { z0.b }, p0/z, [x8]
+; CHECK-NEXT:    asr w9, w8, #31
+; CHECK-NEXT:    sbfx w10, w8, #30, #1
+; CHECK-NEXT:    sbfx w11, w8, #29, #1
+; CHECK-NEXT:    strb w9, [sp, #31]
+; CHECK-NEXT:    sbfx w9, w8, #28, #1
+; CHECK-NEXT:    strb w10, [sp, #30]
+; CHECK-NEXT:    sbfx w10, w8, #27, #1
+; CHECK-NEXT:    strb w11, [sp, #29]
+; CHECK-NEXT:    sbfx w11, w8, #26, #1
+; CHECK-NEXT:    strb w9, [sp, #28]
+; CHECK-NEXT:    sbfx w9, w8, #25, #1
+; CHECK-NEXT:    strb w10, [sp, #27]
+; CHECK-NEXT:    sbfx w10, w8, #24, #1
+; CHECK-NEXT:    strb w11, [sp, #26]
+; CHECK-NEXT:    sbfx w11, w8, #23, #1
+; CHECK-NEXT:    strb w9, [sp, #25]
+; CHECK-NEXT:    sbfx w9, w8, #22, #1
+; CHECK-NEXT:    strb w10, [sp, #24]
+; CHECK-NEXT:    sbfx w10, w8, #21, #1
+; CHECK-NEXT:    strb w11, [sp, #23]
+; CHECK-NEXT:    sbfx w11, w8, #20, #1
+; CHECK-NEXT:    strb w9, [sp, #22]
+; CHECK-NEXT:    sbfx w9, w8, #19, #1
+; CHECK-NEXT:    strb w10, [sp, #21]
+; CHECK-NEXT:    sbfx w10, w8, #18, #1
+; CHECK-NEXT:    strb w11, [sp, #20]
+; CHECK-NEXT:    sbfx w11, w8, #17, #1
+; CHECK-NEXT:    strb w9, [sp, #19]
+; CHECK-NEXT:    sbfx w9, w8, #16, #1
+; CHECK-NEXT:    strb w10, [sp, #18]
+; CHECK-NEXT:    sbfx w10, w8, #15, #1
+; CHECK-NEXT:    strb w11, [sp, #17]
+; CHECK-NEXT:    sbfx w11, w8, #14, #1
+; CHECK-NEXT:    strb w9, [sp, #16]
+; CHECK-NEXT:    sbfx w9, w8, #13, #1
+; CHECK-NEXT:    strb w10, [sp, #15]
+; CHECK-NEXT:    sbfx w10, w8, #12, #1
+; CHECK-NEXT:    strb w11, [sp, #14]
+; CHECK-NEXT:    sbfx w11, w8, #11, #1
+; CHECK-NEXT:    strb w9, [sp, #13]
+; CHECK-NEXT:    sbfx w9, w8, #10, #1
+; CHECK-NEXT:    strb w10, [sp, #12]
+; CHECK-NEXT:    sbfx w10, w8, #9, #1
+; CHECK-NEXT:    strb w11, [sp, #11]
+; CHECK-NEXT:    sbfx w11, w8, #8, #1
+; CHECK-NEXT:    strb w9, [sp, #10]
+; CHECK-NEXT:    sbfx w9, w8, #7, #1
+; CHECK-NEXT:    strb w10, [sp, #9]
+; CHECK-NEXT:    sbfx w10, w8, #6, #1
+; CHECK-NEXT:    strb w11, [sp, #8]
+; CHECK-NEXT:    sbfx w11, w8, #5, #1
+; CHECK-NEXT:    strb w9, [sp, #7]
+; CHECK-NEXT:    sbfx w9, w8, #4, #1
+; CHECK-NEXT:    strb w10, [sp, #6]
+; CHECK-NEXT:    sbfx w10, w8, #3, #1
+; CHECK-NEXT:    strb w11, [sp, #5]
+; CHECK-NEXT:    sbfx w11, w8, #2, #1
+; CHECK-NEXT:    strb w9, [sp, #4]
+; CHECK-NEXT:    sbfx w9, w8, #1, #1
+; CHECK-NEXT:    sbfx w8, w8, #0, #1
+; CHECK-NEXT:    strb w10, [sp, #3]
+; CHECK-NEXT:    strb w11, [sp, #2]
+; CHECK-NEXT:    strb w9, [sp, #1]
+; CHECK-NEXT:    strb w8, [sp]
+; CHECK-NEXT:    ld1b { z0.b }, p0/z, [sp]
 ; CHECK-NEXT:    ld1b { z1.b }, p0/z, [x0]
 ; CHECK-NEXT:    ld1b { z2.b }, p0/z, [x1]
 ; CHECK-NEXT:    and z0.b, z0.b, #0x1
 ; CHECK-NEXT:    cmpne p1.b, p1/z, z0.b, #0
 ; CHECK-NEXT:    sel z0.b, p1, z1.b, z2.b
 ; CHECK-NEXT:    st1b { z0.b }, p0, [x0]
 ; CHECK-NEXT:    mov sp, x29
 ; CHECK-NEXT:    ldp x29, x30, [sp], #16 // 16-byte Folded Reload

 ; VBITS_GE_512:       // %bb.0:
 ; VBITS_GE_512-NEXT:    stp x29, x30, [sp, #-16]! // 16-byte Folded Spill
 ; VBITS_GE_512-NEXT:    sub x9, sp, #112
 ; VBITS_GE_512-NEXT:    mov x29, sp
 ; VBITS_GE_512-NEXT:    and sp, x9, #0xffffffffffffffc0
 ; VBITS_GE_512-NEXT:    .cfi_def_cfa w29, 16
 ; VBITS_GE_512-NEXT:    .cfi_offset w30, -8
 ; VBITS_GE_512-NEXT:    .cfi_offset w29, -16
-; VBITS_GE_512-NEXT:    ldr x9, [x2]
-; VBITS_GE_512-NEXT:    mov x8, sp
+; VBITS_GE_512-NEXT:    ldr x8, [x2]
 ; VBITS_GE_512-NEXT:    ptrue p0.b, vl64
 ; VBITS_GE_512-NEXT:    ptrue p1.b
-; VBITS_GE_512-NEXT:    asr x10, x9, #63
-; VBITS_GE_512-NEXT:    sbfx x11, x9, #62, #1
-; VBITS_GE_512-NEXT:    sbfx x12, x9, #61, #1
-; VBITS_GE_512-NEXT:    strb w10, [sp, #63]
-; VBITS_GE_512-NEXT:    sbfx x10, x9, #60, #1
-; VBITS_GE_512-NEXT:    strb w11, [sp, #62]
-; VBITS_GE_512-NEXT:    sbfx x11, x9, #59, #1
-; VBITS_GE_512-NEXT:    strb w12, [sp, #61]
-; VBITS_GE_512-NEXT:    sbfx x12, x9, #58, #1
-; VBITS_GE_512-NEXT:    strb w10, [sp, #60]
-; VBITS_GE_512-NEXT:    sbfx x10, x9, #57, #1
-; VBITS_GE_512-NEXT:    strb w11, [sp, #59]
-; VBITS_GE_512-NEXT:    sbfx x11, x9, #56, #1
-; VBITS_GE_512-NEXT:    strb w12, [sp, #58]
-; VBITS_GE_512-NEXT:    sbfx x12, x9, #55, #1
-; VBITS_GE_512-NEXT:    strb w10, [sp, #57]
-; VBITS_GE_512-NEXT:    sbfx x10, x9, #54, #1
-; VBITS_GE_512-NEXT:    strb w11, [sp, #56]
-; VBITS_GE_512-NEXT:    sbfx x11, x9, #53, #1
-; VBITS_GE_512-NEXT:    strb w12, [sp, #55]
-; VBITS_GE_512-NEXT:    sbfx x12, x9, #52, #1
-; VBITS_GE_512-NEXT:    strb w10, [sp, #54]
-; VBITS_GE_512-NEXT:    sbfx x10, x9, #51, #1
-; VBITS_GE_512-NEXT:    strb w11, [sp, #53]
-; VBITS_GE_512-NEXT:    sbfx x11, x9, #50, #1
-; VBITS_GE_512-NEXT:    strb w12, [sp, #52]
-; VBITS_GE_512-NEXT:    sbfx x12, x9, #49, #1
-; VBITS_GE_512-NEXT:    strb w10, [sp, #51]
-; VBITS_GE_512-NEXT:    sbfx x10, x9, #48, #1
-; VBITS_GE_512-NEXT:    strb w11, [sp, #50]
-; VBITS_GE_512-NEXT:    sbfx x11, x9, #47, #1
-; VBITS_GE_512-NEXT:    strb w12, [sp, #49]
-; VBITS_GE_512-NEXT:    sbfx x12, x9, #46, #1
-; VBITS_GE_512-NEXT:    strb w10, [sp, #48]
-; VBITS_GE_512-NEXT:    sbfx x10, x9, #45, #1
-; VBITS_GE_512-NEXT:    strb w11, [sp, #47]
-; VBITS_GE_512-NEXT:    sbfx x11, x9, #44, #1
-; VBITS_GE_512-NEXT:    strb w12, [sp, #46]
-; VBITS_GE_512-NEXT:    sbfx x12, x9, #43, #1
-; VBITS_GE_512-NEXT:    strb w10, [sp, #45]
-; VBITS_GE_512-NEXT:    sbfx x10, x9, #42, #1
-; VBITS_GE_512-NEXT:    strb w11, [sp, #44]
-; VBITS_GE_512-NEXT:    sbfx x11, x9, #41, #1
-; VBITS_GE_512-NEXT:    strb w12, [sp, #43]
-; VBITS_GE_512-NEXT:    sbfx x12, x9, #40, #1
-; VBITS_GE_512-NEXT:    strb w10, [sp, #42]
-; VBITS_GE_512-NEXT:    sbfx x10, x9, #39, #1
-; VBITS_GE_512-NEXT:    strb w11, [sp, #41]
-; VBITS_GE_512-NEXT:    sbfx x11, x9, #38, #1
-; VBITS_GE_512-NEXT:    strb w12, [sp, #40]
-; VBITS_GE_512-NEXT:    sbfx x12, x9, #37, #1
-; VBITS_GE_512-NEXT:    strb w10, [sp, #39]
-; VBITS_GE_512-NEXT:    sbfx x10, x9, #36, #1
-; VBITS_GE_512-NEXT:    strb w11, [sp, #38]
-; VBITS_GE_512-NEXT:    sbfx x11, x9, #35, #1
-; VBITS_GE_512-NEXT:    strb w12, [sp, #37]
-; VBITS_GE_512-NEXT:    sbfx x12, x9, #34, #1
-; VBITS_GE_512-NEXT:    strb w10, [sp, #36]
-; VBITS_GE_512-NEXT:    sbfx x10, x9, #33, #1
-; VBITS_GE_512-NEXT:    strb w11, [sp, #35]
-; VBITS_GE_512-NEXT:    sbfx x11, x9, #32, #1
-; VBITS_GE_512-NEXT:    strb w12, [sp, #34]
-; VBITS_GE_512-NEXT:    asr w12, w9, #31
-; VBITS_GE_512-NEXT:    strb w10, [sp, #33]
-; VBITS_GE_512-NEXT:    sbfx w10, w9, #30, #1
-; VBITS_GE_512-NEXT:    strb w11, [sp, #32]
-; VBITS_GE_512-NEXT:    sbfx w11, w9, #29, #1
-; VBITS_GE_512-NEXT:    strb w12, [sp, #31]
-; VBITS_GE_512-NEXT:    sbfx w12, w9, #28, #1
-; VBITS_GE_512-NEXT:    strb w10, [sp, #30]
-; VBITS_GE_512-NEXT:    sbfx w10, w9, #27, #1
-; VBITS_GE_512-NEXT:    strb w11, [sp, #29]
-; VBITS_GE_512-NEXT:    sbfx w11, w9, #26, #1
-; VBITS_GE_512-NEXT:    strb w12, [sp, #28]
-; VBITS_GE_512-NEXT:    sbfx w12, w9, #25, #1
-; VBITS_GE_512-NEXT:    strb w10, [sp, #27]
-; VBITS_GE_512-NEXT:    sbfx w10, w9, #24, #1
-; VBITS_GE_512-NEXT:    strb w11, [sp, #26]
-; VBITS_GE_512-NEXT:    sbfx w11, w9, #23, #1
-; VBITS_GE_512-NEXT:    strb w12, [sp, #25]
-; VBITS_GE_512-NEXT:    sbfx w12, w9, #22, #1
-; VBITS_GE_512-NEXT:    strb w10, [sp, #24]
-; VBITS_GE_512-NEXT:    sbfx w10, w9, #21, #1
-; VBITS_GE_512-NEXT:    strb w11, [sp, #23]
-; VBITS_GE_512-NEXT:    sbfx w11, w9, #20, #1
-; VBITS_GE_512-NEXT:    strb w12, [sp, #22]
-; VBITS_GE_512-NEXT:    sbfx w12, w9, #19, #1
-; VBITS_GE_512-NEXT:    strb w10, [sp, #21]
-; VBITS_GE_512-NEXT:    sbfx w10, w9, #18, #1
-; VBITS_GE_512-NEXT:    strb w11, [sp, #20]
-; VBITS_GE_512-NEXT:    sbfx w11, w9, #17, #1
-; VBITS_GE_512-NEXT:    strb w12, [sp, #19]
-; VBITS_GE_512-NEXT:    sbfx w12, w9, #16, #1
-; VBITS_GE_512-NEXT:    strb w10, [sp, #18]
-; VBITS_GE_512-NEXT:    sbfx w10, w9, #15, #1
-; VBITS_GE_512-NEXT:    strb w11, [sp, #17]
-; VBITS_GE_512-NEXT:    sbfx w11, w9, #14, #1
-; VBITS_GE_512-NEXT:    strb w12, [sp, #16]
-; VBITS_GE_512-NEXT:    sbfx w12, w9, #13, #1
-; VBITS_GE_512-NEXT:    strb w10, [sp, #15]
-; VBITS_GE_512-NEXT:    sbfx w10, w9, #12, #1
-; VBITS_GE_512-NEXT:    strb w11, [sp, #14]
-; VBITS_GE_512-NEXT:    sbfx w11, w9, #11, #1
-; VBITS_GE_512-NEXT:    strb w12, [sp, #13]
-; VBITS_GE_512-NEXT:    sbfx w12, w9, #10, #1
-; VBITS_GE_512-NEXT:    strb w10, [sp, #12]
-; VBITS_GE_512-NEXT:    sbfx w10, w9, #9, #1
-; VBITS_GE_512-NEXT:    strb w11, [sp, #11]
-; VBITS_GE_512-NEXT:    sbfx w11, w9, #8, #1
-; VBITS_GE_512-NEXT:    strb w12, [sp, #10]
-; VBITS_GE_512-NEXT:    sbfx w12, w9, #7, #1
-; VBITS_GE_512-NEXT:    strb w10, [sp, #9]
-; VBITS_GE_512-NEXT:    sbfx w10, w9, #6, #1
-; VBITS_GE_512-NEXT:    strb w11, [sp, #8]
-; VBITS_GE_512-NEXT:    sbfx w11, w9, #5, #1
-; VBITS_GE_512-NEXT:    strb w12, [sp, #7]
-; VBITS_GE_512-NEXT:    sbfx w12, w9, #4, #1
-; VBITS_GE_512-NEXT:    strb w10, [sp, #6]
-; VBITS_GE_512-NEXT:    sbfx w10, w9, #3, #1
-; VBITS_GE_512-NEXT:    strb w11, [sp, #5]
-; VBITS_GE_512-NEXT:    sbfx w11, w9, #2, #1
-; VBITS_GE_512-NEXT:    strb w12, [sp, #4]
-; VBITS_GE_512-NEXT:    sbfx w12, w9, #1, #1
-; VBITS_GE_512-NEXT:    sbfx w9, w9, #0, #1
-; VBITS_GE_512-NEXT:    strb w10, [sp, #3]
-; VBITS_GE_512-NEXT:    strb w11, [sp, #2]
-; VBITS_GE_512-NEXT:    strb w12, [sp, #1]
-; VBITS_GE_512-NEXT:    strb w9, [sp]
-; VBITS_GE_512-NEXT:    ld1b { z0.b }, p0/z, [x8]
+; VBITS_GE_512-NEXT:    asr x9, x8, #63
+; VBITS_GE_512-NEXT:    sbfx x10, x8, #62, #1
+; VBITS_GE_512-NEXT:    sbfx x11, x8, #61, #1
+; VBITS_GE_512-NEXT:    strb w9, [sp, #63]
+; VBITS_GE_512-NEXT:    sbfx x9, x8, #60, #1
+; VBITS_GE_512-NEXT:    strb w10, [sp, #62]
+; VBITS_GE_512-NEXT:    sbfx x10, x8, #59, #1
+; VBITS_GE_512-NEXT:    strb w11, [sp, #61]
+; VBITS_GE_512-NEXT:    sbfx x11, x8, #58, #1
+; VBITS_GE_512-NEXT:    strb w9, [sp, #60]
+; VBITS_GE_512-NEXT:    sbfx x9, x8, #57, #1
+; VBITS_GE_512-NEXT:    strb w10, [sp, #59]
+; VBITS_GE_512-NEXT:    sbfx x10, x8, #56, #1
+; VBITS_GE_512-NEXT:    strb w11, [sp, #58]
+; VBITS_GE_512-NEXT:    sbfx x11, x8, #55, #1
+; VBITS_GE_512-NEXT:    strb w9, [sp, #57]
+; VBITS_GE_512-NEXT:    sbfx x9, x8, #54, #1
+; VBITS_GE_512-NEXT:    strb w10, [sp, #56]
+; VBITS_GE_512-NEXT:    sbfx x10, x8, #53, #1
+; VBITS_GE_512-NEXT:    strb w11, [sp, #55]
+; VBITS_GE_512-NEXT:    sbfx x11, x8, #52, #1
+; VBITS_GE_512-NEXT:    strb w9, [sp, #54]
+; VBITS_GE_512-NEXT:    sbfx x9, x8, #51, #1
+; VBITS_GE_512-NEXT:    strb w10, [sp, #53]
+; VBITS_GE_512-NEXT:    sbfx x10, x8, #50, #1
+; VBITS_GE_512-NEXT:    strb w11, [sp, #52]
+; VBITS_GE_512-NEXT:    sbfx x11, x8, #49, #1
+; VBITS_GE_512-NEXT:    strb w9, [sp, #51]
+; VBITS_GE_512-NEXT:    sbfx x9, x8, #48, #1
+; VBITS_GE_512-NEXT:    strb w10, [sp, #50]
+; VBITS_GE_512-NEXT:    sbfx x10, x8, #47, #1
+; VBITS_GE_512-NEXT:    strb w11, [sp, #49]
+; VBITS_GE_512-NEXT:    sbfx x11, x8, #46, #1
+; VBITS_GE_512-NEXT:    strb w9, [sp, #48]
+; VBITS_GE_512-NEXT:    sbfx x9, x8, #45, #1
+; VBITS_GE_512-NEXT:    strb w10, [sp, #47]
+; VBITS_GE_512-NEXT:    sbfx x10, x8, #44, #1
+; VBITS_GE_512-NEXT:    strb w11, [sp, #46]
+; VBITS_GE_512-NEXT:    sbfx x11, x8, #43, #1
+; VBITS_GE_512-NEXT:    strb w9, [sp, #45]
+; VBITS_GE_512-NEXT:    sbfx x9, x8, #42, #1
+; VBITS_GE_512-NEXT:    strb w10, [sp, #44]
+; VBITS_GE_512-NEXT:    sbfx x10, x8, #41, #1
+; VBITS_GE_512-NEXT:    strb w11, [sp, #43]
+; VBITS_GE_512-NEXT:    sbfx x11, x8, #40, #1
+; VBITS_GE_512-NEXT:    strb w9, [sp, #42]
+; VBITS_GE_512-NEXT:    sbfx x9, x8, #39, #1
+; VBITS_GE_512-NEXT:    strb w10, [sp, #41]
+; VBITS_GE_512-NEXT:    sbfx x10, x8, #38, #1
+; VBITS_GE_512-NEXT:    strb w11, [sp, #40]
+; VBITS_GE_512-NEXT:    sbfx x11, x8, #37, #1
+; VBITS_GE_512-NEXT:    strb w9, [sp, #39]
+; VBITS_GE_512-NEXT:    sbfx x9, x8, #36, #1
+; VBITS_GE_512-NEXT:    strb w10, [sp, #38]
+; VBITS_GE_512-NEXT:    sbfx x10, x8, #35, #1
+; VBITS_GE_512-NEXT:    strb w11, [sp, #37]
+; VBITS_GE_512-NEXT:    sbfx x11, x8, #34, #1
+; VBITS_GE_512-NEXT:    strb w9, [sp, #36]
+; VBITS_GE_512-NEXT:    sbfx x9, x8, #33, #1
+; VBITS_GE_512-NEXT:    strb w10, [sp, #35]
+; VBITS_GE_512-NEXT:    sbfx x10, x8, #32, #1
+; VBITS_GE_512-NEXT:    strb w11, [sp, #34]
+; VBITS_GE_512-NEXT:    asr w11, w8, #31
+; VBITS_GE_512-NEXT:    strb w9, [sp, #33]
+; VBITS_GE_512-NEXT:    sbfx w9, w8, #30, #1
+; VBITS_GE_512-NEXT:    strb w10, [sp, #32]
+; VBITS_GE_512-NEXT:    sbfx w10, w8, #29, #1
+; VBITS_GE_512-NEXT:    strb w11, [sp, #31]
+; VBITS_GE_512-NEXT:    sbfx w11, w8, #28, #1
+; VBITS_GE_512-NEXT:    strb w9, [sp, #30]
+; VBITS_GE_512-NEXT:    sbfx w9, w8, #27, #1
+; VBITS_GE_512-NEXT:    strb w10, [sp, #29]
+; VBITS_GE_512-NEXT:    sbfx w10, w8, #26, #1
+; VBITS_GE_512-NEXT:    strb w11, [sp, #28]
+; VBITS_GE_512-NEXT:    sbfx w11, w8, #25, #1
+; VBITS_GE_512-NEXT:    strb w9, [sp, #27]
+; VBITS_GE_512-NEXT:    sbfx w9, w8, #24, #1
+; VBITS_GE_512-NEXT:    strb w10, [sp, #26]
+; VBITS_GE_512-NEXT:    sbfx w10, w8, #23, #1
+; VBITS_GE_512-NEXT:    strb w11, [sp, #25]
+; VBITS_GE_512-NEXT:    sbfx w11, w8, #22, #1
+; VBITS_GE_512-NEXT:    strb w9, [sp, #24]
+; VBITS_GE_512-NEXT:    sbfx w9, w8, #21, #1
+; VBITS_GE_512-NEXT:    strb w10, [sp, #23]
+; VBITS_GE_512-NEXT:    sbfx w10, w8, #20, #1
+; VBITS_GE_512-NEXT:    strb w11, [sp, #22]
+; VBITS_GE_512-NEXT:    sbfx w11, w8, #19, #1
+; VBITS_GE_512-NEXT:    strb w9, [sp, #21]
+; VBITS_GE_512-NEXT:    sbfx w9, w8, #18, #1
+; VBITS_GE_512-NEXT:    strb w10, [sp, #20]
+; VBITS_GE_512-NEXT:    sbfx w10, w8, #17, #1
+; VBITS_GE_512-NEXT:    strb w11, [sp, #19]
+; VBITS_GE_512-NEXT:    sbfx w11, w8, #16, #1
+; VBITS_GE_512-NEXT:    strb w9, [sp, #18]
+; VBITS_GE_512-NEXT:    sbfx w9, w8, #15, #1
+; VBITS_GE_512-NEXT:    strb w10, [sp, #17]
+; VBITS_GE_512-NEXT:    sbfx w10, w8, #14, #1
+; VBITS_GE_512-NEXT:    strb w11, [sp, #16]
+; VBITS_GE_512-NEXT:    sbfx w11, w8, #13, #1
+; VBITS_GE_512-NEXT:    strb w9, [sp, #15]
+; VBITS_GE_512-NEXT:    sbfx w9, w8, #12, #1
+; VBITS_GE_512-NEXT:    strb w10, [sp, #14]
+; VBITS_GE_512-NEXT:    sbfx w10, w8, #11, #1
+; VBITS_GE_512-NEXT:    strb w11, [sp, #13]
+; VBITS_GE_512-NEXT:    sbfx w11, w8, #10, #1
+; VBITS_GE_512-NEXT:    strb w9, [sp, #12]
+; VBITS_GE_512-NEXT:    sbfx w9, w8, #9, #1
+; VBITS_GE_512-NEXT:    strb w10, [sp, #11]
+; VBITS_GE_512-NEXT:    sbfx w10, w8, #8, #1
+; VBITS_GE_512-NEXT:    strb w11, [sp, #10]
+; VBITS_GE_512-NEXT:    sbfx w11, w8, #7, #1
+; VBITS_GE_512-NEXT:    strb w9, [sp, #9]
+; VBITS_GE_512-NEXT:    sbfx w9, w8, #6, #1
+; VBITS_GE_512-NEXT:    strb w10, [sp, #8]
+; VBITS_GE_512-NEXT:    sbfx w10, w8, #5, #1
+; VBITS_GE_512-NEXT:    strb w11, [sp, #7]
+; VBITS_GE_512-NEXT:    sbfx w11, w8, #4, #1
+; VBITS_GE_512-NEXT:    strb w9, [sp, #6]
+; VBITS_GE_512-NEXT:    sbfx w9, w8, #3, #1
+; VBITS_GE_512-NEXT:    strb w10, [sp, #5]
+; VBITS_GE_512-NEXT:    sbfx w10, w8, #2, #1
+; VBITS_GE_512-NEXT:    strb w11, [sp, #4]
+; VBITS_GE_512-NEXT:    sbfx w11, w8, #1, #1
+; VBITS_GE_512-NEXT:    sbfx w8, w8, #0, #1
+; VBITS_GE_512-NEXT:    strb w9, [sp, #3]
+; VBITS_GE_512-NEXT:    strb w10, [sp, #2]
+; VBITS_GE_512-NEXT:    strb w11, [sp, #1]
+; VBITS_GE_512-NEXT:    strb w8, [sp]
+; VBITS_GE_512-NEXT:    ld1b { z0.b }, p0/z, [sp]
 ; VBITS_GE_512-NEXT:    ld1b { z1.b }, p0/z, [x0]
 ; VBITS_GE_512-NEXT:    ld1b { z2.b }, p0/z, [x1]
 ; VBITS_GE_512-NEXT:    and z0.b, z0.b, #0x1
 ; VBITS_GE_512-NEXT:    cmpne p1.b, p1/z, z0.b, #0
 ; VBITS_GE_512-NEXT:    sel z0.b, p1, z1.b, z2.b
 ; VBITS_GE_512-NEXT:    st1b { z0.b }, p0, [x0]
 ; VBITS_GE_512-NEXT:    mov sp, x29
 ; VBITS_GE_512-NEXT:    ldp x29, x30, [sp], #16 // 16-byte Folded Reload

 ; VBITS_GE_1024:       // %bb.0:
 ; VBITS_GE_1024-NEXT:    stp x29, x30, [sp, #-16]! // 16-byte Folded Spill
 ; VBITS_GE_1024-NEXT:    sub x9, sp, #240
 ; VBITS_GE_1024-NEXT:    mov x29, sp
 ; VBITS_GE_1024-NEXT:    and sp, x9, #0xffffffffffffff80
 ; VBITS_GE_1024-NEXT:    .cfi_def_cfa w29, 16
 ; VBITS_GE_1024-NEXT:    .cfi_offset w30, -8
 ; VBITS_GE_1024-NEXT:    .cfi_offset w29, -16
-; VBITS_GE_1024-NEXT:    ldr x9, [x2, #8]
-; VBITS_GE_1024-NEXT:    mov x8, sp
+; VBITS_GE_1024-NEXT:    ldr x8, [x2, #8]
 ; VBITS_GE_1024-NEXT:    ptrue p0.b, vl128
 ; VBITS_GE_1024-NEXT:    ptrue p1.b
-; VBITS_GE_1024-NEXT:    asr x10, x9, #63
-; VBITS_GE_1024-NEXT:    sbfx x11, x9, #62, #1
-; VBITS_GE_1024-NEXT:    sbfx x12, x9, #61, #1
-; VBITS_GE_1024-NEXT:    strb w10, [sp, #127]
-; VBITS_GE_1024-NEXT:    sbfx x10, x9, #60, #1
-; VBITS_GE_1024-NEXT:    strb w11, [sp, #126]
-; VBITS_GE_1024-NEXT:    sbfx x11, x9, #59, #1
-; VBITS_GE_1024-NEXT:    strb w12, [sp, #125]
-; VBITS_GE_1024-NEXT:    sbfx x12, x9, #58, #1
-; VBITS_GE_1024-NEXT:    strb w10, [sp, #124]
-; VBITS_GE_1024-NEXT:    sbfx x10, x9, #57, #1
-; VBITS_GE_1024-NEXT:    strb w11, [sp, #123]
-; VBITS_GE_1024-NEXT:    sbfx x11, x9, #56, #1
-; VBITS_GE_1024-NEXT:    strb w12, [sp, #122]
-; VBITS_GE_1024-NEXT:    sbfx x12, x9, #55, #1
-; VBITS_GE_1024-NEXT:    strb w10, [sp, #121]
-; VBITS_GE_1024-NEXT:    sbfx x10, x9, #54, #1
-; VBITS_GE_1024-NEXT:    strb w11, [sp, #120]
-; VBITS_GE_1024-NEXT:    sbfx x11, x9, #53, #1
-; VBITS_GE_1024-NEXT:    strb w12, [sp, #119]
-; VBITS_GE_1024-NEXT:    sbfx x12, x9, #52, #1
-; VBITS_GE_1024-NEXT:    strb w10, [sp, #118]
-; VBITS_GE_1024-NEXT:    sbfx x10, x9, #51, #1
-; VBITS_GE_1024-NEXT:    strb w11, [sp, #117]
-; VBITS_GE_1024-NEXT:    sbfx x11, x9, #50, #1
-; VBITS_GE_1024-NEXT:    strb w12, [sp, #116]
-; VBITS_GE_1024-NEXT:    sbfx x12, x9, #49, #1
-; VBITS_GE_1024-NEXT:    strb w10, [sp, #115]
-; VBITS_GE_1024-NEXT:    sbfx x10, x9, #48, #1
-; VBITS_GE_1024-NEXT:    strb w11, [sp, #114]
-; VBITS_GE_1024-NEXT:    sbfx x11, x9, #47, #1
-; VBITS_GE_1024-NEXT:    strb w12, [sp, #113]
-; VBITS_GE_1024-NEXT:    sbfx x12, x9, #46, #1
-; VBITS_GE_1024-NEXT:    strb w10, [sp, #112]
-; VBITS_GE_1024-NEXT:    sbfx x10, x9, #45, #1
-; VBITS_GE_1024-NEXT:    strb w11, [sp, #111]
-; VBITS_GE_1024-NEXT:    sbfx x11, x9, #44, #1
-; VBITS_GE_1024-NEXT:    strb w12, [sp, #110]
-; VBITS_GE_1024-NEXT:    sbfx x12, x9, #43, #1
-; VBITS_GE_1024-NEXT:    strb w10, [sp, #109]
-; VBITS_GE_1024-NEXT:    sbfx x10, x9, #42, #1
-; VBITS_GE_1024-NEXT:    strb w11, [sp, #108]
-; VBITS_GE_1024-NEXT:    sbfx x11, x9, #41, #1
-; VBITS_GE_1024-NEXT:    strb w12, [sp, #107]
-; VBITS_GE_1024-NEXT:    sbfx x12, x9, #40, #1
-; VBITS_GE_1024-NEXT:    strb w10, [sp, #106]
-; VBITS_GE_1024-NEXT:    sbfx x10, x9, #39, #1
-; VBITS_GE_1024-NEXT:    strb w11, [sp, #105]
-; VBITS_GE_1024-NEXT:    sbfx x11, x9, #38, #1
-; VBITS_GE_1024-NEXT:    strb w12, [sp, #104]
-; VBITS_GE_1024-NEXT:    sbfx x12, x9, #37, #1
-; VBITS_GE_1024-NEXT:    strb w10, [sp, #103]
-; VBITS_GE_1024-NEXT:    sbfx x10, x9, #36, #1
-; VBITS_GE_1024-NEXT:    strb w11, [sp, #102]
-; VBITS_GE_1024-NEXT:    sbfx x11, x9, #35, #1
-; VBITS_GE_1024-NEXT:    strb w12, [sp, #101]
-; VBITS_GE_1024-NEXT:    sbfx x12, x9, #34, #1
-; VBITS_GE_1024-NEXT:    strb w10, [sp, #100]
-; VBITS_GE_1024-NEXT:    sbfx x10, x9, #33, #1
-; VBITS_GE_1024-NEXT:    strb w11, [sp, #99]
-; VBITS_GE_1024-NEXT:    sbfx x11, x9, #32, #1
-; VBITS_GE_1024-NEXT:    strb w12, [sp, #98]
-; VBITS_GE_1024-NEXT:    asr w12, w9, #31
-; VBITS_GE_1024-NEXT:    strb w10, [sp, #97]
-; VBITS_GE_1024-NEXT:    sbfx w10, w9, #30, #1
-; VBITS_GE_1024-NEXT:    strb w11, [sp, #96]
-; VBITS_GE_1024-NEXT:    sbfx w11, w9, #29, #1
-; VBITS_GE_1024-NEXT:    strb w12, [sp, #95]
-; VBITS_GE_1024-NEXT:    sbfx w12, w9, #28, #1
-; VBITS_GE_1024-NEXT:    strb w10, [sp, #94]
-; VBITS_GE_1024-NEXT:    sbfx w10, w9, #27, #1
-; VBITS_GE_1024-NEXT:    strb w11, [sp, #93]
-; VBITS_GE_1024-NEXT:    sbfx w11, w9, #26, #1
-; VBITS_GE_1024-NEXT:    strb w12, [sp, #92]
-; VBITS_GE_1024-NEXT:    sbfx w12, w9, #25, #1
-; VBITS_GE_1024-NEXT:    strb w10, [sp, #91]
-; VBITS_GE_1024-NEXT:    sbfx w10, w9, #24, #1
-; VBITS_GE_1024-NEXT:    strb w11, [sp, #90]
-; VBITS_GE_1024-NEXT:    sbfx w11, w9, #23, #1
-; VBITS_GE_1024-NEXT:    strb w12, [sp, #89]
-; VBITS_GE_1024-NEXT:    sbfx w12, w9, #22, #1
-; VBITS_GE_1024-NEXT:    strb w10, [sp, #88]
-; VBITS_GE_1024-NEXT:    sbfx w10, w9, #21, #1
-; VBITS_GE_1024-NEXT:    strb w11, [sp, #87]
-; VBITS_GE_1024-NEXT:    sbfx w11, w9, #20, #1
-; VBITS_GE_1024-NEXT:    strb w12, [sp, #86]
-; VBITS_GE_1024-NEXT:    sbfx w12, w9, #19, #1
-; VBITS_GE_1024-NEXT:    strb w10, [sp, #85]
-; VBITS_GE_1024-NEXT:    sbfx w10, w9, #18, #1
-; VBITS_GE_1024-NEXT:    strb w11, [sp, #84]
-; VBITS_GE_1024-NEXT:    sbfx w11, w9, #17, #1
-; VBITS_GE_1024-NEXT:    strb w12, [sp, #83]
-; VBITS_GE_1024-NEXT:    sbfx w12, w9, #16, #1
-; VBITS_GE_1024-NEXT:    strb w10, [sp, #82]
-; VBITS_GE_1024-NEXT:    sbfx w10, w9, #15, #1
-; VBITS_GE_1024-NEXT:    strb w11, [sp, #81]
-; VBITS_GE_1024-NEXT:    sbfx w11, w9, #14, #1
-; VBITS_GE_1024-NEXT:    strb w12, [sp, #80]
-; VBITS_GE_1024-NEXT:    sbfx w12, w9, #13, #1
-; VBITS_GE_1024-NEXT:    strb w10, [sp, #79]
-; VBITS_GE_1024-NEXT:    sbfx w10, w9, #12, #1
-; VBITS_GE_1024-NEXT:    strb w11, [sp, #78]
-; VBITS_GE_1024-NEXT:    sbfx w11, w9, #11, #1
-; VBITS_GE_1024-NEXT:    strb w12, [sp, #77]
-; VBITS_GE_1024-NEXT:    sbfx w12, w9, #10, #1
-; VBITS_GE_1024-NEXT:    strb w10, [sp, #76]
-; VBITS_GE_1024-NEXT:    sbfx w10, w9, #9, #1
-; VBITS_GE_1024-NEXT:    strb w11, [sp, #75]
-; VBITS_GE_1024-NEXT:    sbfx w11, w9, #8, #1
-; VBITS_GE_1024-NEXT:    strb w12, [sp, #74]
-; VBITS_GE_1024-NEXT:    sbfx w12, w9, #7, #1
-; VBITS_GE_1024-NEXT:    strb w10, [sp, #73]
-; VBITS_GE_1024-NEXT:    sbfx w10, w9, #6, #1
-; VBITS_GE_1024-NEXT:    strb w11, [sp, #72]
-; VBITS_GE_1024-NEXT:    sbfx w11, w9, #5, #1
-; VBITS_GE_1024-NEXT:    strb w12, [sp, #71]
-; VBITS_GE_1024-NEXT:    sbfx w12, w9, #4, #1
-; VBITS_GE_1024-NEXT:    strb w10, [sp, #70]
-; VBITS_GE_1024-NEXT:    sbfx w10, w9, #3, #1
-; VBITS_GE_1024-NEXT:    strb w11, [sp, #69]
-; VBITS_GE_1024-NEXT:    sbfx w11, w9, #2, #1
-; VBITS_GE_1024-NEXT:    strb w12, [sp, #68]
-; VBITS_GE_1024-NEXT:    sbfx w12, w9, #1, #1
-; VBITS_GE_1024-NEXT:    sbfx w9, w9, #0, #1
-; VBITS_GE_1024-NEXT:    strb w10, [sp, #67]
-; VBITS_GE_1024-NEXT:    strb w11, [sp, #66]
-; VBITS_GE_1024-NEXT:    strb w12, [sp, #65]
-; VBITS_GE_1024-NEXT:    strb w9, [sp, #64]
-; VBITS_GE_1024-NEXT:    ldr x9, [x2]
-; VBITS_GE_1024-NEXT:    asr x10, x9, #63
-; VBITS_GE_1024-NEXT:    sbfx x11, x9, #62, #1
-; VBITS_GE_1024-NEXT:    sbfx x12, x9, #61, #1
-; VBITS_GE_1024-NEXT:    strb w10, [sp, #63]
-; VBITS_GE_1024-NEXT:    sbfx x10, x9, #60, #1
-; VBITS_GE_1024-NEXT:    strb w11, [sp, #62]
-; VBITS_GE_1024-NEXT:    sbfx x11, x9, #59, #1
-; VBITS_GE_1024-NEXT:    strb w12, [sp, #61]
-; VBITS_GE_1024-NEXT:    sbfx x12, x9, #58, #1
-; VBITS_GE_1024-NEXT:    strb w10, [sp, #60]
-; VBITS_GE_1024-NEXT:    sbfx x10, x9, #57, #1
-; VBITS_GE_1024-NEXT:    strb w11, [sp, #59]
-; VBITS_GE_1024-NEXT:    sbfx x11, x9, #56, #1
-; VBITS_GE_1024-NEXT:    strb w12, [sp, #58]
-; VBITS_GE_1024-NEXT:    sbfx x12, x9, #55, #1
-; VBITS_GE_1024-NEXT:    strb w10, [sp, #57]
-; VBITS_GE_1024-NEXT:    sbfx x10, x9, #54, #1
-; VBITS_GE_1024-NEXT:    strb w11, [sp, #56]
-; VBITS_GE_1024-NEXT:    sbfx x11, x9, #53, #1
-; VBITS_GE_1024-NEXT:    strb w12, [sp, #55]
-; VBITS_GE_1024-NEXT:    sbfx x12, x9, #52, #1
-; VBITS_GE_1024-NEXT:    strb w10, [sp, #54]
-; VBITS_GE_1024-NEXT:    sbfx x10, x9, #51, #1
-; VBITS_GE_1024-NEXT:    strb w11, [sp, #53]
-; VBITS_GE_1024-NEXT:    sbfx x11, x9, #50, #1
-; VBITS_GE_1024-NEXT:    strb w12, [sp, #52]
-; VBITS_GE_1024-NEXT:    sbfx x12, x9, #49, #1
-; VBITS_GE_1024-NEXT:    strb w10, [sp, #51]
-; VBITS_GE_1024-NEXT:    sbfx x10, x9, #48, #1
-; VBITS_GE_1024-NEXT:    strb w11, [sp, #50]
-; VBITS_GE_1024-NEXT:    sbfx x11, x9, #47, #1
-; VBITS_GE_1024-NEXT:    strb w12, [sp, #49]
-; VBITS_GE_1024-NEXT:    sbfx x12, x9, #46, #1
-; VBITS_GE_1024-NEXT:    strb w10, [sp, #48]
-; VBITS_GE_1024-NEXT:    sbfx x10, x9, #45, #1
-; VBITS_GE_1024-NEXT:    strb w11, [sp, #47]
-; VBITS_GE_1024-NEXT:    sbfx x11, x9, #44, #1
-; VBITS_GE_1024-NEXT:    strb w12, [sp, #46]
-; VBITS_GE_1024-NEXT:    sbfx x12, x9, #43, #1
-; VBITS_GE_1024-NEXT:    strb w10, [sp, #45]
-; VBITS_GE_1024-NEXT:    sbfx x10, x9, #42, #1
-; VBITS_GE_1024-NEXT:    strb w11, [sp, #44]
-; VBITS_GE_1024-NEXT:    sbfx x11, x9, #41, #1
-; VBITS_GE_1024-NEXT:    strb w12, [sp, #43]
-; VBITS_GE_1024-NEXT:    sbfx x12, x9, #40, #1
-; VBITS_GE_1024-NEXT:    strb w10, [sp, #42]
-; VBITS_GE_1024-NEXT:    sbfx x10, x9, #39, #1
-; VBITS_GE_1024-NEXT:    strb w11, [sp, #41]
-; VBITS_GE_1024-NEXT:    sbfx x11, x9, #38, #1
-; VBITS_GE_1024-NEXT:    strb w12, [sp, #40]
-; VBITS_GE_1024-NEXT:    sbfx x12, x9, #37, #1
-; VBITS_GE_1024-NEXT:    strb w10, [sp, #39]
-; VBITS_GE_1024-NEXT:    sbfx x10, x9, #36, #1
-; VBITS_GE_1024-NEXT:    strb w11, [sp, #38]
-; VBITS_GE_1024-NEXT:    sbfx x11, x9, #35, #1
-; VBITS_GE_1024-NEXT:    strb w12, [sp, #37]
-; VBITS_GE_1024-NEXT:    sbfx x12, x9, #34, #1
-; VBITS_GE_1024-NEXT:    strb w10, [sp, #36]
-; VBITS_GE_1024-NEXT:    sbfx x10, x9, #33, #1
-; VBITS_GE_1024-NEXT:    strb w11, [sp, #35]
-; VBITS_GE_1024-NEXT:    sbfx x11, x9, #32, #1
-; VBITS_GE_1024-NEXT:    strb w12, [sp, #34]
-; VBITS_GE_1024-NEXT:    asr w12, w9, #31
-; VBITS_GE_1024-NEXT:    strb w10, [sp, #33]
-; VBITS_GE_1024-NEXT:    sbfx w10, w9, #30, #1
-; VBITS_GE_1024-NEXT:    strb w11, [sp, #32]
-; VBITS_GE_1024-NEXT:    sbfx w11, w9, #29, #1
-; VBITS_GE_1024-NEXT:    strb w12, [sp, #31]
-; VBITS_GE_1024-NEXT:    sbfx w12, w9, #28, #1
-; VBITS_GE_1024-NEXT:    strb w10, [sp, #30]
-; VBITS_GE_1024-NEXT:    sbfx w10, w9, #27, #1
-; VBITS_GE_1024-NEXT:    strb w11, [sp, #29]
-; VBITS_GE_1024-NEXT:    sbfx w11, w9, #26, #1
-; VBITS_GE_1024-NEXT:    strb w12, [sp, #28]
-; VBITS_GE_1024-NEXT:    sbfx w12, w9, #25, #1
-; VBITS_GE_1024-NEXT:    strb w10, [sp, #27]
-; VBITS_GE_1024-NEXT:    sbfx w10, w9, #24, #1
-; VBITS_GE_1024-NEXT:    strb w11, [sp, #26]
-; VBITS_GE_1024-NEXT:    sbfx w11, w9, #23, #1
-; VBITS_GE_1024-NEXT:    strb w12, [sp, #25]
-; VBITS_GE_1024-NEXT:    sbfx w12, w9, #22, #1
-; VBITS_GE_1024-NEXT:    strb w10, [sp, #24]
-; VBITS_GE_1024-NEXT:    sbfx w10, w9, #21, #1
-; VBITS_GE_1024-NEXT:    strb w11, [sp, #23]
-; VBITS_GE_1024-NEXT:    sbfx w11, w9, #20, #1
-; VBITS_GE_1024-NEXT:    strb w12, [sp, #22]
-; VBITS_GE_1024-NEXT:    sbfx w12, w9, #19, #1
-; VBITS_GE_1024-NEXT:    strb w10, [sp, #21]
-; VBITS_GE_1024-NEXT:    sbfx w10, w9, #18, #1
-; VBITS_GE_1024-NEXT:    strb w11, [sp, #20]
-; VBITS_GE_1024-NEXT:    sbfx w11, w9, #17, #1
-; VBITS_GE_1024-NEXT:    strb w12, [sp, #19]
-; VBITS_GE_1024-NEXT:    sbfx w12, w9, #16, #1
-; VBITS_GE_1024-NEXT:    strb w10, [sp, #18]
-; VBITS_GE_1024-NEXT:    sbfx w10, w9, #15, #1
-; VBITS_GE_1024-NEXT:    strb w11, [sp, #17]
-; VBITS_GE_1024-NEXT:    sbfx w11, w9, #14, #1
-; VBITS_GE_1024-NEXT:    strb w12, [sp, #16]
-; VBITS_GE_1024-NEXT:    sbfx w12, w9, #13, #1
-; VBITS_GE_1024-NEXT:    strb w10, [sp, #15]
-; VBITS_GE_1024-NEXT:    sbfx w10, w9, #12, #1
-; VBITS_GE_1024-NEXT:    strb w11, [sp, #14]
-; VBITS_GE_1024-NEXT:    sbfx w11, w9, #11, #1
-; VBITS_GE_1024-NEXT:    strb w12, [sp, #13]
-; VBITS_GE_1024-NEXT:    sbfx w12, w9, #10, #1
-; VBITS_GE_1024-NEXT:    strb w10, [sp, #12]
-; VBITS_GE_1024-NEXT:    sbfx w10, w9, #9, #1
-; VBITS_GE_1024-NEXT:    strb w11, [sp, #11]
-; VBITS_GE_1024-NEXT:    sbfx w11, w9, #8, #1
-; VBITS_GE_1024-NEXT:    strb w12, [sp, #10]
-; VBITS_GE_1024-NEXT:    sbfx w12, w9, #7, #1
-; VBITS_GE_1024-NEXT:    strb w10, [sp, #9]
-; VBITS_GE_1024-NEXT:    sbfx w10, w9, #6, #1
-; VBITS_GE_1024-NEXT:    strb w11, [sp, #8]
-; VBITS_GE_1024-NEXT:    sbfx w11, w9, #5, #1
-; VBITS_GE_1024-NEXT:    strb w12, [sp, #7]
-; VBITS_GE_1024-NEXT:    sbfx w12, w9, #4, #1
-; VBITS_GE_1024-NEXT:    strb w10, [sp, #6]
-; VBITS_GE_1024-NEXT:    sbfx w10, w9, #3, #1
-; VBITS_GE_1024-NEXT:    strb w11, [sp, #5]
-; VBITS_GE_1024-NEXT:    sbfx w11, w9, #2, #1
-; VBITS_GE_1024-NEXT:    strb w12, [sp, #4]
-; VBITS_GE_1024-NEXT:    sbfx w12, w9, #1, #1
-; VBITS_GE_1024-NEXT:    sbfx w9, w9, #0, #1
-; VBITS_GE_1024-NEXT:    strb w10, [sp, #3]
-; VBITS_GE_1024-NEXT:    strb w11, [sp, #2]
-; VBITS_GE_1024-NEXT:    strb w12, [sp, #1]
-; VBITS_GE_1024-NEXT:    strb w9, [sp]
-; VBITS_GE_1024-NEXT:    ld1b { z0.b }, p0/z, [x8]
+; VBITS_GE_1024-NEXT:    asr x9, x8, #63
+; VBITS_GE_1024-NEXT:    sbfx x10, x8, #62, #1
+; VBITS_GE_1024-NEXT:    sbfx x11, x8, #61, #1
+; VBITS_GE_1024-NEXT:    strb w9, [sp, #127]
+; VBITS_GE_1024-NEXT:    sbfx x9, x8, #60, #1
+; VBITS_GE_1024-NEXT:    strb w10, [sp, #126]
+; VBITS_GE_1024-NEXT:    sbfx x10, x8, #59, #1
+; VBITS_GE_1024-NEXT:    strb w11, [sp, #125]
+; VBITS_GE_1024-NEXT:    sbfx x11, x8, #58, #1
+; VBITS_GE_1024-NEXT:    strb w9, [sp, #124]
+; VBITS_GE_1024-NEXT:    sbfx x9, x8, #57, #1
+; VBITS_GE_1024-NEXT:    strb w10, [sp, #123]
+; VBITS_GE_1024-NEXT:    sbfx x10, x8, #56, #1
+; VBITS_GE_1024-NEXT:    strb w11, [sp, #122]
+; VBITS_GE_1024-NEXT:    sbfx x11, x8, #55, #1
+; VBITS_GE_1024-NEXT:    strb w9, [sp, #121]
+; VBITS_GE_1024-NEXT:    sbfx x9, x8, #54, #1
+; VBITS_GE_1024-NEXT:    strb w10, [sp, #120]
+; VBITS_GE_1024-NEXT:    sbfx x10, x8, #53, #1
+; VBITS_GE_1024-NEXT:    strb w11, [sp, #119]
+; VBITS_GE_1024-NEXT:    sbfx x11, x8, #52, #1
+; VBITS_GE_1024-NEXT:    strb w9, [sp, #118]
+; VBITS_GE_1024-NEXT:    sbfx x9, x8, #51, #1
+; VBITS_GE_1024-NEXT:    strb w10, [sp, #117]
+; VBITS_GE_1024-NEXT:    sbfx x10, x8, #50, #1
+; VBITS_GE_1024-NEXT:    strb w11, [sp, #116]
+; VBITS_GE_1024-NEXT:    sbfx x11, x8, #49, #1
+; VBITS_GE_1024-NEXT:    strb w9, [sp, #115]
+; VBITS_GE_1024-NEXT:    sbfx x9, x8, #48, #1
+; VBITS_GE_1024-NEXT:    strb w10, [sp, #114]
+; VBITS_GE_1024-NEXT:    sbfx x10, x8, #47, #1
+; VBITS_GE_1024-NEXT:    strb w11, [sp, #113]
+; VBITS_GE_1024-NEXT:    sbfx x11, x8, #46, #1
+; VBITS_GE_1024-NEXT:    strb w9, [sp, #112]
+; VBITS_GE_1024-NEXT:    sbfx x9, x8, #45, #1
+; VBITS_GE_1024-NEXT:    strb w10, [sp, #111]
+; VBITS_GE_1024-NEXT:    sbfx x10, x8, #44, #1
+; VBITS_GE_1024-NEXT:    strb w11, [sp, #110]
+; VBITS_GE_1024-NEXT:    sbfx x11, x8, #43, #1
+; VBITS_GE_1024-NEXT:    strb w9, [sp, #109]
+; VBITS_GE_1024-NEXT:    sbfx x9, x8, #42, #1
+; VBITS_GE_1024-NEXT:    strb w10, [sp, #108]
+; VBITS_GE_1024-NEXT:    sbfx x10, x8, #41, #1
+; VBITS_GE_1024-NEXT:    strb w11, [sp, #107]
+; VBITS_GE_1024-NEXT:    sbfx x11, x8, #40, #1
+; VBITS_GE_1024-NEXT:    strb w9, [sp, #106]
+; VBITS_GE_1024-NEXT:    sbfx x9, x8, #39, #1
+; VBITS_GE_1024-NEXT:    strb w10, [sp, #105]
+; VBITS_GE_1024-NEXT:    sbfx x10, x8, #38, #1
+; VBITS_GE_1024-NEXT:    strb w11, [sp, #104]
+; VBITS_GE_1024-NEXT:    sbfx x11, x8, #37, #1
+; VBITS_GE_1024-NEXT:    strb w9, [sp, #103]
+; VBITS_GE_1024-NEXT:    sbfx x9, x8, #36, #1
+; VBITS_GE_1024-NEXT:    strb w10, [sp, #102]
+; VBITS_GE_1024-NEXT:    sbfx x10, x8, #35, #1
+; VBITS_GE_1024-NEXT:    strb w11, [sp, #101]
+; VBITS_GE_1024-NEXT:    sbfx x11, x8, #34, #1
+; VBITS_GE_1024-NEXT:    strb w9, [sp, #100]
+; VBITS_GE_1024-NEXT:    sbfx x9, x8, #33, #1
+; VBITS_GE_1024-NEXT:    strb w10, [sp, #99]
+; VBITS_GE_1024-NEXT:    sbfx x10, x8, #32, #1
+; VBITS_GE_1024-NEXT:    strb w11, [sp, #98]
+; VBITS_GE_1024-NEXT:    asr w11, w8, #31
+; VBITS_GE_1024-NEXT:    strb w9, [sp, #97]
+; VBITS_GE_1024-NEXT:    sbfx w9, w8, #30, #1
+; VBITS_GE_1024-NEXT:    strb w10, [sp, #96]
+; VBITS_GE_1024-NEXT:    sbfx w10, w8, #29, #1
+; VBITS_GE_1024-NEXT:    strb w11, [sp, #95]
+; VBITS_GE_1024-NEXT:    sbfx w11, w8, #28, #1
+; VBITS_GE_1024-NEXT:    strb w9, [sp, #94]
+; VBITS_GE_1024-NEXT:    sbfx w9, w8, #27, #1
+; VBITS_GE_1024-NEXT:    strb w10, [sp, #93]
+; VBITS_GE_1024-NEXT:    sbfx w10, w8, #26, #1
+; VBITS_GE_1024-NEXT:    strb w11, [sp, #92]
+; VBITS_GE_1024-NEXT:    sbfx w11, w8, #25, #1
+; VBITS_GE_1024-NEXT:    strb w9, [sp, #91]
+; VBITS_GE_1024-NEXT:    sbfx w9, w8, #24, #1
+; VBITS_GE_1024-NEXT:    strb w10, [sp, #90]
+; VBITS_GE_1024-NEXT:    sbfx w10, w8, #23, #1
+; VBITS_GE_1024-NEXT:    strb w11, [sp, #89]
+; VBITS_GE_1024-NEXT:    sbfx w11, w8, #22, #1
+; VBITS_GE_1024-NEXT:    strb w9, [sp, #88]
+; VBITS_GE_1024-NEXT:    sbfx w9, w8, #21, #1
+; VBITS_GE_1024-NEXT:    strb w10, [sp, #87]
+; VBITS_GE_1024-NEXT:    sbfx w10, w8, #20, #1
+; VBITS_GE_1024-NEXT:    strb w11, [sp, #86]
+; VBITS_GE_1024-NEXT:    sbfx w11, w8, #19, #1
+; VBITS_GE_1024-NEXT:    strb w9, [sp, #85]
+; VBITS_GE_1024-NEXT:    sbfx w9, w8, #18, #1
+; VBITS_GE_1024-NEXT:    strb w10, [sp, #84]
+; VBITS_GE_1024-NEXT:    sbfx w10, w8, #17, #1
+; VBITS_GE_1024-NEXT:    strb w11, [sp, #83]
+; VBITS_GE_1024-NEXT:    sbfx w11, w8, #16, #1
+; VBITS_GE_1024-NEXT:    strb w9, [sp, #82]
+; VBITS_GE_1024-NEXT:    sbfx w9, w8, #15, #1
+; VBITS_GE_1024-NEXT:    strb w10, [sp, #81]
+; VBITS_GE_1024-NEXT:    sbfx w10, w8, #14, #1
+; VBITS_GE_1024-NEXT:    strb w11, [sp, #80]
+; VBITS_GE_1024-NEXT:    sbfx w11, w8, #13, #1
+; VBITS_GE_1024-NEXT:    strb w9, [sp, #79]
+; VBITS_GE_1024-NEXT:    sbfx w9, w8, #12, #1
+; VBITS_GE_1024-NEXT:    strb w10, [sp, #78]
+; VBITS_GE_1024-NEXT:    sbfx w10, w8, #11, #1
+; VBITS_GE_1024-NEXT:    strb w11, [sp, #77]
+; VBITS_GE_1024-NEXT:    sbfx w11, w8, #10, #1
+; VBITS_GE_1024-NEXT:    strb w9, [sp, #76]
+; VBITS_GE_1024-NEXT:    sbfx w9, w8, #9, #1
+; VBITS_GE_1024-NEXT:    strb w10, [sp, #75]
+; VBITS_GE_1024-NEXT:    sbfx w10, w8, #8, #1
+; VBITS_GE_1024-NEXT:    strb w11, [sp, #74]
+; VBITS_GE_1024-NEXT:    sbfx w11, w8, #7, #1
+; VBITS_GE_1024-NEXT:    strb w9, [sp, #73]
+; VBITS_GE_1024-NEXT:    sbfx w9, w8, #6, #1
+; VBITS_GE_1024-NEXT:    strb w10, [sp, #72]
+; VBITS_GE_1024-NEXT:    sbfx w10, w8, #5, #1
+; VBITS_GE_1024-NEXT:    strb w11, [sp, #71]
+; VBITS_GE_1024-NEXT:    sbfx w11, w8, #4, #1
+; VBITS_GE_1024-NEXT:    strb w9, [sp, #70]
+; VBITS_GE_1024-NEXT:    sbfx w9, w8, #3, #1
+; VBITS_GE_1024-NEXT:    strb w10, [sp, #69]
+; VBITS_GE_1024-NEXT:    sbfx w10, w8, #2, #1
+; VBITS_GE_1024-NEXT:    strb w11, [sp, #68]
+; VBITS_GE_1024-NEXT:    sbfx w11, w8, #1, #1
+; VBITS_GE_1024-NEXT:    sbfx w8, w8, #0, #1
+; VBITS_GE_1024-NEXT:    strb w9, [sp, #67]
+; VBITS_GE_1024-NEXT:    strb w10, [sp, #66]
+; VBITS_GE_1024-NEXT:    strb w11, [sp, #65]
+; VBITS_GE_1024-NEXT:    strb w8, [sp, #64]
+; VBITS_GE_1024-NEXT:    ldr x8, [x2]
+; VBITS_GE_1024-NEXT:    asr x9, x8, #63
+; VBITS_GE_1024-NEXT:    sbfx x10, x8, #62, #1
+; VBITS_GE_1024-NEXT:    sbfx x11, x8, #61, #1
+; VBITS_GE_1024-NEXT:    strb w9, [sp, #63]
+; VBITS_GE_1024-NEXT:    sbfx x9, x8, #60, #1
+; VBITS_GE_1024-NEXT:    strb w10, [sp, #62]
+; VBITS_GE_1024-NEXT:    sbfx x10, x8, #59, #1
+; VBITS_GE_1024-NEXT:    strb w11, [sp, #61]
+; VBITS_GE_1024-NEXT:    sbfx x11, x8, #58, #1
+; VBITS_GE_1024-NEXT:    strb w9, [sp, #60]
+; VBITS_GE_1024-NEXT:    sbfx x9, x8, #57, #1
+; VBITS_GE_1024-NEXT:    strb w10, [sp, #59]
+; VBITS_GE_1024-NEXT:    sbfx x10, x8, #56, #1
+; VBITS_GE_1024-NEXT:    strb w11, [sp, #58]
+; VBITS_GE_1024-NEXT:    sbfx x11, x8, #55, #1
+; VBITS_GE_1024-NEXT:    strb w9, [sp, #57]
+; VBITS_GE_1024-NEXT:    sbfx x9, x8, #54, #1
+; VBITS_GE_1024-NEXT:    strb w10, [sp, #56]
+; VBITS_GE_1024-NEXT:    sbfx x10, x8, #53, #1
+; VBITS_GE_1024-NEXT:    strb w11, [sp, #55]
+; VBITS_GE_1024-NEXT:    sbfx x11, x8, #52, #1
+; VBITS_GE_1024-NEXT:    strb w9, [sp, #54]
+; VBITS_GE_1024-NEXT:    sbfx x9, x8, #51, #1
+; VBITS_GE_1024-NEXT:    strb w10, [sp, #53]
+; VBITS_GE_1024-NEXT:    sbfx x10, x8, #50, #1
+; VBITS_GE_1024-NEXT:    strb w11, [sp, #52]
+; VBITS_GE_1024-NEXT:    sbfx x11, x8, #49, #1
+; VBITS_GE_1024-NEXT:    strb w9, [sp, #51]
+; VBITS_GE_1024-NEXT:    sbfx x9, x8, #48, #1
+; VBITS_GE_1024-NEXT:    strb w10, [sp, #50]
+; VBITS_GE_1024-NEXT:    sbfx x10, x8, #47, #1
+; VBITS_GE_1024-NEXT:    strb w11, [sp, #49]
+; VBITS_GE_1024-NEXT:    sbfx x11, x8, #46, #1
+; VBITS_GE_1024-NEXT:    strb w9, [sp, #48]
+; VBITS_GE_1024-NEXT:    sbfx x9, x8, #45, #1
+; VBITS_GE_1024-NEXT:    strb w10, [sp, #47]
+; VBITS_GE_1024-NEXT:    sbfx x10, x8, #44, #1
+; VBITS_GE_1024-NEXT:    strb w11, [sp, #46]
+; VBITS_GE_1024-NEXT:    sbfx x11, x8, #43, #1
+; VBITS_GE_1024-NEXT:    strb w9, [sp, #45]
+; VBITS_GE_1024-NEXT:    sbfx x9, x8, #42, #1
+; VBITS_GE_1024-NEXT:    strb w10, [sp, #44]
+; VBITS_GE_1024-NEXT:    sbfx x10, x8, #41, #1
+; VBITS_GE_1024-NEXT:    strb w11, [sp, #43]
+; VBITS_GE_1024-NEXT:    sbfx x11, x8, #40, #1
+; VBITS_GE_1024-NEXT:    strb w9, [sp, #42]
+; VBITS_GE_1024-NEXT:    sbfx x9, x8, #39, #1
+; VBITS_GE_1024-NEXT:    strb w10, [sp, #41]
+; VBITS_GE_1024-NEXT:    sbfx x10, x8, #38, #1
+; VBITS_GE_1024-NEXT:    strb w11, [sp, #40]
+; VBITS_GE_1024-NEXT:    sbfx x11, x8, #37, #1
+; VBITS_GE_1024-NEXT:    strb w9, [sp, #39]
+; VBITS_GE_1024-NEXT:    sbfx x9, x8, #36, #1
+; VBITS_GE_1024-NEXT:    strb w10, [sp, #38]
+; VBITS_GE_1024-NEXT:    sbfx x10, x8, #35, #1
+; VBITS_GE_1024-NEXT:    strb w11, [sp, #37]
+; VBITS_GE_1024-NEXT:    sbfx x11, x8, #34, #1
+; VBITS_GE_1024-NEXT:    strb w9, [sp, #36]
+; VBITS_GE_1024-NEXT:    sbfx x9, x8, #33, #1
+; VBITS_GE_1024-NEXT:    strb w10, [sp, #35]
+; VBITS_GE_1024-NEXT:    sbfx x10, x8, #32, #1
+; VBITS_GE_1024-NEXT:    strb w11, [sp, #34]
+; VBITS_GE_1024-NEXT:    asr w11, w8, #31
+; VBITS_GE_1024-NEXT:    strb w9, [sp, #33]
+; VBITS_GE_1024-NEXT:    sbfx w9, w8, #30, #1
+; VBITS_GE_1024-NEXT:    strb w10, [sp, #32]
+; VBITS_GE_1024-NEXT:    sbfx w10, w8, #29, #1
+; VBITS_GE_1024-NEXT:    strb w11, [sp, #31]
+; VBITS_GE_1024-NEXT:    sbfx w11, w8, #28, #1
+; VBITS_GE_1024-NEXT:    strb w9, [sp, #30]
+; VBITS_GE_1024-NEXT:    sbfx w9, w8, #27, #1
+; VBITS_GE_1024-NEXT:    strb w10, [sp, #29]
+; VBITS_GE_1024-NEXT:    sbfx w10, w8, #26, #1
+; VBITS_GE_1024-NEXT:    strb w11, [sp, #28]
+; VBITS_GE_1024-NEXT:    sbfx w11, w8, #25, #1
+; VBITS_GE_1024-NEXT:    strb w9, [sp, #27]
+; VBITS_GE_1024-NEXT:    sbfx w9, w8, #24, #1
+; VBITS_GE_1024-NEXT:    strb w10, [sp, #26]
+; VBITS_GE_1024-NEXT:    sbfx w10, w8, #23, #1
+; VBITS_GE_1024-NEXT:    strb w11, [sp, #25]
+; VBITS_GE_1024-NEXT:    sbfx w11, w8, #22, #1
+; VBITS_GE_1024-NEXT:    strb w9, [sp, #24]
+; VBITS_GE_1024-NEXT:    sbfx w9, w8, #21, #1
+; VBITS_GE_1024-NEXT:    strb w10, [sp, #23]
+; VBITS_GE_1024-NEXT:    sbfx w10, w8, #20, #1
+; VBITS_GE_1024-NEXT:    strb w11, [sp, #22]
+; VBITS_GE_1024-NEXT:    sbfx w11, w8, #19, #1
+; VBITS_GE_1024-NEXT:    strb w9, [sp, #21]
+; VBITS_GE_1024-NEXT:    sbfx w9, w8, #18, #1
+; VBITS_GE_1024-NEXT:    strb w10, [sp, #20]
+; VBITS_GE_1024-NEXT:    sbfx w10, w8, #17, #1
+; VBITS_GE_1024-NEXT:    strb w11, [sp, #19]
+; VBITS_GE_1024-NEXT:    sbfx w11, w8, #16, #1
+; VBITS_GE_1024-NEXT:    strb w9, [sp, #18]
+; VBITS_GE_1024-NEXT:    sbfx w9, w8, #15, #1
+; VBITS_GE_1024-NEXT:    strb w10, [sp, #17]
+; VBITS_GE_1024-NEXT:    sbfx w10, w8, #14, #1
+; VBITS_GE_1024-NEXT:    strb w11, [sp, #16]
+; VBITS_GE_1024-NEXT:    sbfx w11, w8, #13, #1
+; VBITS_GE_1024-NEXT:    strb w9, [sp, #15]
+; VBITS_GE_1024-NEXT:    sbfx w9, w8, #12, #1
+; VBITS_GE_1024-NEXT:    strb w10, [sp, #14]
+; VBITS_GE_1024-NEXT:    sbfx w10, w8, #11, #1
+; VBITS_GE_1024-NEXT:    strb w11, [sp, #13]
+; VBITS_GE_1024-NEXT:    sbfx w11, w8, #10, #1
+; VBITS_GE_1024-NEXT:    strb w9, [sp, #12]
+; VBITS_GE_1024-NEXT:    sbfx w9, w8, #9, #1
+; VBITS_GE_1024-NEXT:    strb w10, [sp, #11]
+; VBITS_GE_1024-NEXT:    sbfx w10, w8, #8, #1
+; VBITS_GE_1024-NEXT:    strb w11, [sp, #10]
+; VBITS_GE_1024-NEXT:    sbfx w11, w8, #7, #1
+; VBITS_GE_1024-NEXT:    strb w9, [sp, #9]
+; VBITS_GE_1024-NEXT:    sbfx w9, w8, #6, #1
+; VBITS_GE_1024-NEXT:    strb w10, [sp, #8]
+; VBITS_GE_1024-NEXT:    sbfx w10, w8, #5, #1
+; VBITS_GE_1024-NEXT:    strb w11, [sp, #7]
+; VBITS_GE_1024-NEXT:    sbfx w11, w8, #4, #1
+; VBITS_GE_1024-NEXT:    strb w9, [sp, #6]
+; VBITS_GE_1024-NEXT:    sbfx w9, w8, #3, #1
+; VBITS_GE_1024-NEXT:    strb w10, [sp, #5]
+; VBITS_GE_1024-NEXT:    sbfx w10, w8, #2, #1
+; VBITS_GE_1024-NEXT:    strb w11, [sp, #4]
+; VBITS_GE_1024-NEXT:    sbfx w11, w8, #1, #1
+; VBITS_GE_1024-NEXT:    sbfx w8, w8, #0, #1
+; VBITS_GE_1024-NEXT:    strb w9, [sp, #3]
+; VBITS_GE_1024-NEXT:    strb w10, [sp, #2]
+; VBITS_GE_1024-NEXT:    strb w11, [sp, #1]
+; VBITS_GE_1024-NEXT:    strb w8, [sp]
+; VBITS_GE_1024-NEXT:    ld1b { z0.b }, p0/z, [sp]
 ; VBITS_GE_1024-NEXT:    ld1b { z1.b }, p0/z, [x0]
 ; VBITS_GE_1024-NEXT:    ld1b { z2.b }, p0/z, [x1]
 ; VBITS_GE_1024-NEXT:    and z0.b, z0.b, #0x1
 ; VBITS_GE_1024-NEXT:    cmpne p1.b, p1/z, z0.b, #0
 ; VBITS_GE_1024-NEXT:    sel z0.b, p1, z1.b, z2.b
 ; VBITS_GE_1024-NEXT:    st1b { z0.b }, p0, [x0]
 ; VBITS_GE_1024-NEXT:    mov sp, x29
 ; VBITS_GE_1024-NEXT:    ldp x29, x30, [sp], #16 // 16-byte Folded Reload

 ; VBITS_GE_2048:       // %bb.0:
 ; VBITS_GE_2048-NEXT:    stp x29, x30, [sp, #-16]! // 16-byte Folded Spill
 ; VBITS_GE_2048-NEXT:    sub x9, sp, #496
 ; VBITS_GE_2048-NEXT:    mov x29, sp
 ; VBITS_GE_2048-NEXT:    and sp, x9, #0xffffffffffffff00
 ; VBITS_GE_2048-NEXT:    .cfi_def_cfa w29, 16
 ; VBITS_GE_2048-NEXT:    .cfi_offset w30, -8
 ; VBITS_GE_2048-NEXT:    .cfi_offset w29, -16
-; VBITS_GE_2048-NEXT:    ldr x9, [x2, #24]
-; VBITS_GE_2048-NEXT:    mov x8, sp
+; VBITS_GE_2048-NEXT:    ldr x8, [x2, #24]
 ; VBITS_GE_2048-NEXT:    ptrue p0.b, vl256
 ; VBITS_GE_2048-NEXT:    ptrue p1.b
-; VBITS_GE_2048-NEXT:    asr x10, x9, #63
-; VBITS_GE_2048-NEXT:    sbfx x11, x9, #62, #1
-; VBITS_GE_2048-NEXT:    sbfx x12, x9, #61, #1
-; VBITS_GE_2048-NEXT:    strb w10, [sp, #255]
-; VBITS_GE_2048-NEXT:    sbfx x10, x9, #60, #1
-; VBITS_GE_2048-NEXT:    strb w11, [sp, #254]
-; VBITS_GE_2048-NEXT:    sbfx x11, x9, #59, #1
-; VBITS_GE_2048-NEXT:    strb w12, [sp, #253]
-; VBITS_GE_2048-NEXT:    sbfx x12, x9, #58, #1
-; VBITS_GE_2048-NEXT:    strb w10, [sp, #252]
-; VBITS_GE_2048-NEXT:    sbfx x10, x9, #57, #1
-; VBITS_GE_2048-NEXT:    strb w11, [sp, #251]
-; VBITS_GE_2048-NEXT:    sbfx x11, x9, #56, #1
-; VBITS_GE_2048-NEXT:    strb w12, [sp, #250]
-; VBITS_GE_2048-NEXT:    sbfx x12, x9, #55, #1
-; VBITS_GE_2048-NEXT:    strb w10, [sp, #249]
-; VBITS_GE_2048-NEXT:    sbfx x10, x9, #54, #1
-; VBITS_GE_2048-NEXT:    strb w11, [sp, #248]
-; VBITS_GE_2048-NEXT:    sbfx x11, x9, #53, #1
-; VBITS_GE_2048-NEXT:    strb w12, [sp, #247]
-; VBITS_GE_2048-NEXT:    sbfx x12, x9, #52, #1
-; VBITS_GE_2048-NEXT:    strb w10, [sp, #246]
-; VBITS_GE_2048-NEXT:    sbfx x10, x9, #51, #1
-; VBITS_GE_2048-NEXT:    strb w11, [sp, #245]
-; VBITS_GE_2048-NEXT:    sbfx x11, x9, #50, #1
-; VBITS_GE_2048-NEXT:    strb w12, [sp, #244]
-; VBITS_GE_2048-NEXT:    sbfx x12, x9, #49, #1
-; VBITS_GE_2048-NEXT:    strb w10, [sp, #243]
-; VBITS_GE_2048-NEXT:    sbfx x10, x9, #48, #1
-; VBITS_GE_2048-NEXT:    strb w11, [sp, #242]
-; VBITS_GE_2048-NEXT:    sbfx x11, x9, #47, #1
-; VBITS_GE_2048-NEXT:    strb w12, [sp, #241]
-; VBITS_GE_2048-NEXT:    sbfx x12, x9, #46, #1
-; VBITS_GE_2048-NEXT:    strb w10, [sp, #240]
-; VBITS_GE_2048-NEXT:    sbfx x10, x9, #45, #1
-; VBITS_GE_2048-NEXT:    strb w11, [sp, #239]
-; VBITS_GE_2048-NEXT:    sbfx x11, x9, #44, #1
-; VBITS_GE_2048-NEXT:    strb w12, [sp, #238]
-; VBITS_GE_2048-NEXT:    sbfx x12, x9, #43, #1
-; VBITS_GE_2048-NEXT:    strb w10, [sp, #237]
-; VBITS_GE_2048-NEXT:    sbfx x10, x9, #42, #1
-; VBITS_GE_2048-NEXT:    strb w11, [sp, #236]
-; VBITS_GE_2048-NEXT:    sbfx x11, x9, #41, #1
-; VBITS_GE_2048-NEXT:    strb w12, [sp, #235]
-; VBITS_GE_2048-NEXT:    sbfx x12, x9, #40, #1
-; VBITS_GE_2048-NEXT:    strb w10, [sp, #234]
-; VBITS_GE_2048-NEXT:    sbfx x10, x9, #39, #1
-; VBITS_GE_2048-NEXT:    strb w11, [sp, #233]
-; VBITS_GE_2048-NEXT:    sbfx x11, x9, #38, #1
-; VBITS_GE_2048-NEXT:    strb w12, [sp, #232]
-; VBITS_GE_2048-NEXT:    sbfx x12, x9, #37, #1
-; VBITS_GE_2048-NEXT:    strb w10, [sp, #231]
-; VBITS_GE_2048-NEXT:    sbfx x10, x9, #36, #1
-; VBITS_GE_2048-NEXT:    strb w11, [sp, #230]
-; VBITS_GE_2048-NEXT:    sbfx x11, x9, #35, #1
-; VBITS_GE_2048-NEXT:    strb w12, [sp, #229]
-; VBITS_GE_2048-NEXT:    sbfx x12, x9, #34, #1
-; VBITS_GE_2048-NEXT:    strb w10, [sp, #228]
-; VBITS_GE_2048-NEXT:    sbfx x10, x9, #33, #1
-; VBITS_GE_2048-NEXT:    strb w11, [sp, #227]
-; VBITS_GE_2048-NEXT:    sbfx x11, x9, #32, #1
-; VBITS_GE_2048-NEXT:    strb w12, [sp, #226]
-; VBITS_GE_2048-NEXT:    asr w12, w9, #31
-; VBITS_GE_2048-NEXT:    strb w10, [sp, #225]
-; VBITS_GE_2048-NEXT:    sbfx w10, w9, #30, #1
-; VBITS_GE_2048-NEXT:    strb w11, [sp, #224]
-; VBITS_GE_2048-NEXT:    sbfx w11, w9, #29, #1
-; VBITS_GE_2048-NEXT:    strb w12, [sp, #223]
-; VBITS_GE_2048-NEXT:    sbfx w12, w9, #28, #1
-; VBITS_GE_2048-NEXT:    strb w10, [sp, #222]
-; VBITS_GE_2048-NEXT:    sbfx w10, w9, #27, #1
-; VBITS_GE_2048-NEXT:    strb w11, [sp, #221]
-; VBITS_GE_2048-NEXT:    sbfx w11, w9, #26, #1
-; VBITS_GE_2048-NEXT:    strb w12, [sp, #220]
-; VBITS_GE_2048-NEXT:    sbfx w12, w9, #25, #1
-; VBITS_GE_2048-NEXT:    strb w10, [sp, #219]
-; VBITS_GE_2048-NEXT:    sbfx w10, w9, #24, #1
-; VBITS_GE_2048-NEXT:    strb w11, [sp, #218]
-; VBITS_GE_2048-NEXT:    sbfx w11, w9, #23, #1
-; VBITS_GE_2048-NEXT:    strb w12, [sp, #217]
-; VBITS_GE_2048-NEXT:    sbfx w12, w9, #22, #1
-; VBITS_GE_2048-NEXT:    strb w10, [sp, #216]
-; VBITS_GE_2048-NEXT:    sbfx w10, w9, #21, #1
-; VBITS_GE_2048-NEXT:    strb w11, [sp, #215]
-; VBITS_GE_2048-NEXT:    sbfx w11, w9, #20, #1
-; VBITS_GE_2048-NEXT:    strb w12, [sp, #214]
-; VBITS_GE_2048-NEXT:    sbfx w12, w9, #19, #1
-; VBITS_GE_2048-NEXT:    strb w10, [sp, #213]
-; VBITS_GE_2048-NEXT:    sbfx w10, w9, #18, #1
-; VBITS_GE_2048-NEXT:    strb w11, [sp, #212]
-; VBITS_GE_2048-NEXT:    sbfx w11, w9, #17, #1
-; VBITS_GE_2048-NEXT:    strb w12, [sp, #211]
-; VBITS_GE_2048-NEXT:    sbfx w12, w9, #16, #1
-; VBITS_GE_2048-NEXT:    strb w10, [sp, #210]
-; VBITS_GE_2048-NEXT:    sbfx w10, w9, #15, #1
-; VBITS_GE_2048-NEXT:    strb w11, [sp, #209]
-; VBITS_GE_2048-NEXT:    sbfx w11, w9, #14, #1
-; VBITS_GE_2048-NEXT:    strb w12, [sp, #208]
-; VBITS_GE_2048-NEXT:    sbfx w12, w9, #13, #1
-; VBITS_GE_2048-NEXT:    strb w10, [sp, #207]
-; VBITS_GE_2048-NEXT:    sbfx w10, w9, #12, #1
-; VBITS_GE_2048-NEXT:    strb w11, [sp, #206]
-; VBITS_GE_2048-NEXT:    sbfx w11, w9, #11, #1
-; VBITS_GE_2048-NEXT:    strb w12, [sp, #205]
-; VBITS_GE_2048-NEXT:    sbfx w12, w9, #10, #1
-; VBITS_GE_2048-NEXT:    strb w10, [sp, #204]
-; VBITS_GE_2048-NEXT:    sbfx w10, w9, #9, #1
-; VBITS_GE_2048-NEXT:    strb w11, [sp, #203]
-; VBITS_GE_2048-NEXT:    sbfx w11, w9, #8, #1
-; VBITS_GE_2048-NEXT:    strb w12, [sp, #202]
-; VBITS_GE_2048-NEXT:    sbfx w12, w9, #7, #1
-; VBITS_GE_2048-NEXT:    strb w10, [sp, #201]
-; VBITS_GE_2048-NEXT:    sbfx w10, w9, #6, #1
-; VBITS_GE_2048-NEXT:    strb w11, [sp, #200]
-; VBITS_GE_2048-NEXT:    sbfx w11, w9, #5, #1
-; VBITS_GE_2048-NEXT:    strb w12, [sp, #199]
-; VBITS_GE_2048-NEXT:    sbfx w12, w9, #4, #1
-; VBITS_GE_2048-NEXT:    strb w10, [sp, #198]
-; VBITS_GE_2048-NEXT:    sbfx w10, w9, #3, #1
-; VBITS_GE_2048-NEXT:    strb w11, [sp, #197]
-; VBITS_GE_2048-NEXT:    sbfx w11, w9, #2, #1
-; VBITS_GE_2048-NEXT:    strb w12, [sp, #196]
-; VBITS_GE_2048-NEXT:    sbfx w12, w9, #1, #1
-; VBITS_GE_2048-NEXT:    sbfx w9, w9, #0, #1
-; VBITS_GE_2048-NEXT:    strb w10, [sp, #195]
-; VBITS_GE_2048-NEXT:    strb w11, [sp, #194]
-; VBITS_GE_2048-NEXT:    strb w12, [sp, #193]
-; VBITS_GE_2048-NEXT:    strb w9, [sp, #192]
-; VBITS_GE_2048-NEXT:    ldr x9, [x2, #16]
-; VBITS_GE_2048-NEXT:    asr x10, x9, #63
-; VBITS_GE_2048-NEXT:    sbfx x11, x9, #62, #1
-; VBITS_GE_2048-NEXT:    sbfx x12, x9, #61, #1
-; VBITS_GE_2048-NEXT:    strb w10, [sp, #191]
-; VBITS_GE_2048-NEXT:    sbfx x10, x9, #60, #1
-; VBITS_GE_2048-NEXT:    strb w11, [sp, #190]
-; VBITS_GE_2048-NEXT:    sbfx x11, x9, #59, #1
-; VBITS_GE_2048-NEXT:    strb w12, [sp, #189]
-; VBITS_GE_2048-NEXT:    sbfx x12, x9, #58, #1
-; VBITS_GE_2048-NEXT:    strb w10, [sp, #188]
-; VBITS_GE_2048-NEXT:    sbfx x10, x9, #57, #1
-; VBITS_GE_2048-NEXT:    strb w11, [sp, #187]
-; VBITS_GE_2048-NEXT:    sbfx x11, x9, #56, #1
-; VBITS_GE_2048-NEXT:    strb w12, [sp, #186]
-; VBITS_GE_2048-NEXT:    sbfx x12, x9, #55, #1
-; VBITS_GE_2048-NEXT:    strb w10, [sp, #185]
-; VBITS_GE_2048-NEXT:    sbfx x10, x9, #54, #1
-; VBITS_GE_2048-NEXT:    strb w11, [sp, #184]
-; VBITS_GE_2048-NEXT:    sbfx x11, x9, #53, #1
-; VBITS_GE_2048-NEXT:    strb w12, [sp, #183]
-; VBITS_GE_2048-NEXT:    sbfx x12, x9, #52, #1
-; VBITS_GE_2048-NEXT:    strb w10, [sp, #182]
-; VBITS_GE_2048-NEXT:    sbfx x10, x9, #51, #1
-; VBITS_GE_2048-NEXT:    strb w11, [sp, #181]
-; VBITS_GE_2048-NEXT:    sbfx x11, x9, #50, #1
-; VBITS_GE_2048-NEXT:    strb w12, [sp, #180]
-; VBITS_GE_2048-NEXT:    sbfx x12, x9, #49, #1
-; VBITS_GE_2048-NEXT:    strb w10, [sp, #179]
-; VBITS_GE_2048-NEXT:    sbfx x10, x9, #48, #1
-; VBITS_GE_2048-NEXT:    strb w11, [sp, #178]
-; VBITS_GE_2048-NEXT:    sbfx x11, x9, #47, #1
-; VBITS_GE_2048-NEXT:    strb w12, [sp, #177]
-; VBITS_GE_2048-NEXT:    sbfx x12, x9, #46, #1
-; VBITS_GE_2048-NEXT:    strb w10, [sp, #176]
-; VBITS_GE_2048-NEXT:    sbfx x10, x9, #45, #1
-; VBITS_GE_2048-NEXT:    strb w11, [sp, #175]
-; VBITS_GE_2048-NEXT:    sbfx x11, x9, #44, #1
-; VBITS_GE_2048-NEXT:    strb w12, [sp, #174]
-; VBITS_GE_2048-NEXT:    sbfx x12, x9, #43, #1
-; VBITS_GE_2048-NEXT:    strb w10, [sp, #173]
-; VBITS_GE_2048-NEXT:    sbfx x10, x9, #42, #1
-; VBITS_GE_2048-NEXT:    strb w11, [sp, #172]
-; VBITS_GE_2048-NEXT:    sbfx x11, x9, #41, #1
-; VBITS_GE_2048-NEXT:    strb w12, [sp, #171]
-; VBITS_GE_2048-NEXT:    sbfx x12, x9, #40, #1
-; VBITS_GE_2048-NEXT:    strb w10, [sp, #170]
-; VBITS_GE_2048-NEXT:    sbfx x10, x9, #39, #1
-; VBITS_GE_2048-NEXT:    strb w11, [sp, #169]
-; VBITS_GE_2048-NEXT:    sbfx x11, x9, #38, #1
-; VBITS_GE_2048-NEXT:    strb w12, [sp, #168]
-; VBITS_GE_2048-NEXT:    sbfx x12, x9, #37, #1
-; VBITS_GE_2048-NEXT:    strb w10, [sp, #167]
-; VBITS_GE_2048-NEXT:    sbfx x10, x9, #36, #1
-; VBITS_GE_2048-NEXT:    strb w11, [sp, #166]
-; VBITS_GE_2048-NEXT:    sbfx x11, x9, #35, #1
-; VBITS_GE_2048-NEXT:    strb w12, [sp, #165]
-; VBITS_GE_2048-NEXT:    sbfx x12, x9, #34, #1
-; VBITS_GE_2048-NEXT:    strb w10, [sp, #164]
-; VBITS_GE_2048-NEXT:    sbfx x10, x9, #33, #1
-; VBITS_GE_2048-NEXT:    strb w11, [sp, #163]
-; VBITS_GE_2048-NEXT:    sbfx x11, x9, #32, #1
-; VBITS_GE_2048-NEXT:    strb w12, [sp, #162]
-; VBITS_GE_2048-NEXT:    asr w12, w9, #31
-; VBITS_GE_2048-NEXT:    strb w10, [sp, #161]
-; VBITS_GE_2048-NEXT:    sbfx w10, w9, #30, #1
-; VBITS_GE_2048-NEXT:    strb w11, [sp, #160]
-; VBITS_GE_2048-NEXT:    sbfx w11, w9, #29, #1
-; VBITS_GE_2048-NEXT:    strb w12, [sp, #159]
-; VBITS_GE_2048-NEXT:    sbfx w12, w9, #28, #1
-; VBITS_GE_2048-NEXT:    strb w10, [sp, #158]
-; VBITS_GE_2048-NEXT:    sbfx w10, w9, #27, #1
-; VBITS_GE_2048-NEXT:    strb w11, [sp, #157]
-; VBITS_GE_2048-NEXT:    sbfx w11, w9, #26, #1
-; VBITS_GE_2048-NEXT:    strb w12, [sp, #156]
-; VBITS_GE_2048-NEXT:    sbfx w12, w9, #25, #1
-; VBITS_GE_2048-NEXT:    strb w10, [sp, #155]
-; VBITS_GE_2048-NEXT:    sbfx w10, w9, #24, #1
-; VBITS_GE_2048-NEXT:    strb w11, [sp, #154]
-; VBITS_GE_2048-NEXT:    sbfx w11, w9, #23, #1
-; VBITS_GE_2048-NEXT:    strb w12, [sp, #153]
-; VBITS_GE_2048-NEXT:    sbfx w12, w9, #22, #1
-; VBITS_GE_2048-NEXT:    strb w10, [sp, #152]
-; VBITS_GE_2048-NEXT:    sbfx w10, w9, #21, #1
-; VBITS_GE_2048-NEXT:    strb w11, [sp, #151]
-; VBITS_GE_2048-NEXT:    sbfx w11, w9, #20, #1
-; VBITS_GE_2048-NEXT:    strb w12, [sp, #150]
-; VBITS_GE_2048-NEXT:    sbfx w12, w9, #19, #1
-; VBITS_GE_2048-NEXT:    strb w10, [sp, #149]
-; VBITS_GE_2048-NEXT:    sbfx w10, w9, #18, #1
-; VBITS_GE_2048-NEXT:    strb w11, [sp, #148]
-; VBITS_GE_2048-NEXT:    sbfx w11, w9, #17, #1
-; VBITS_GE_2048-NEXT:    strb w12, [sp, #147]
-; VBITS_GE_2048-NEXT:    sbfx w12, w9, #16, #1
-; VBITS_GE_2048-NEXT:    strb w10, [sp, #146]
-; VBITS_GE_2048-NEXT:    sbfx w10, w9, #15, #1
-; VBITS_GE_2048-NEXT:    strb w11, [sp, #145]
-; VBITS_GE_2048-NEXT:    sbfx w11, w9, #14, #1
-; VBITS_GE_2048-NEXT:    strb w12, [sp, #144]
-; VBITS_GE_2048-NEXT:    sbfx w12, w9, #13, #1
-; VBITS_GE_2048-NEXT:    strb w10, [sp, #143]
-; VBITS_GE_2048-NEXT:    sbfx w10, w9, #12, #1
-; VBITS_GE_2048-NEXT:    strb w11, [sp, #142]
-; VBITS_GE_2048-NEXT:    sbfx w11, w9, #11, #1
-; VBITS_GE_2048-NEXT:    strb w12, [sp, #141]
-; VBITS_GE_2048-NEXT:    sbfx w12, w9, #10, #1
-; VBITS_GE_2048-NEXT:    strb w10, [sp, #140]
-; VBITS_GE_2048-NEXT:    sbfx w10, w9, #9, #1
-; VBITS_GE_2048-NEXT:    strb w11, [sp, #139]
-; VBITS_GE_2048-NEXT:    sbfx w11, w9, #8, #1
-; VBITS_GE_2048-NEXT:    strb w12, [sp, #138]
-; VBITS_GE_2048-NEXT:    sbfx w12, w9, #7, #1
-; VBITS_GE_2048-NEXT:    strb w10, [sp, #137]
-; VBITS_GE_2048-NEXT:    sbfx w10, w9, #6, #1
-; VBITS_GE_2048-NEXT:    strb w11, [sp, #136]
-; VBITS_GE_2048-NEXT:    sbfx w11, w9, #5, #1
-; VBITS_GE_2048-NEXT:    strb w12, [sp, #135]
-; VBITS_GE_2048-NEXT:    sbfx w12, w9, #4, #1
-; VBITS_GE_2048-NEXT:    strb w10, [sp, #134]
-; VBITS_GE_2048-NEXT:    sbfx w10, w9, #3, #1
-; VBITS_GE_2048-NEXT:    strb w11, [sp, #133]
-; VBITS_GE_2048-NEXT:    sbfx w11, w9, #2, #1
-; VBITS_GE_2048-NEXT:    strb w12, [sp, #132]
-; VBITS_GE_2048-NEXT:    sbfx w12, w9, #1, #1
-; VBITS_GE_2048-NEXT:    sbfx w9, w9, #0, #1
-; VBITS_GE_2048-NEXT:    strb w10, [sp, #131]
-; VBITS_GE_2048-NEXT:    strb w11, [sp, #130]
-; VBITS_GE_2048-NEXT:    strb w12, [sp, #129]
-; VBITS_GE_2048-NEXT:    strb w9, [sp, #128]
-; VBITS_GE_2048-NEXT:    ldr x9, [x2, #8]
-; VBITS_GE_2048-NEXT:    asr x10, x9, #63
-; VBITS_GE_2048-NEXT:    sbfx x11, x9, #62, #1
-; VBITS_GE_2048-NEXT:    sbfx x12, x9, #61, #1
-; VBITS_GE_2048-NEXT:    strb w10, [sp, #127]
-; VBITS_GE_2048-NEXT:    sbfx x10, x9, #60, #1
-; VBITS_GE_2048-NEXT:    strb w11, [sp, #126]
-; VBITS_GE_2048-NEXT:    sbfx x11, x9, #59, #1
-; VBITS_GE_2048-NEXT:    strb w12, [sp, #125]
-; VBITS_GE_2048-NEXT:    sbfx x12, x9, #58, #1
-; VBITS_GE_2048-NEXT:    strb w10, [sp, #124]
-; VBITS_GE_2048-NEXT:    sbfx x10, x9, #57, #1
-; VBITS_GE_2048-NEXT:    strb w11, [sp, #123]
-; VBITS_GE_2048-NEXT:    sbfx x11, x9, #56, #1
-; VBITS_GE_2048-NEXT:    strb w12, [sp, #122]
-; VBITS_GE_2048-NEXT:    sbfx x12, x9, #55, #1
-; VBITS_GE_2048-NEXT:    strb w10, [sp, #121]
-; VBITS_GE_2048-NEXT:    sbfx x10, x9, #54, #1
-; VBITS_GE_2048-NEXT:    strb w11, [sp, #120]
-; VBITS_GE_2048-NEXT:    sbfx x11, x9, #53, #1
-; VBITS_GE_2048-NEXT:    strb w12, [sp, #119]
-; VBITS_GE_2048-NEXT:    sbfx x12, x9, #52, #1
-; VBITS_GE_2048-NEXT:    strb w10, [sp, #118]
-; VBITS_GE_2048-NEXT:    sbfx x10, x9, #51, #1
-; VBITS_GE_2048-NEXT:    strb w11, [sp, #117]
-; VBITS_GE_2048-NEXT:    sbfx x11, x9, #50, #1
-; VBITS_GE_2048-NEXT:    strb w12, [sp, #116]
-; VBITS_GE_2048-NEXT:    sbfx x12, x9, #49, #1
-; VBITS_GE_2048-NEXT:    strb w10, [sp, #115]
-; VBITS_GE_2048-NEXT:    sbfx x10, x9, #48, #1
-; VBITS_GE_2048-NEXT:    strb w11, [sp, #114]
-; VBITS_GE_2048-NEXT:    sbfx x11, x9, #47, #1
-; VBITS_GE_2048-NEXT:    strb w12, [sp, #113]
-; VBITS_GE_2048-NEXT:    sbfx x12, x9, #46, #1
-; VBITS_GE_2048-NEXT:    strb w10, [sp, #112]
-; VBITS_GE_2048-NEXT:    sbfx x10, x9, #45, #1
-; VBITS_GE_2048-NEXT:    strb w11, [sp, #111]
-; VBITS_GE_2048-NEXT:    sbfx x11, x9, #44, #1
-; VBITS_GE_2048-NEXT:    strb w12, [sp, #110]
-; VBITS_GE_2048-NEXT:    sbfx x12, x9, #43, #1
-; VBITS_GE_2048-NEXT:    strb w10, [sp, #109]
-; VBITS_GE_2048-NEXT:    sbfx x10, x9, #42, #1
-; VBITS_GE_2048-NEXT:    strb w11, [sp, #108]
-; VBITS_GE_2048-NEXT:    sbfx x11, x9, #41, #1
-; VBITS_GE_2048-NEXT:    strb w12, [sp, #107]
-; VBITS_GE_2048-NEXT:    sbfx x12, x9, #40, #1
-; VBITS_GE_2048-NEXT:    strb w10, [sp, #106]
-; VBITS_GE_2048-NEXT:    sbfx x10, x9, #39, #1
-; VBITS_GE_2048-NEXT:    strb w11, [sp, #105]
-; VBITS_GE_2048-NEXT:    sbfx x11, x9, #38, #1
-; VBITS_GE_2048-NEXT:    strb w12, [sp, #104]
-; VBITS_GE_2048-NEXT:    sbfx x12, x9, #37, #1
-; VBITS_GE_2048-NEXT:    strb w10, [sp, #103]
-; VBITS_GE_2048-NEXT:    sbfx x10, x9, #36, #1
-; VBITS_GE_2048-NEXT:    strb w11, [sp, #102]
-; VBITS_GE_2048-NEXT:    sbfx x11, x9, #35, #1
-; VBITS_GE_2048-NEXT:    strb w12, [sp, #101]
-; VBITS_GE_2048-NEXT:    sbfx x12, x9, #34, #1
-; VBITS_GE_2048-NEXT:    strb w10, [sp, #100]
-; VBITS_GE_2048-NEXT:    sbfx x10, x9, #33, #1
-; VBITS_GE_2048-NEXT:    strb w11, [sp, #99]
-; VBITS_GE_2048-NEXT:    sbfx x11, x9, #32, #1
-; VBITS_GE_2048-NEXT:    strb w12, [sp, #98]
-; VBITS_GE_2048-NEXT:    asr w12, w9, #31
-; VBITS_GE_2048-NEXT:    strb w10, [sp, #97]
-; VBITS_GE_2048-NEXT:    sbfx w10, w9, #30, #1
-; VBITS_GE_2048-NEXT:    strb w11, [sp, #96]
-; VBITS_GE_2048-NEXT:    sbfx w11, w9, #29, #1
-; VBITS_GE_2048-NEXT:    strb w12, [sp, #95]
-; VBITS_GE_2048-NEXT:    sbfx w12, w9, #28, #1
-; VBITS_GE_2048-NEXT:    strb w10, [sp, #94]
-; VBITS_GE_2048-NEXT:    sbfx w10, w9, #27, #1
-; VBITS_GE_2048-NEXT:    strb w11, [sp, #93]
-; VBITS_GE_2048-NEXT:    sbfx w11, w9, #26, #1
-; VBITS_GE_2048-NEXT:    strb w12, [sp, #92]
-; VBITS_GE_2048-NEXT:    sbfx w12, w9, #25, #1
-; VBITS_GE_2048-NEXT:    strb w10, [sp, #91]
-; VBITS_GE_2048-NEXT:    sbfx w10, w9, #24, #1
-; VBITS_GE_2048-NEXT:    strb w11, [sp, #90]
-; VBITS_GE_2048-NEXT:    sbfx w11, w9, #23, #1
-; VBITS_GE_2048-NEXT:    strb w12, [sp, #89]
-; VBITS_GE_2048-NEXT:    sbfx w12, w9, #22, #1
-; VBITS_GE_2048-NEXT:    strb w10, [sp, #88]
-; VBITS_GE_2048-NEXT:    sbfx w10, w9, #21, #1
-; VBITS_GE_2048-NEXT:    strb w11, [sp, #87]
-; VBITS_GE_2048-NEXT:    sbfx w11, w9, #20, #1
-; VBITS_GE_2048-NEXT:    strb w12, [sp, #86]
-; VBITS_GE_2048-NEXT:    sbfx w12, w9, #19, #1
-; VBITS_GE_2048-NEXT:    strb w10, [sp, #85]
-; VBITS_GE_2048-NEXT:    sbfx w10, w9, #18, #1
-; VBITS_GE_2048-NEXT:    strb w11, [sp, #84]
-; VBITS_GE_2048-NEXT:    sbfx w11, w9, #17, #1
-; VBITS_GE_2048-NEXT:    strb w12, [sp, #83]
-; VBITS_GE_2048-NEXT:    sbfx w12, w9, #16, #1
-; VBITS_GE_2048-NEXT:    strb w10, [sp, #82]
-; VBITS_GE_2048-NEXT:    sbfx w10, w9, #15, #1
-; VBITS_GE_2048-NEXT:    strb w11, [sp, #81]
-; VBITS_GE_2048-NEXT:    sbfx w11, w9, #14, #1
-; VBITS_GE_2048-NEXT:    strb w12, [sp, #80]
-; VBITS_GE_2048-NEXT:    sbfx w12, w9, #13, #1
-; VBITS_GE_2048-NEXT:    strb w10, [sp, #79]
-; VBITS_GE_2048-NEXT:    sbfx w10, w9, #12, #1
-; VBITS_GE_2048-NEXT:    strb w11, [sp, #78]
-; VBITS_GE_2048-NEXT:    sbfx w11, w9, #11, #1
-; VBITS_GE_2048-NEXT:    strb w12, [sp, #77]
-; VBITS_GE_2048-NEXT:    sbfx w12, w9, #10, #1
-; VBITS_GE_2048-NEXT:    strb w10, [sp, #76]
-; VBITS_GE_2048-NEXT:    sbfx w10, w9, #9, #1
-; VBITS_GE_2048-NEXT:    strb w11, [sp, #75]
-; VBITS_GE_2048-NEXT:    sbfx w11, w9, #8, #1
-; VBITS_GE_2048-NEXT:    strb w12, [sp, #74]
-; VBITS_GE_2048-NEXT:    sbfx w12, w9, #7, #1
-; VBITS_GE_2048-NEXT:    strb w10, [sp, #73]
-; VBITS_GE_2048-NEXT:    sbfx w10, w9, #6, #1
-; VBITS_GE_2048-NEXT:    strb w11, [sp, #72]
-; VBITS_GE_2048-NEXT:    sbfx w11, w9, #5, #1
-; VBITS_GE_2048-NEXT:    strb w12, [sp, #71]
-; VBITS_GE_2048-NEXT:    sbfx w12, w9, #4, #1
-; VBITS_GE_2048-NEXT:    strb w10, [sp, #70]
-; VBITS_GE_2048-NEXT:    sbfx w10, w9, #3, #1
-; VBITS_GE_2048-NEXT:    strb w11, [sp, #69]
-; VBITS_GE_2048-NEXT:    sbfx w11, w9, #2, #1
-; VBITS_GE_2048-NEXT:    strb w12, [sp, #68]
-; VBITS_GE_2048-NEXT:    sbfx w12, w9, #1, #1
-; VBITS_GE_2048-NEXT:    sbfx w9, w9, #0, #1
-; VBITS_GE_2048-NEXT:    strb w10, [sp, #67]
-; VBITS_GE_2048-NEXT:    strb w11, [sp, #66]
-; VBITS_GE_2048-NEXT:    strb w12, [sp, #65]
-; VBITS_GE_2048-NEXT:    strb w9, [sp, #64]
-; VBITS_GE_2048-NEXT:    ldr x9, [x2]
-; VBITS_GE_2048-NEXT:    asr x10, x9, #63
-; VBITS_GE_2048-NEXT:    sbfx x11, x9, #62, #1
-; VBITS_GE_2048-NEXT:    sbfx x12, x9, #61, #1
-; VBITS_GE_2048-NEXT:    strb w10, [sp, #63]
-; VBITS_GE_2048-NEXT:    sbfx x10, x9, #60, #1
-; VBITS_GE_2048-NEXT:    strb w11, [sp, #62]
-; VBITS_GE_2048-NEXT:    sbfx x11, x9, #59, #1
-; VBITS_GE_2048-NEXT:    strb w12, [sp, #61]
-; VBITS_GE_2048-NEXT:    sbfx x12, x9, #58, #1
-; VBITS_GE_2048-NEXT:    strb w10, [sp, #60]
-; VBITS_GE_2048-NEXT:    sbfx x10, x9, #57, #1
-; VBITS_GE_2048-NEXT:    strb w11, [sp, #59]
-; VBITS_GE_2048-NEXT:    sbfx x11, x9, #56, #1
-; VBITS_GE_2048-NEXT:    strb w12, [sp, #58]
-; VBITS_GE_2048-NEXT:    sbfx x12, x9, #55, #1
-; VBITS_GE_2048-NEXT:    strb w10, [sp, #57]
-; VBITS_GE_2048-NEXT:    sbfx x10, x9, #54, #1
-; VBITS_GE_2048-NEXT:    strb w11, [sp, #56]
-; VBITS_GE_2048-NEXT:    sbfx x11, x9, #53, #1
-; VBITS_GE_2048-NEXT:    strb w12, [sp, #55]
-; VBITS_GE_2048-NEXT:    sbfx x12, x9, #52, #1
-; VBITS_GE_2048-NEXT:    strb w10, [sp, #54]
-; VBITS_GE_2048-NEXT:    sbfx x10, x9, #51, #1
-; VBITS_GE_2048-NEXT:    strb w11, [sp, #53]
-; VBITS_GE_2048-NEXT:    sbfx x11, x9, #50, #1
-; VBITS_GE_2048-NEXT:    strb w12, [sp, #52]
-; VBITS_GE_2048-NEXT:    sbfx x12, x9, #49, #1
-; VBITS_GE_2048-NEXT:    strb w10, [sp, #51]
-; VBITS_GE_2048-NEXT:    sbfx x10, x9, #48, #1
-; VBITS_GE_2048-NEXT:    strb w11, [sp, #50]
-; VBITS_GE_2048-NEXT:    sbfx x11, x9, #47, #1
-; VBITS_GE_2048-NEXT:    strb w12, [sp, #49]
-; VBITS_GE_2048-NEXT:    sbfx x12, x9, #46, #1
-; VBITS_GE_2048-NEXT:    strb w10, [sp, #48]
-; VBITS_GE_2048-NEXT:    sbfx x10, x9, #45, #1
-; VBITS_GE_2048-NEXT:    strb w11, [sp, #47]
-; VBITS_GE_2048-NEXT:    sbfx x11, x9, #44, #1
-; VBITS_GE_2048-NEXT:    strb w12, [sp, #46]
-; VBITS_GE_2048-NEXT:    sbfx x12, x9, #43, #1
-; VBITS_GE_2048-NEXT:    strb w10, [sp, #45]
-; VBITS_GE_2048-NEXT:    sbfx x10, x9, #42, #1
-; VBITS_GE_2048-NEXT:    strb w11, [sp, #44]
-; VBITS_GE_2048-NEXT:    sbfx x11, x9, #41, #1
-; VBITS_GE_2048-NEXT:    strb w12, [sp, #43]
-; VBITS_GE_2048-NEXT:    sbfx x12, x9, #40, #1
-; VBITS_GE_2048-NEXT:    strb w10, [sp, #42]
-; VBITS_GE_2048-NEXT:    sbfx x10, x9, #39, #1
-; VBITS_GE_2048-NEXT:    strb w11, [sp, #41]
-; VBITS_GE_2048-NEXT:    sbfx x11, x9, #38, #1
-; VBITS_GE_2048-NEXT:    strb w12, [sp, #40]
-; VBITS_GE_2048-NEXT:    sbfx x12, x9, #37, #1
-; VBITS_GE_2048-NEXT:    strb w10, [sp, #39]
-; VBITS_GE_2048-NEXT:    sbfx x10, x9, #36, #1
-; VBITS_GE_2048-NEXT:    strb w11, [sp, #38]
-; VBITS_GE_2048-NEXT:    sbfx x11, x9, #35, #1
-; VBITS_GE_2048-NEXT:    strb w12, [sp, #37]
-; VBITS_GE_2048-NEXT:    sbfx x12, x9, #34, #1
-; VBITS_GE_2048-NEXT:    strb w10, [sp, #36]
-; VBITS_GE_2048-NEXT:    sbfx x10, x9, #33, #1
-; VBITS_GE_2048-NEXT:    strb w11, [sp, #35]
-; VBITS_GE_2048-NEXT:    sbfx x11, x9, #32, #1
-; VBITS_GE_2048-NEXT:    strb w12, [sp, #34]
-; VBITS_GE_2048-NEXT:    asr w12, w9, #31
-; VBITS_GE_2048-NEXT:    strb w10, [sp, #33]
-; VBITS_GE_2048-NEXT:    sbfx w10, w9, #30, #1
-; VBITS_GE_2048-NEXT:    strb w11, [sp, #32]
-; VBITS_GE_2048-NEXT:    sbfx w11, w9, #29, #1
-; VBITS_GE_2048-NEXT:    strb w12, [sp, #31]
-; VBITS_GE_2048-NEXT:    sbfx w12, w9, #28, #1
-; VBITS_GE_2048-NEXT:    strb w10, [sp, #30]
-; VBITS_GE_2048-NEXT:    sbfx w10, w9, #27, #1
-; VBITS_GE_2048-NEXT:    strb w11, [sp, #29]
-; VBITS_GE_2048-NEXT:    sbfx w11, w9, #26, #1
-; VBITS_GE_2048-NEXT:    strb w12, [sp, #28]
-; VBITS_GE_2048-NEXT:    sbfx w12, w9, #25, #1
-; VBITS_GE_2048-NEXT:    strb w10, [sp, #27]
-; VBITS_GE_2048-NEXT:    sbfx w10, w9, #24, #1
-; VBITS_GE_2048-NEXT:    strb w11, [sp, #26]
-; VBITS_GE_2048-NEXT:    sbfx w11, w9, #23, #1
-; VBITS_GE_2048-NEXT:    strb w12, [sp, #25]
-; VBITS_GE_2048-NEXT:    sbfx w12, w9, #22, #1
-; VBITS_GE_2048-NEXT:    strb w10, [sp, #24]
-; VBITS_GE_2048-NEXT:    sbfx w10, w9, #21, #1
-; VBITS_GE_2048-NEXT:    strb w11, [sp, #23]
-; VBITS_GE_2048-NEXT:    sbfx w11, w9, #20, #1
-; VBITS_GE_2048-NEXT:    strb w12, [sp, #22]
-; VBITS_GE_2048-NEXT:    sbfx w12, w9, #19, #1
-; VBITS_GE_2048-NEXT:    strb w10, [sp, #21]
-; VBITS_GE_2048-NEXT:    sbfx w10, w9, #18, #1
-; VBITS_GE_2048-NEXT:    strb w11, [sp, #20]
-; VBITS_GE_2048-NEXT:    sbfx w11, w9, #17, #1
-; VBITS_GE_2048-NEXT:    strb w12, [sp, #19]
-; VBITS_GE_2048-NEXT:    sbfx w12, w9, #16, #1
-; VBITS_GE_2048-NEXT:    strb w10, [sp, #18]
-; VBITS_GE_2048-NEXT:    sbfx w10, w9, #15, #1
-; VBITS_GE_2048-NEXT:    strb w11, [sp, #17]
-; VBITS_GE_2048-NEXT:    sbfx w11, w9, #14, #1
-; VBITS_GE_2048-NEXT:    strb w12, [sp, #16]
-; VBITS_GE_2048-NEXT:    sbfx w12, w9, #13, #1
-; VBITS_GE_2048-NEXT:    strb w10, [sp, #15]
-; VBITS_GE_2048-NEXT:    sbfx w10, w9, #12, #1
-; VBITS_GE_2048-NEXT:    strb w11, [sp, #14]
-; VBITS_GE_2048-NEXT:    sbfx w11, w9, #11, #1
-; VBITS_GE_2048-NEXT:    strb w12, [sp, #13]
-; VBITS_GE_2048-NEXT:    sbfx w12, w9, #10, #1
-; VBITS_GE_2048-NEXT:    strb w10, [sp, #12]
-; VBITS_GE_2048-NEXT:    sbfx w10, w9, #9, #1
-; VBITS_GE_2048-NEXT:    strb w11, [sp, #11]
-; VBITS_GE_2048-NEXT:    sbfx w11, w9, #8, #1
-; VBITS_GE_2048-NEXT:    strb w12, [sp, #10]
-; VBITS_GE_2048-NEXT:    sbfx w12, w9, #7, #1
-; VBITS_GE_2048-NEXT:    strb w10, [sp, #9]
-; VBITS_GE_2048-NEXT:    sbfx w10, w9, #6, #1
-; VBITS_GE_2048-NEXT:    strb w11, [sp, #8]
-; VBITS_GE_2048-NEXT:    sbfx w11, w9, #5, #1
-; VBITS_GE_2048-NEXT:    strb w12, [sp, #7]
-; VBITS_GE_2048-NEXT:    sbfx w12, w9, #4, #1
-; VBITS_GE_2048-NEXT:    strb w10, [sp, #6]
-; VBITS_GE_2048-NEXT:    sbfx w10, w9, #3, #1
-; VBITS_GE_2048-NEXT:    strb w11, [sp, #5]
-; VBITS_GE_2048-NEXT:    sbfx w11, w9, #2, #1
-; VBITS_GE_2048-NEXT:    strb w12, [sp, #4]
-; VBITS_GE_2048-NEXT:    sbfx w12, w9, #1, #1
-; VBITS_GE_2048-NEXT:    sbfx w9, w9, #0, #1
-; VBITS_GE_2048-NEXT:    strb w10, [sp, #3]
-; VBITS_GE_2048-NEXT:    strb w11, [sp, #2]
-; VBITS_GE_2048-NEXT:    strb w12, [sp, #1]
-; VBITS_GE_2048-NEXT:    strb w9, [sp]
-; VBITS_GE_2048-NEXT:    ld1b { z0.b }, p0/z, [x8]
+; VBITS_GE_2048-NEXT:    asr x9, x8, #63
+; VBITS_GE_2048-NEXT:    sbfx x10, x8, #62, #1
+; VBITS_GE_2048-NEXT:    sbfx x11, x8, #61, #1
+; VBITS_GE_2048-NEXT:    strb w9, [sp, #255]
+; VBITS_GE_2048-NEXT:    sbfx x9, x8, #60, #1
+; VBITS_GE_2048-NEXT:    strb w10, [sp, #254]
+; VBITS_GE_2048-NEXT:    sbfx x10, x8, #59, #1
+; VBITS_GE_2048-NEXT:    strb w11, [sp, #253]
+; VBITS_GE_2048-NEXT:    sbfx x11, x8, #58, #1
+; VBITS_GE_2048-NEXT:    strb w9, [sp, #252]
+; VBITS_GE_2048-NEXT:    sbfx x9, x8, #57, #1
+; VBITS_GE_2048-NEXT:    strb w10, [sp, #251]
+; VBITS_GE_2048-NEXT:    sbfx x10, x8, #56, #1
+; VBITS_GE_2048-NEXT:    strb w11, [sp, #250]
+; VBITS_GE_2048-NEXT:    sbfx x11, x8, #55, #1
+; VBITS_GE_2048-NEXT:    strb w9, [sp, #249]
+; VBITS_GE_2048-NEXT:    sbfx x9, x8, #54, #1
+; VBITS_GE_2048-NEXT:    strb w10, [sp, #248]
+; VBITS_GE_2048-NEXT:    sbfx x10, x8, #53, #1
+; VBITS_GE_2048-NEXT:    strb w11, [sp, #247]
+; VBITS_GE_2048-NEXT:    sbfx x11, x8, #52, #1
+; VBITS_GE_2048-NEXT:    strb w9, [sp, #246]
+; VBITS_GE_2048-NEXT:    sbfx x9, x8, #51, #1
+; VBITS_GE_2048-NEXT:    strb w10, [sp, #245]
+; VBITS_GE_2048-NEXT:    sbfx x10, x8, #50, #1
+; VBITS_GE_2048-NEXT:    strb w11, [sp, #244]
+; VBITS_GE_2048-NEXT:    sbfx x11, x8, #49, #1
+; VBITS_GE_2048-NEXT:    strb w9, [sp, #243]
+; VBITS_GE_2048-NEXT:    sbfx x9, x8, #48, #1
+; VBITS_GE_2048-NEXT:    strb w10, [sp, #242]
+; VBITS_GE_2048-NEXT:    sbfx x10, x8, #47, #1
+; VBITS_GE_2048-NEXT:    strb w11, [sp, #241]
+; VBITS_GE_2048-NEXT:    sbfx x11, x8, #46, #1
+; VBITS_GE_2048-NEXT:    strb w9, [sp, #240]
+; VBITS_GE_2048-NEXT:    sbfx x9, x8, #45, #1
+; VBITS_GE_2048-NEXT:    strb w10, [sp, #239]
+; VBITS_GE_2048-NEXT:    sbfx x10, x8, #44, #1
+; VBITS_GE_2048-NEXT:    strb w11, [sp, #238]
+; VBITS_GE_2048-NEXT:    sbfx x11, x8, #43, #1
+; VBITS_GE_2048-NEXT:    strb w9, [sp, #237]
+; VBITS_GE_2048-NEXT:    sbfx x9, x8, #42, #1
+; VBITS_GE_2048-NEXT:    strb w10, [sp, #236]
+; VBITS_GE_2048-NEXT:    sbfx x10, x8, #41, #1
+; VBITS_GE_2048-NEXT:    strb w11, [sp, #235]
+; VBITS_GE_2048-NEXT:    sbfx x11, x8, #40, #1
+; VBITS_GE_2048-NEXT:    strb w9, [sp, #234]
+; VBITS_GE_2048-NEXT:    sbfx x9, x8, #39, #1
+; VBITS_GE_2048-NEXT:    strb w10, [sp, #233]
+; VBITS_GE_2048-NEXT:    sbfx x10, x8, #38, #1
+; VBITS_GE_2048-NEXT:    strb w11, [sp, #232]
+; VBITS_GE_2048-NEXT:    sbfx x11, x8, #37, #1
+; VBITS_GE_2048-NEXT:    strb w9, [sp, #231]
+; VBITS_GE_2048-NEXT:    sbfx x9, x8, #36, #1
+; VBITS_GE_2048-NEXT:    strb w10, [sp, #230]
+; VBITS_GE_2048-NEXT:    sbfx x10, x8, #35, #1
+; VBITS_GE_2048-NEXT:    strb w11, [sp, #229]
+; VBITS_GE_2048-NEXT:    sbfx x11, x8, #34, #1
+; VBITS_GE_2048-NEXT:    strb w9, [sp, #228]
+; VBITS_GE_2048-NEXT:    sbfx x9, x8, #33, #1
+; VBITS_GE_2048-NEXT:    strb w10, [sp, #227]
+; VBITS_GE_2048-NEXT:    sbfx x10, x8, #32, #1
+; VBITS_GE_2048-NEXT:    strb w11, [sp, #226]
+; VBITS_GE_2048-NEXT:    asr w11, w8, #31
+; VBITS_GE_2048-NEXT:    strb w9, [sp, #225]
+; VBITS_GE_2048-NEXT:    sbfx w9, w8, #30, #1
+; VBITS_GE_2048-NEXT:    strb w10, [sp, #224]
+; VBITS_GE_2048-NEXT:    sbfx w10, w8, #29, #1
+; VBITS_GE_2048-NEXT:    strb w11, [sp, #223]
+; VBITS_GE_2048-NEXT:    sbfx w11, w8, #28, #1
+; VBITS_GE_2048-NEXT:    strb w9, [sp, #222]
+; VBITS_GE_2048-NEXT:    sbfx w9, w8, #27, #1
+; VBITS_GE_2048-NEXT:    strb w10, [sp, #221]
+; VBITS_GE_2048-NEXT:    sbfx w10, w8, #26, #1
+; VBITS_GE_2048-NEXT:    strb w11, [sp, #220]
+; VBITS_GE_2048-NEXT:    sbfx w11, w8, #25, #1
+; VBITS_GE_2048-NEXT:    strb w9, [sp, #219]
+; VBITS_GE_2048-NEXT:    sbfx w9, w8, #24, #1
+; VBITS_GE_2048-NEXT:    strb w10, [sp, #218]
+; VBITS_GE_2048-NEXT:    sbfx w10, w8, #23, #1
+; VBITS_GE_2048-NEXT:    strb w11, [sp, #217]
+; VBITS_GE_2048-NEXT:    sbfx w11, w8, #22, #1
+; VBITS_GE_2048-NEXT:    strb w9, [sp, #216]
+; VBITS_GE_2048-NEXT:    sbfx w9, w8, #21, #1
+; VBITS_GE_2048-NEXT:    strb w10, [sp, #215]
+; VBITS_GE_2048-NEXT:    sbfx w10, w8, #20, #1
+; VBITS_GE_2048-NEXT:    strb w11, [sp, #214]
+; VBITS_GE_2048-NEXT:    sbfx w11, w8, #19, #1
+; VBITS_GE_2048-NEXT:    strb w9, [sp, #213]
+; VBITS_GE_2048-NEXT:    sbfx w9, w8, #18, #1
+; VBITS_GE_2048-NEXT:    strb w10, [sp, #212]
+; VBITS_GE_2048-NEXT:    sbfx w10, w8, #17, #1
+; VBITS_GE_2048-NEXT:    strb w11, [sp, #211]
+; VBITS_GE_2048-NEXT:    sbfx w11, w8, #16, #1
+; VBITS_GE_2048-NEXT:    strb w9, [sp, #210]
+; VBITS_GE_2048-NEXT:    sbfx w9, w8, #15, #1
+; VBITS_GE_2048-NEXT:    strb w10, [sp, #209]
+; VBITS_GE_2048-NEXT:    sbfx w10, w8, #14, #1
+; VBITS_GE_2048-NEXT:    strb w11, [sp, #208]
+; VBITS_GE_2048-NEXT:    sbfx w11, w8, #13, #1
+; VBITS_GE_2048-NEXT:    strb w9, [sp, #207]
+; VBITS_GE_2048-NEXT:    sbfx w9, w8, #12, #1
+; VBITS_GE_2048-NEXT:    strb w10, [sp, #206]
+; VBITS_GE_2048-NEXT:    sbfx w10, w8, #11, #1
+; VBITS_GE_2048-NEXT:    strb w11, [sp, #205]
+; VBITS_GE_2048-NEXT:    sbfx w11, w8, #10, #1
+; VBITS_GE_2048-NEXT:    strb w9, [sp, #204]
+; VBITS_GE_2048-NEXT:    sbfx w9, w8, #9, #1
+; VBITS_GE_2048-NEXT:    strb w10, [sp, #203]
+; VBITS_GE_2048-NEXT:    sbfx w10, w8, #8, #1
+; VBITS_GE_2048-NEXT:    strb w11, [sp, #202]
+; VBITS_GE_2048-NEXT:    sbfx w11, w8, #7, #1
+; VBITS_GE_2048-NEXT:    strb w9, [sp, #201]
+; VBITS_GE_2048-NEXT:    sbfx w9, w8, #6, #1
+; VBITS_GE_2048-NEXT:    strb w10, [sp, #200]
+; VBITS_GE_2048-NEXT:    sbfx w10, w8, #5, #1
+; VBITS_GE_2048-NEXT:    strb w11, [sp, #199]
+; VBITS_GE_2048-NEXT:    sbfx w11, w8, #4, #1
+; VBITS_GE_2048-NEXT:    strb w9, [sp, #198]
+; VBITS_GE_2048-NEXT:    sbfx w9, w8, #3, #1
+; VBITS_GE_2048-NEXT:    strb w10, [sp, #197]
+; VBITS_GE_2048-NEXT:    sbfx w10, w8, #2, #1
+; VBITS_GE_2048-NEXT:    strb w11, [sp, #196]
+; VBITS_GE_2048-NEXT:    sbfx w11, w8, #1, #1
+; VBITS_GE_2048-NEXT:    sbfx w8, w8, #0, #1
+; VBITS_GE_2048-NEXT:    strb w9, [sp, #195]
+; VBITS_GE_2048-NEXT:    strb w10, [sp, #194]
+; VBITS_GE_2048-NEXT:    strb w11, [sp, #193]
+; VBITS_GE_2048-NEXT:    strb w8, [sp, #192]
+; VBITS_GE_2048-NEXT:    ldr x8, [x2, #16]
+; VBITS_GE_2048-NEXT:    asr x9, x8, #63
+; VBITS_GE_2048-NEXT:    sbfx x10, x8, #62, #1
+; VBITS_GE_2048-NEXT:    sbfx x11, x8, #61, #1
+; VBITS_GE_2048-NEXT:    strb w9, [sp, #191]
+; VBITS_GE_2048-NEXT:    sbfx x9, x8, #60, #1
+; VBITS_GE_2048-NEXT:    strb w10, [sp, #190]
+; VBITS_GE_2048-NEXT:    sbfx x10, x8, #59, #1
+; VBITS_GE_2048-NEXT:    strb w11, [sp, #189]
+; VBITS_GE_2048-NEXT:    sbfx x11, x8, #58, #1
+; VBITS_GE_2048-NEXT:    strb w9, [sp, #188]
+; VBITS_GE_2048-NEXT:    sbfx x9, x8, #57, #1
+; VBITS_GE_2048-NEXT:    strb w10, [sp, #187]
+; VBITS_GE_2048-NEXT:    sbfx x10, x8, #56, #1
+; VBITS_GE_2048-NEXT:    strb w11, [sp, #186]
+; VBITS_GE_2048-NEXT:    sbfx x11, x8, #55, #1
+; VBITS_GE_2048-NEXT:    strb w9, [sp, #185]
+; VBITS_GE_2048-NEXT:    sbfx x9, x8, #54, #1
+; VBITS_GE_2048-NEXT:    strb w10, [sp, #184]
+; VBITS_GE_2048-NEXT:    sbfx x10, x8, #53, #1
+; VBITS_GE_2048-NEXT:    strb w11, [sp, #183]
+; VBITS_GE_2048-NEXT:    sbfx x11, x8, #52, #1
+; VBITS_GE_2048-NEXT:    strb w9, [sp, #182]
+; VBITS_GE_2048-NEXT:    sbfx x9, x8, #51, #1
+; VBITS_GE_2048-NEXT:    strb w10, [sp, #181]
+; VBITS_GE_2048-NEXT:    sbfx x10, x8, #50, #1
+; VBITS_GE_2048-NEXT:    strb w11, [sp, #180]
+; VBITS_GE_2048-NEXT:    sbfx x11, x8, #49, #1
+; VBITS_GE_2048-NEXT:    strb w9, [sp, #179]
+; VBITS_GE_2048-NEXT:    sbfx x9, x8, #48, #1
+; VBITS_GE_2048-NEXT:    strb w10, [sp, #178]
+; VBITS_GE_2048-NEXT:    sbfx x10, x8, #47, #1
+; VBITS_GE_2048-NEXT:    strb w11, [sp, #177]
+; VBITS_GE_2048-NEXT:    sbfx x11, x8, #46, #1
+; VBITS_GE_2048-NEXT:    strb w9, [sp, #176]
+; VBITS_GE_2048-NEXT:    sbfx x9, x8, #45, #1
+; VBITS_GE_2048-NEXT:    strb w10, [sp, #175]
+; VBITS_GE_2048-NEXT:    sbfx x10, x8, #44, #1
+; VBITS_GE_2048-NEXT:    strb w11, [sp, #174]
+; VBITS_GE_2048-NEXT:    sbfx x11, x8, #43, #1
+; VBITS_GE_2048-NEXT:    strb w9, [sp, #173]
+; VBITS_GE_2048-NEXT:    sbfx x9, x8, #42, #1
+; VBITS_GE_2048-NEXT:    strb w10, [sp, #172]
+; VBITS_GE_2048-NEXT:    sbfx x10, x8, #41, #1
+; VBITS_GE_2048-NEXT:    strb w11, [sp, #171]
+; VBITS_GE_2048-NEXT:    sbfx x11, x8, #40, #1
+; VBITS_GE_2048-NEXT:    strb w9, [sp, #170]
+; VBITS_GE_2048-NEXT:    sbfx x9, x8, #39, #1
+; VBITS_GE_2048-NEXT:    strb w10, [sp, #169]
+; VBITS_GE_2048-NEXT:    sbfx x10, x8, #38, #1
+; VBITS_GE_2048-NEXT:    strb w11, [sp, #168]
+; VBITS_GE_2048-NEXT:    sbfx x11, x8, #37, #1
+; VBITS_GE_2048-NEXT:    strb w9, [sp, #167]
+; VBITS_GE_2048-NEXT:    sbfx x9, x8, #36, #1
+; VBITS_GE_2048-NEXT:    strb w10, [sp, #166]
+; VBITS_GE_2048-NEXT:    sbfx x10, x8, #35, #1
+; VBITS_GE_2048-NEXT:    strb w11, [sp, #165]
+; VBITS_GE_2048-NEXT:    sbfx x11, x8, #34, #1
+; VBITS_GE_2048-NEXT:    strb w9, [sp, #164]
+; VBITS_GE_2048-NEXT:    sbfx x9, x8, #33, #1
+; VBITS_GE_2048-NEXT:    strb w10, [sp, #163]
+; VBITS_GE_2048-NEXT:    sbfx x10, x8, #32, #1
+; VBITS_GE_2048-NEXT:    strb w11, [sp, #162]
+; VBITS_GE_2048-NEXT:    asr w11, w8, #31
+; VBITS_GE_2048-NEXT:    strb w9, [sp, #161]
+; VBITS_GE_2048-NEXT:    sbfx w9, w8, #30, #1
+; VBITS_GE_2048-NEXT:    strb w10, [sp, #160]
+; VBITS_GE_2048-NEXT:    sbfx w10, w8, #29, #1
+; VBITS_GE_2048-NEXT:    strb w11, [sp, #159]
+; VBITS_GE_2048-NEXT:    sbfx w11, w8, #28, #1
+; VBITS_GE_2048-NEXT:    strb w9, [sp, #158]
+; VBITS_GE_2048-NEXT:    sbfx w9, w8, #27, #1
+; VBITS_GE_2048-NEXT:    strb w10, [sp, #157]
+; VBITS_GE_2048-NEXT:    sbfx w10, w8, #26, #1
+; VBITS_GE_2048-NEXT:    strb w11, [sp, #156]
+; VBITS_GE_2048-NEXT:    sbfx w11, w8, #25, #1
+; VBITS_GE_2048-NEXT:    strb w9, [sp, #155]
+; VBITS_GE_2048-NEXT:    sbfx w9, w8, #24, #1
+; VBITS_GE_2048-NEXT:    strb w10, [sp, #154]
+; VBITS_GE_2048-NEXT:    sbfx w10, w8, #23, #1
+; VBITS_GE_2048-NEXT:    strb w11, [sp, #153]
+; VBITS_GE_2048-NEXT:    sbfx w11, w8, #22, #1
+; VBITS_GE_2048-NEXT:    strb w9, [sp, #152]
+; VBITS_GE_2048-NEXT:    sbfx w9, w8, #21, #1
+; VBITS_GE_2048-NEXT:    strb w10, [sp, #151]
+; VBITS_GE_2048-NEXT:    sbfx w10, w8, #20, #1
+; VBITS_GE_2048-NEXT:    strb w11, [sp, #150]
+; VBITS_GE_2048-NEXT:    sbfx w11, w8, #19, #1
+; VBITS_GE_2048-NEXT:    strb w9, [sp, #149]
+; VBITS_GE_2048-NEXT:    sbfx w9, w8, #18, #1
+; VBITS_GE_2048-NEXT:    strb w10, [sp, #148]
+; VBITS_GE_2048-NEXT:    sbfx w10, w8, #17, #1
+; VBITS_GE_2048-NEXT:    strb w11, [sp, #147]
+; VBITS_GE_2048-NEXT:    sbfx w11, w8, #16, #1
+; VBITS_GE_2048-NEXT:    strb w9, [sp, #146]
+; VBITS_GE_2048-NEXT:    sbfx w9, w8, #15, #1
+; VBITS_GE_2048-NEXT:    strb w10, [sp, #145]
+; VBITS_GE_2048-NEXT:    sbfx w10, w8, #14, #1
+; VBITS_GE_2048-NEXT:    strb w11, [sp, #144]
+; VBITS_GE_2048-NEXT:    sbfx w11, w8, #13, #1
+; VBITS_GE_2048-NEXT:    strb w9, [sp, #143]
+; VBITS_GE_2048-NEXT:    sbfx w9, w8, #12, #1
+; VBITS_GE_2048-NEXT:    strb w10, [sp, #142]
+; VBITS_GE_2048-NEXT:    sbfx w10, w8, #11, #1
+; VBITS_GE_2048-NEXT:    strb w11, [sp, #141]
+; VBITS_GE_2048-NEXT:    sbfx w11, w8, #10, #1
+; VBITS_GE_2048-NEXT:    strb w9, [sp, #140]
+; VBITS_GE_2048-NEXT:    sbfx w9, w8, #9, #1
+; VBITS_GE_2048-NEXT:    strb w10, [sp, #139]
+; VBITS_GE_2048-NEXT:    sbfx w10, w8, #8, #1
+; VBITS_GE_2048-NEXT:    strb w11, [sp, #138]
+; VBITS_GE_2048-NEXT:    sbfx w11, w8, #7, #1
+; VBITS_GE_2048-NEXT:    strb w9, [sp, #137]
+; VBITS_GE_2048-NEXT:    sbfx w9, w8, #6, #1
+; VBITS_GE_2048-NEXT:    strb w10, [sp, #136]
+; VBITS_GE_2048-NEXT:    sbfx w10, w8, #5, #1
+; VBITS_GE_2048-NEXT:    strb w11, [sp, #135]
+; VBITS_GE_2048-NEXT:    sbfx w11, w8, #4, #1
+; VBITS_GE_2048-NEXT:    strb w9, [sp, #134]
+; VBITS_GE_2048-NEXT:    sbfx w9, w8, #3, #1
+; VBITS_GE_2048-NEXT:    strb w10, [sp, #133]
+; VBITS_GE_2048-NEXT:    sbfx w10, w8, #2, #1
+; VBITS_GE_2048-NEXT:    strb w11, [sp, #132]
+; VBITS_GE_2048-NEXT:    sbfx w11, w8, #1, #1
+; VBITS_GE_2048-NEXT:    sbfx w8, w8, #0, #1
+; VBITS_GE_2048-NEXT:    strb w9, [sp, #131]
+; VBITS_GE_2048-NEXT:    strb w10, [sp, #130]
+; VBITS_GE_2048-NEXT:    strb w11, [sp, #129]
+; VBITS_GE_2048-NEXT:    strb w8, [sp, #128]
+; VBITS_GE_2048-NEXT:    ldr x8, [x2, #8]
+; VBITS_GE_2048-NEXT:    asr x9, x8, #63
+; VBITS_GE_2048-NEXT:    sbfx x10, x8, #62, #1
+; VBITS_GE_2048-NEXT:    sbfx x11, x8, #61, #1
+; VBITS_GE_2048-NEXT:    strb w9, [sp, #127]
+; VBITS_GE_2048-NEXT:    sbfx x9, x8, #60, #1
+; VBITS_GE_2048-NEXT:    strb w10, [sp, #126]
+; VBITS_GE_2048-NEXT:    sbfx x10, x8, #59, #1
+; VBITS_GE_2048-NEXT:    strb w11, [sp, #125]
+; VBITS_GE_2048-NEXT:    sbfx x11, x8, #58, #1
+; VBITS_GE_2048-NEXT:    strb w9, [sp, #124]
+; VBITS_GE_2048-NEXT:    sbfx x9, x8, #57, #1
+; VBITS_GE_2048-NEXT:    strb w10, [sp, #123]
+; VBITS_GE_2048-NEXT:    sbfx x10, x8, #56, #1
+; VBITS_GE_2048-NEXT:    strb w11, [sp, #122]
+; VBITS_GE_2048-NEXT:    sbfx x11, x8, #55, #1
+; VBITS_GE_2048-NEXT:    strb w9, [sp, #121]
+; VBITS_GE_2048-NEXT:    sbfx x9, x8, #54, #1
+; VBITS_GE_2048-NEXT:    strb w10, [sp, #120]
+; VBITS_GE_2048-NEXT:    sbfx x10, x8, #53, #1
+; VBITS_GE_2048-NEXT:    strb w11, [sp, #119]
+; VBITS_GE_2048-NEXT:    sbfx x11, x8, #52, #1
+; VBITS_GE_2048-NEXT:    strb w9, [sp, #118]
+; VBITS_GE_2048-NEXT:    sbfx x9, x8, #51, #1
+; VBITS_GE_2048-NEXT:    strb w10, [sp, #117]
+; VBITS_GE_2048-NEXT:    sbfx x10, x8, #50, #1
+; VBITS_GE_2048-NEXT:    strb w11, [sp, #116]
+; VBITS_GE_2048-NEXT:    sbfx x11, x8, #49, #1
+; VBITS_GE_2048-NEXT:    strb w9, [sp, #115]
+; VBITS_GE_2048-NEXT:    sbfx x9, x8, #48, #1
+; VBITS_GE_2048-NEXT:    strb w10, [sp, #114]
+; VBITS_GE_2048-NEXT:    sbfx x10, x8, #47, #1
+; VBITS_GE_2048-NEXT:    strb w11, [sp, #113]
+; VBITS_GE_2048-NEXT:    sbfx x11, x8, #46, #1
+; VBITS_GE_2048-NEXT:    strb w9, [sp, #112]
+; VBITS_GE_2048-NEXT:    sbfx x9, x8, #45, #1
+; VBITS_GE_2048-NEXT:    strb w10, [sp, #111]
+; VBITS_GE_2048-NEXT:    sbfx x10, x8, #44, #1
+; VBITS_GE_2048-NEXT:    strb w11, [sp, #110]
+; VBITS_GE_2048-NEXT:    sbfx x11, x8, #43, #1
+; VBITS_GE_2048-NEXT:    strb w9, [sp, #109]
+; VBITS_GE_2048-NEXT:    sbfx x9, x8, #42, #1
+; VBITS_GE_2048-NEXT:    strb w10, [sp, #108]
+; VBITS_GE_2048-NEXT:    sbfx x10, x8, #41, #1
+; VBITS_GE_2048-NEXT:    strb w11, [sp, #107]
+; VBITS_GE_2048-NEXT:    sbfx x11, x8, #40, #1
+; VBITS_GE_2048-NEXT:    strb w9, [sp, #106]
+; VBITS_GE_2048-NEXT:    sbfx x9, x8, #39, #1
+; VBITS_GE_2048-NEXT:    strb w10, [sp, #105]
+; VBITS_GE_2048-NEXT:    sbfx x10, x8, #38, #1
+; VBITS_GE_2048-NEXT:    strb w11, [sp, #104]
+; VBITS_GE_2048-NEXT:    sbfx x11, x8, #37, #1
+; VBITS_GE_2048-NEXT:    strb w9, [sp, #103]
+; VBITS_GE_2048-NEXT:    sbfx x9, x8, #36, #1
+; VBITS_GE_2048-NEXT:    strb w10, [sp, #102]
+; VBITS_GE_2048-NEXT:    sbfx x10, x8, #35, #1
+; VBITS_GE_2048-NEXT:    strb w11, [sp, #101]
+; VBITS_GE_2048-NEXT:    sbfx x11, x8, #34, #1
+; VBITS_GE_2048-NEXT:    strb w9, [sp, #100]
+; VBITS_GE_2048-NEXT:    sbfx x9, x8, #33, #1
+; VBITS_GE_2048-NEXT:    strb w10, [sp, #99]
+; VBITS_GE_2048-NEXT:    sbfx x10, x8, #32, #1
+; VBITS_GE_2048-NEXT:    strb w11, [sp, #98]
+; VBITS_GE_2048-NEXT:    asr w11, w8, #31
+; VBITS_GE_2048-NEXT:    strb w9, [sp, #97]
+; VBITS_GE_2048-NEXT:    sbfx w9, w8, #30, #1
+; VBITS_GE_2048-NEXT:    strb w10, [sp, #96]
+; VBITS_GE_2048-NEXT:    sbfx w10, w8, #29, #1
+; VBITS_GE_2048-NEXT:    strb w11, [sp, #95]
+; VBITS_GE_2048-NEXT:    sbfx w11, w8, #28, #1
+; VBITS_GE_2048-NEXT:    strb w9, [sp, #94]
+; VBITS_GE_2048-NEXT:    sbfx w9, w8, #27, #1
+; VBITS_GE_2048-NEXT:    strb w10, [sp, #93]
+; VBITS_GE_2048-NEXT:    sbfx w10, w8, #26, #1
+; VBITS_GE_2048-NEXT:    strb w11, [sp, #92]
+; VBITS_GE_2048-NEXT:    sbfx w11, w8, #25, #1
+; VBITS_GE_2048-NEXT:    strb w9, [sp, #91]
+; VBITS_GE_2048-NEXT:    sbfx w9, w8, #24, #1
+; VBITS_GE_2048-NEXT:    strb w10, [sp, #90]
+; VBITS_GE_2048-NEXT:    sbfx w10, w8, #23, #1
+; VBITS_GE_2048-NEXT:    strb w11, [sp, #89]
+; VBITS_GE_2048-NEXT:    sbfx w11, w8, #22, #1
+; VBITS_GE_2048-NEXT:    strb w9, [sp, #88]
+; VBITS_GE_2048-NEXT:    sbfx w9, w8, #21, #1
+; VBITS_GE_2048-NEXT:    strb w10, [sp, #87]
+; VBITS_GE_2048-NEXT:    sbfx w10, w8, #20, #1
+; VBITS_GE_2048-NEXT:    strb w11, [sp, #86]
+; VBITS_GE_2048-NEXT:    sbfx w11, w8, #19, #1
+; VBITS_GE_2048-NEXT:    strb w9, [sp, #85]
+; VBITS_GE_2048-NEXT:    sbfx w9, w8, #18, #1
+; VBITS_GE_2048-NEXT:    strb w10, [sp, #84]
+; VBITS_GE_2048-NEXT:    sbfx w10, w8, #17, #1
+; VBITS_GE_2048-NEXT:    strb w11, [sp, #83]
+; VBITS_GE_2048-NEXT:    sbfx w11, w8, #16, #1
+; VBITS_GE_2048-NEXT:    strb w9, [sp, #82]
+; VBITS_GE_2048-NEXT:    sbfx w9, w8, #15, #1
+; VBITS_GE_2048-NEXT:    strb w10, [sp, #81]
+; VBITS_GE_2048-NEXT:    sbfx w10, w8, #14, #1
+; VBITS_GE_2048-NEXT:    strb w11, [sp, #80]
+; VBITS_GE_2048-NEXT:    sbfx w11, w8, #13, #1
+; VBITS_GE_2048-NEXT:    strb w9, [sp, #79]
+; VBITS_GE_2048-NEXT:    sbfx w9, w8, #12, #1
+; VBITS_GE_2048-NEXT:    strb w10, [sp, #78]
+; VBITS_GE_2048-NEXT:    sbfx w10, w8, #11, #1
+; VBITS_GE_2048-NEXT:    strb w11, [sp, #77]
+; VBITS_GE_2048-NEXT:    sbfx w11, w8, #10, #1
+; VBITS_GE_2048-NEXT:    strb w9, [sp, #76]
+; VBITS_GE_2048-NEXT:    sbfx w9, w8, #9, #1
+; VBITS_GE_2048-NEXT:    strb w10, [sp, #75]
+; VBITS_GE_2048-NEXT:    sbfx w10, w8, #8, #1
+; VBITS_GE_2048-NEXT:    strb w11, [sp, #74]
+; VBITS_GE_2048-NEXT:    sbfx w11, w8, #7, #1
+; VBITS_GE_2048-NEXT:    strb w9, [sp, #73]
+; VBITS_GE_2048-NEXT:    sbfx w9, w8, #6, #1
+; VBITS_GE_2048-NEXT:    strb w10, [sp, #72]
+; VBITS_GE_2048-NEXT:    sbfx w10, w8, #5, #1
+; VBITS_GE_2048-NEXT:    strb w11, [sp, #71]
+; VBITS_GE_2048-NEXT:    sbfx w11, w8, #4, #1
+; VBITS_GE_2048-NEXT:    strb w9, [sp, #70]
+; VBITS_GE_2048-NEXT:    sbfx w9, w8, #3, #1
+; VBITS_GE_2048-NEXT:    strb w10, [sp, #69]
+; VBITS_GE_2048-NEXT:    sbfx w10, w8, #2, #1
+; VBITS_GE_2048-NEXT:    strb w11, [sp, #68]
+; VBITS_GE_2048-NEXT:    sbfx w11, w8, #1, #1
+; VBITS_GE_2048-NEXT:    sbfx w8, w8, #0, #1
+; VBITS_GE_2048-NEXT:    strb w9, [sp, #67]
+; VBITS_GE_2048-NEXT:    strb w10, [sp, #66]
+; VBITS_GE_2048-NEXT:    strb w11, [sp, #65]
+; VBITS_GE_2048-NEXT:    strb w8, [sp, #64]
+; VBITS_GE_2048-NEXT:    ldr x8, [x2]
+; VBITS_GE_2048-NEXT:    asr x9, x8, #63
+; VBITS_GE_2048-NEXT:    sbfx x10, x8, #62, #1
+; VBITS_GE_2048-NEXT:    sbfx x11, x8, #61, #1
+; VBITS_GE_2048-NEXT:    strb w9, [sp, #63]
+; VBITS_GE_2048-NEXT:    sbfx x9, x8, #60, #1
+; VBITS_GE_2048-NEXT:    strb w10, [sp, #62]
+; VBITS_GE_2048-NEXT:    sbfx x10, x8, #59, #1
+; VBITS_GE_2048-NEXT:    strb w11, [sp, #61]
+; VBITS_GE_2048-NEXT:    sbfx x11, x8, #58, #1
+; VBITS_GE_2048-NEXT:    strb w9, [sp, #60]
+; VBITS_GE_2048-NEXT:    sbfx x9, x8, #57, #1
+; VBITS_GE_2048-NEXT:    strb w10, [sp, #59]
+; VBITS_GE_2048-NEXT:    sbfx x10, x8, #56, #1
+; VBITS_GE_2048-NEXT:    strb w11, [sp, #58]
+; VBITS_GE_2048-NEXT:    sbfx x11, x8, #55, #1
+; VBITS_GE_2048-NEXT:    strb w9, [sp, #57]
+; VBITS_GE_2048-NEXT:    sbfx x9, x8, #54, #1
+; VBITS_GE_2048-NEXT:    strb w10, [sp, #56]
+; VBITS_GE_2048-NEXT:    sbfx x10, x8, #53, #1
+; VBITS_GE_2048-NEXT:    strb w11, [sp, #55]
+; VBITS_GE_2048-NEXT:    sbfx x11, x8, #52, #1
+; VBITS_GE_2048-NEXT:    strb w9, [sp, #54]
+; VBITS_GE_2048-NEXT:    sbfx x9, x8, #51, #1
+; VBITS_GE_2048-NEXT:    strb w10, [sp, #53]
+; VBITS_GE_2048-NEXT:    sbfx x10, x8, #50, #1
+; VBITS_GE_2048-NEXT:    strb w11, [sp, #52]
+; VBITS_GE_2048-NEXT:    sbfx x11, x8, #49, #1
+; VBITS_GE_2048-NEXT:    strb w9, [sp, #51]
+; VBITS_GE_2048-NEXT:    sbfx x9, x8, #48, #1
+; VBITS_GE_2048-NEXT:    strb w10, [sp, #50]
+; VBITS_GE_2048-NEXT:    sbfx x10, x8, #47, #1
+; VBITS_GE_2048-NEXT:    strb w11, [sp, #49]
+; VBITS_GE_2048-NEXT:    sbfx x11, x8, #46, #1
+; VBITS_GE_2048-NEXT:    strb w9, [sp, #48]
+; VBITS_GE_2048-NEXT:    sbfx x9, x8, #45, #1
+; VBITS_GE_2048-NEXT:    strb w10, [sp, #47]
+; VBITS_GE_2048-NEXT:    sbfx x10, x8, #44, #1
+; VBITS_GE_2048-NEXT:    strb w11, [sp, #46]
+; VBITS_GE_2048-NEXT:    sbfx x11, x8, #43, #1
+; VBITS_GE_2048-NEXT:    strb w9, [sp, #45]
+; VBITS_GE_2048-NEXT:    sbfx x9, x8, #42, #1
+; VBITS_GE_2048-NEXT:    strb w10, [sp, #44]
+; VBITS_GE_2048-NEXT:    sbfx x10, x8, #41, #1
+; VBITS_GE_2048-NEXT:    strb w11, [sp, #43]
+; VBITS_GE_2048-NEXT:    sbfx x11, x8, #40, #1
+; VBITS_GE_2048-NEXT:    strb w9, [sp, #42]
+; VBITS_GE_2048-NEXT:    sbfx x9, x8, #39, #1
+; VBITS_GE_2048-NEXT:    strb w10, [sp, #41]
+; VBITS_GE_2048-NEXT:    sbfx x10, x8, #38, #1
+; VBITS_GE_2048-NEXT:    strb w11, [sp, #40]
+; VBITS_GE_2048-NEXT:    sbfx x11, x8, #37, #1
+; VBITS_GE_2048-NEXT:    strb w9, [sp, #39]
+; VBITS_GE_2048-NEXT:    sbfx x9, x8, #36, #1
+; VBITS_GE_2048-NEXT:    strb w10, [sp, #38]
+; VBITS_GE_2048-NEXT:    sbfx x10, x8, #35, #1
+; VBITS_GE_2048-NEXT:    strb w11, [sp, #37]
+; VBITS_GE_2048-NEXT:    sbfx x11, x8, #34, #1
+; VBITS_GE_2048-NEXT:    strb w9, [sp, #36]
+; VBITS_GE_2048-NEXT:    sbfx x9, x8, #33, #1
+; VBITS_GE_2048-NEXT:    strb w10, [sp, #35]
+; VBITS_GE_2048-NEXT:    sbfx x10, x8, #32, #1
+; VBITS_GE_2048-NEXT:    strb w11, [sp, #34]
+; VBITS_GE_2048-NEXT:    asr w11, w8, #31
+; VBITS_GE_2048-NEXT:    strb w9, [sp, #33]
+; VBITS_GE_2048-NEXT:    sbfx w9, w8, #30, #1
+; VBITS_GE_2048-NEXT:    strb w10, [sp, #32]
+; VBITS_GE_2048-NEXT:    sbfx w10, w8, #29, #1
+; VBITS_GE_2048-NEXT:    strb w11, [sp, #31]
+; VBITS_GE_2048-NEXT:    sbfx w11, w8, #28, #1
+; VBITS_GE_2048-NEXT:    strb w9, [sp, #30]
+; VBITS_GE_2048-NEXT:    sbfx w9, w8, #27, #1
+; VBITS_GE_2048-NEXT:    strb w10, [sp, #29]
+; VBITS_GE_2048-NEXT:    sbfx w10, w8, #26, #1
+; VBITS_GE_2048-NEXT:    strb w11, [sp, #28]
+; VBITS_GE_2048-NEXT:    sbfx w11, w8, #25, #1
+; VBITS_GE_2048-NEXT:    strb w9, [sp, #27]
+; VBITS_GE_2048-NEXT:    sbfx w9, w8, #24, #1
+; VBITS_GE_2048-NEXT:    strb w10, [sp, #26]
+; VBITS_GE_2048-NEXT:    sbfx w10, w8, #23, #1
+; VBITS_GE_2048-NEXT:    strb w11, [sp, #25]
+; VBITS_GE_2048-NEXT:    sbfx w11, w8, #22, #1
+; VBITS_GE_2048-NEXT:    strb w9, [sp, #24]
+; VBITS_GE_2048-NEXT:    sbfx w9, w8, #21, #1
+; VBITS_GE_2048-NEXT:    strb w10, [sp, #23]
+; VBITS_GE_2048-NEXT:    sbfx w10, w8, #20, #1
+; VBITS_GE_2048-NEXT:    strb w11, [sp, #22]
+; VBITS_GE_2048-NEXT:    sbfx w11, w8, #19, #1
+; VBITS_GE_2048-NEXT:    strb w9, [sp, #21]
+; VBITS_GE_2048-NEXT:    sbfx w9, w8, #18, #1
+; VBITS_GE_2048-NEXT:    strb w10, [sp, #20]
+; VBITS_GE_2048-NEXT:    sbfx w10, w8, #17, #1
+; VBITS_GE_2048-NEXT:    strb w11, [sp, #19]
+; VBITS_GE_2048-NEXT:    sbfx w11, w8, #16, #1
+; VBITS_GE_2048-NEXT:    strb w9, [sp, #18]
+; VBITS_GE_2048-NEXT:    sbfx w9, w8, #15, #1
+; VBITS_GE_2048-NEXT:    strb w10, [sp, #17]
+; VBITS_GE_2048-NEXT:    sbfx w10, w8, #14, #1
+; VBITS_GE_2048-NEXT:    strb w11, [sp, #16]
+; VBITS_GE_2048-NEXT:    sbfx w11, w8, #13, #1
+; VBITS_GE_2048-NEXT:    strb w9, [sp, #15]
+; VBITS_GE_2048-NEXT:    sbfx w9, w8, #12, #1
+; VBITS_GE_2048-NEXT:    strb w10, [sp, #14]
+; VBITS_GE_2048-NEXT:    sbfx w10, w8, #11, #1
+; VBITS_GE_2048-NEXT:    strb w11, [sp, #13]
+; VBITS_GE_2048-NEXT:    sbfx w11, w8, #10, #1
+; VBITS_GE_2048-NEXT:    strb w9, [sp, #12]
+; VBITS_GE_2048-NEXT:    sbfx w9, w8, #9, #1
+; VBITS_GE_2048-NEXT:    strb w10, [sp, #11]
+; VBITS_GE_2048-NEXT:    sbfx w10, w8, #8, #1
+; VBITS_GE_2048-NEXT:    strb w11, [sp, #10]
+; VBITS_GE_2048-NEXT:    sbfx w11, w8, #7, #1
+; VBITS_GE_2048-NEXT:    strb w9, [sp, #9]
+; VBITS_GE_2048-NEXT:    sbfx w9, w8, #6, #1
+; VBITS_GE_2048-NEXT:    strb w10, [sp, #8]
+; VBITS_GE_2048-NEXT:    sbfx w10, w8, #5, #1
+; VBITS_GE_2048-NEXT:    strb w11, [sp, #7]
+; VBITS_GE_2048-NEXT:    sbfx w11, w8, #4, #1
+; VBITS_GE_2048-NEXT:    strb w9, [sp, #6]
+; VBITS_GE_2048-NEXT:    sbfx w9, w8, #3, #1
+; VBITS_GE_2048-NEXT:    strb w10, [sp, #5]
+; VBITS_GE_2048-NEXT:    sbfx w10, w8, #2, #1
+; VBITS_GE_2048-NEXT:    strb w11, [sp, #4]
+; VBITS_GE_2048-NEXT:    sbfx w11, w8, #1, #1
+; VBITS_GE_2048-NEXT:    sbfx w8, w8, #0, #1
+; VBITS_GE_2048-NEXT:    strb w9, [sp, #3]
+; VBITS_GE_2048-NEXT:    strb w10, [sp, #2]
+; VBITS_GE_2048-NEXT:    strb w11, [sp, #1]
+; VBITS_GE_2048-NEXT:    strb w8, [sp]
+; VBITS_GE_2048-NEXT:    ld1b { z0.b }, p0/z, [sp]
 ; VBITS_GE_2048-NEXT:    ld1b { z1.b }, p0/z, [x0]
 ; VBITS_GE_2048-NEXT:    ld1b { z2.b }, p0/z, [x1]
 ; VBITS_GE_2048-NEXT:    and z0.b, z0.b, #0x1
 ; VBITS_GE_2048-NEXT:    cmpne p1.b, p1/z, z0.b, #0
 ; VBITS_GE_2048-NEXT:    sel z0.b, p1, z1.b, z2.b
 ; VBITS_GE_2048-NEXT:    st1b { z0.b }, p0, [x0]
 ; VBITS_GE_2048-NEXT:    mov sp, x29
 ; VBITS_GE_2048-NEXT:    ldp x29, x30, [sp], #16 // 16-byte Folded Reload

 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    stp x29, x30, [sp, #-16]! // 16-byte Folded Spill
 ; CHECK-NEXT:    sub x9, sp, #48
 ; CHECK-NEXT:    mov x29, sp
 ; CHECK-NEXT:    and sp, x9, #0xffffffffffffffe0
 ; CHECK-NEXT:    .cfi_def_cfa w29, 16
 ; CHECK-NEXT:    .cfi_offset w30, -8
 ; CHECK-NEXT:    .cfi_offset w29, -16
-; CHECK-NEXT:    ldrh w9, [x2]
-; CHECK-NEXT:    mov x8, sp
+; CHECK-NEXT:    ldrh w8, [x2]
 ; CHECK-NEXT:    ptrue p0.h, vl16
 ; CHECK-NEXT:    ptrue p1.h
-; CHECK-NEXT:    sbfx w10, w9, #15, #1
-; CHECK-NEXT:    sbfx w11, w9, #14, #1
-; CHECK-NEXT:    sbfx w12, w9, #13, #1
-; CHECK-NEXT:    strh w10, [sp, #30]
-; CHECK-NEXT:    sbfx w10, w9, #12, #1
-; CHECK-NEXT:    strh w11, [sp, #28]
-; CHECK-NEXT:    sbfx w11, w9, #11, #1
-; CHECK-NEXT:    strh w12, [sp, #26]
-; CHECK-NEXT:    sbfx w12, w9, #10, #1
-; CHECK-NEXT:    strh w10, [sp, #24]
-; CHECK-NEXT:    sbfx w10, w9, #9, #1
-; CHECK-NEXT:    strh w11, [sp, #22]
-; CHECK-NEXT:    sbfx w11, w9, #8, #1
-; CHECK-NEXT:    strh w12, [sp, #20]
-; CHECK-NEXT:    sbfx w12, w9, #7, #1
-; CHECK-NEXT:    strh w10, [sp, #18]
-; CHECK-NEXT:    sbfx w10, w9, #6, #1
-; CHECK-NEXT:    strh w11, [sp, #16]
-; CHECK-NEXT:    sbfx w11, w9, #5, #1
-; CHECK-NEXT:    strh w12, [sp, #14]
-; CHECK-NEXT:    sbfx w12, w9, #4, #1
-; CHECK-NEXT:    strh w10, [sp, #12]
-; CHECK-NEXT:    sbfx w10, w9, #3, #1
-; CHECK-NEXT:    strh w11, [sp, #10]
-; CHECK-NEXT:    sbfx w11, w9, #2, #1
-; CHECK-NEXT:    strh w12, [sp, #8]
-; CHECK-NEXT:    sbfx w12, w9, #1, #1
-; CHECK-NEXT:    sbfx w9, w9, #0, #1
-; CHECK-NEXT:    strh w10, [sp, #6]
-; CHECK-NEXT:    strh w11, [sp, #4]
-; CHECK-NEXT:    strh w12, [sp, #2]
-; CHECK-NEXT:    strh w9, [sp]
-; CHECK-NEXT:    ld1h { z0.h }, p0/z, [x8]
+; CHECK-NEXT:    sbfx w9, w8, #15, #1
+; CHECK-NEXT:    sbfx w10, w8, #14, #1
+; CHECK-NEXT:    sbfx w11, w8, #13, #1
+; CHECK-NEXT:    strh w9, [sp, #30]
+; CHECK-NEXT:    sbfx w9, w8, #12, #1
+; CHECK-NEXT:    strh w10, [sp, #28]
+; CHECK-NEXT:    sbfx w10, w8, #11, #1
+; CHECK-NEXT:    strh w11, [sp, #26]
+; CHECK-NEXT:    sbfx w11, w8, #10, #1
+; CHECK-NEXT:    strh w9, [sp, #24]
+; CHECK-NEXT:    sbfx w9, w8, #9, #1
+; CHECK-NEXT:    strh w10, [sp, #22]
+; CHECK-NEXT:    sbfx w10, w8, #8, #1
+; CHECK-NEXT:    strh w11, [sp, #20]
+; CHECK-NEXT:    sbfx w11, w8, #7, #1
+; CHECK-NEXT:    strh w9, [sp, #18]
+; CHECK-NEXT:    sbfx w9, w8, #6, #1
+; CHECK-NEXT:    strh w10, [sp, #16]
+; CHECK-NEXT:    sbfx w10, w8, #5, #1
+; CHECK-NEXT:    strh w11, [sp, #14]
+; CHECK-NEXT:    sbfx w11, w8, #4, #1
+; CHECK-NEXT:    strh w9, [sp, #12]
+; CHECK-NEXT:    sbfx w9, w8, #3, #1
+; CHECK-NEXT:    strh w10, [sp, #10]
+; CHECK-NEXT:    sbfx w10, w8, #2, #1
+; CHECK-NEXT:    strh w11, [sp, #8]
+; CHECK-NEXT:    sbfx w11, w8, #1, #1
+; CHECK-NEXT:    sbfx w8, w8, #0, #1
+; CHECK-NEXT:    strh w9, [sp, #6]
+; CHECK-NEXT:    strh w10, [sp, #4]
+; CHECK-NEXT:    strh w11, [sp, #2]
+; CHECK-NEXT:    strh w8, [sp]
+; CHECK-NEXT:    ld1h { z0.h }, p0/z, [sp]
 ; CHECK-NEXT:    ld1h { z1.h }, p0/z, [x0]
 ; CHECK-NEXT:    ld1h { z2.h }, p0/z, [x1]
 ; CHECK-NEXT:    and z0.h, z0.h, #0x1
 ; CHECK-NEXT:    cmpne p1.h, p1/z, z0.h, #0
 ; CHECK-NEXT:    sel z0.h, p1, z1.h, z2.h
 ; CHECK-NEXT:    st1h { z0.h }, p0, [x0]
 ; CHECK-NEXT:    mov sp, x29
 ; CHECK-NEXT:    ldp x29, x30, [sp], #16 // 16-byte Folded Reload

 ; VBITS_GE_512:       // %bb.0:
 ; VBITS_GE_512-NEXT:    stp x29, x30, [sp, #-16]! // 16-byte Folded Spill
 ; VBITS_GE_512-NEXT:    sub x9, sp, #112
 ; VBITS_GE_512-NEXT:    mov x29, sp
 ; VBITS_GE_512-NEXT:    and sp, x9, #0xffffffffffffffc0
 ; VBITS_GE_512-NEXT:    .cfi_def_cfa w29, 16
 ; VBITS_GE_512-NEXT:    .cfi_offset w30, -8
 ; VBITS_GE_512-NEXT:    .cfi_offset w29, -16
-; VBITS_GE_512-NEXT:    ldr w9, [x2]
-; VBITS_GE_512-NEXT:    mov x8, sp
+; VBITS_GE_512-NEXT:    ldr w8, [x2]
 ; VBITS_GE_512-NEXT:    ptrue p0.h, vl32
 ; VBITS_GE_512-NEXT:    ptrue p1.h
-; VBITS_GE_512-NEXT:    asr w10, w9, #31
-; VBITS_GE_512-NEXT:    sbfx w11, w9, #30, #1
-; VBITS_GE_512-NEXT:    sbfx w12, w9, #29, #1
-; VBITS_GE_512-NEXT:    strh w10, [sp, #62]
-; VBITS_GE_512-NEXT:    sbfx w10, w9, #28, #1
-; VBITS_GE_512-NEXT:    strh w11, [sp, #60]
-; VBITS_GE_512-NEXT:    sbfx w11, w9, #27, #1
-; VBITS_GE_512-NEXT:    strh w12, [sp, #58]
-; VBITS_GE_512-NEXT:    sbfx w12, w9, #26, #1
-; VBITS_GE_512-NEXT:    strh w10, [sp, #56]
-; VBITS_GE_512-NEXT:    sbfx w10, w9, #25, #1
-; VBITS_GE_512-NEXT:    strh w11, [sp, #54]
-; VBITS_GE_512-NEXT:    sbfx w11, w9, #24, #1
-; VBITS_GE_512-NEXT:    strh w12, [sp, #52]
-; VBITS_GE_512-NEXT:    sbfx w12, w9, #23, #1
-; VBITS_GE_512-NEXT:    strh w10, [sp, #50]
-; VBITS_GE_512-NEXT:    sbfx w10, w9, #22, #1
-; VBITS_GE_512-NEXT:    strh w11, [sp, #48]
-; VBITS_GE_512-NEXT:    sbfx w11, w9, #21, #1
-; VBITS_GE_512-NEXT:    strh w12, [sp, #46]
-; VBITS_GE_512-NEXT:    sbfx w12, w9, #20, #1
-; VBITS_GE_512-NEXT:    strh w10, [sp, #44]
-; VBITS_GE_512-NEXT:    sbfx w10, w9, #19, #1
-; VBITS_GE_512-NEXT:    strh w11, [sp, #42]
-; VBITS_GE_512-NEXT:    sbfx w11, w9, #18, #1
-; VBITS_GE_512-NEXT:    strh w12, [sp, #40]
-; VBITS_GE_512-NEXT:    sbfx w12, w9, #17, #1
-; VBITS_GE_512-NEXT:    strh w10, [sp, #38]
-; VBITS_GE_512-NEXT:    sbfx w10, w9, #16, #1
-; VBITS_GE_512-NEXT:    strh w11, [sp, #36]
-; VBITS_GE_512-NEXT:    sbfx w11, w9, #15, #1
-; VBITS_GE_512-NEXT:    strh w12, [sp, #34]
-; VBITS_GE_512-NEXT:    sbfx w12, w9, #14, #1
-; VBITS_GE_512-NEXT:    strh w10, [sp, #32]
-; VBITS_GE_512-NEXT:    sbfx w10, w9, #13, #1
-; VBITS_GE_512-NEXT:    strh w11, [sp, #30]
-; VBITS_GE_512-NEXT:    sbfx w11, w9, #12, #1
-; VBITS_GE_512-NEXT:    strh w12, [sp, #28]
-; VBITS_GE_512-NEXT:    sbfx w12, w9, #11, #1
-; VBITS_GE_512-NEXT:    strh w10, [sp, #26]
-; VBITS_GE_512-NEXT:    sbfx w10, w9, #10, #1
-; VBITS_GE_512-NEXT:    strh w11, [sp, #24]
-; VBITS_GE_512-NEXT:    sbfx w11, w9, #9, #1
-; VBITS_GE_512-NEXT:    strh w12, [sp, #22]
-; VBITS_GE_512-NEXT:    sbfx w12, w9, #8, #1
-; VBITS_GE_512-NEXT:    strh w10, [sp, #20]
-; VBITS_GE_512-NEXT:    sbfx w10, w9, #7, #1
-; VBITS_GE_512-NEXT:    strh w11, [sp, #18]
-; VBITS_GE_512-NEXT:    sbfx w11, w9, #6, #1
-; VBITS_GE_512-NEXT:    strh w12, [sp, #16]
-; VBITS_GE_512-NEXT:    sbfx w12, w9, #5, #1
-; VBITS_GE_512-NEXT:    strh w10, [sp, #14]
-; VBITS_GE_512-NEXT:    sbfx w10, w9, #4, #1
-; VBITS_GE_512-NEXT:    strh w11, [sp, #12]
-; VBITS_GE_512-NEXT:    sbfx w11, w9, #3, #1
-; VBITS_GE_512-NEXT:    strh w12, [sp, #10]
-; VBITS_GE_512-NEXT:    sbfx w12, w9, #2, #1
-; VBITS_GE_512-NEXT:    strh w10, [sp, #8]
-; VBITS_GE_512-NEXT:    sbfx w10, w9, #1, #1
-; VBITS_GE_512-NEXT:    sbfx w9, w9, #0, #1
-; VBITS_GE_512-NEXT:    strh w11, [sp, #6]
-; VBITS_GE_512-NEXT:    strh w12, [sp, #4]
-; VBITS_GE_512-NEXT:    strh w10, [sp, #2]
-; VBITS_GE_512-NEXT:    strh w9, [sp]
-; VBITS_GE_512-NEXT:    ld1h { z0.h }, p0/z, [x8]
+; VBITS_GE_512-NEXT:    asr w9, w8, #31
+; VBITS_GE_512-NEXT:    sbfx w10, w8, #30, #1
+; VBITS_GE_512-NEXT:    sbfx w11, w8, #29, #1
+; VBITS_GE_512-NEXT:    strh w9, [sp, #62]
+; VBITS_GE_512-NEXT:    sbfx w9, w8, #28, #1
+; VBITS_GE_512-NEXT:    strh w10, [sp, #60]
+; VBITS_GE_512-NEXT:    sbfx w10, w8, #27, #1
+; VBITS_GE_512-NEXT:    strh w11, [sp, #58]
+; VBITS_GE_512-NEXT:    sbfx w11, w8, #26, #1
+; VBITS_GE_512-NEXT:    strh w9, [sp, #56]
+; VBITS_GE_512-NEXT:    sbfx w9, w8, #25, #1
+; VBITS_GE_512-NEXT:    strh w10, [sp, #54]
+; VBITS_GE_512-NEXT:    sbfx w10, w8, #24, #1
+; VBITS_GE_512-NEXT:    strh w11, [sp, #52]
+; VBITS_GE_512-NEXT:    sbfx w11, w8, #23, #1
+; VBITS_GE_512-NEXT:    strh w9, [sp, #50]
+; VBITS_GE_512-NEXT:    sbfx w9, w8, #22, #1
+; VBITS_GE_512-NEXT:    strh w10, [sp, #48]
+; VBITS_GE_512-NEXT:    sbfx w10, w8, #21, #1
+; VBITS_GE_512-NEXT:    strh w11, [sp, #46]
+; VBITS_GE_512-NEXT:    sbfx w11, w8, #20, #1
+; VBITS_GE_512-NEXT:    strh w9, [sp, #44]
+; VBITS_GE_512-NEXT:    sbfx w9, w8, #19, #1
+; VBITS_GE_512-NEXT:    strh w10, [sp, #42]
+; VBITS_GE_512-NEXT:    sbfx w10, w8, #18, #1
+; VBITS_GE_512-NEXT:    strh w11, [sp, #40]
+; VBITS_GE_512-NEXT:    sbfx w11, w8, #17, #1
+; VBITS_GE_512-NEXT:    strh w9, [sp, #38]
+; VBITS_GE_512-NEXT:    sbfx w9, w8, #16, #1
+; VBITS_GE_512-NEXT:    strh w10, [sp, #36]
+; VBITS_GE_512-NEXT:    sbfx w10, w8, #15, #1
+; VBITS_GE_512-NEXT:    strh w11, [sp, #34]
+; VBITS_GE_512-NEXT:    sbfx w11, w8, #14, #1
+; VBITS_GE_512-NEXT:    strh w9, [sp, #32]
+; VBITS_GE_512-NEXT:    sbfx w9, w8, #13, #1
+; VBITS_GE_512-NEXT:    strh w10, [sp, #30]
+; VBITS_GE_512-NEXT:    sbfx w10, w8, #12, #1
+; VBITS_GE_512-NEXT:    strh w11, [sp, #28]
+; VBITS_GE_512-NEXT:    sbfx w11, w8, #11, #1
+; VBITS_GE_512-NEXT:    strh w9, [sp, #26]
+; VBITS_GE_512-NEXT:    sbfx w9, w8, #10, #1
+; VBITS_GE_512-NEXT:    strh w10, [sp, #24]
+; VBITS_GE_512-NEXT:    sbfx w10, w8, #9, #1
+; VBITS_GE_512-NEXT:    strh w11, [sp, #22]
+; VBITS_GE_512-NEXT:    sbfx w11, w8, #8, #1
+; VBITS_GE_512-NEXT:    strh w9, [sp, #20]
+; VBITS_GE_512-NEXT:    sbfx w9, w8, #7, #1
+; VBITS_GE_512-NEXT:    strh w10, [sp, #18]
+; VBITS_GE_512-NEXT:    sbfx w10, w8, #6, #1
+; VBITS_GE_512-NEXT:    strh w11, [sp, #16]
+; VBITS_GE_512-NEXT:    sbfx w11, w8, #5, #1
+; VBITS_GE_512-NEXT:    strh w9, [sp, #14]
+; VBITS_GE_512-NEXT:    sbfx w9, w8, #4, #1
+; VBITS_GE_512-NEXT:    strh w10, [sp, #12]
+; VBITS_GE_512-NEXT:    sbfx w10, w8, #3, #1
+; VBITS_GE_512-NEXT:    strh w11, [sp, #10]
+; VBITS_GE_512-NEXT:    sbfx w11, w8, #2, #1
+; VBITS_GE_512-NEXT:    strh w9, [sp, #8]
+; VBITS_GE_512-NEXT:    sbfx w9, w8, #1, #1
+; VBITS_GE_512-NEXT:    sbfx w8, w8, #0, #1
+; VBITS_GE_512-NEXT:    strh w10, [sp, #6]
+; VBITS_GE_512-NEXT:    strh w11, [sp, #4]
+; VBITS_GE_512-NEXT:    strh w9, [sp, #2]
+; VBITS_GE_512-NEXT:    strh w8, [sp]
+; VBITS_GE_512-NEXT:    ld1h { z0.h }, p0/z, [sp]
 ; VBITS_GE_512-NEXT:    ld1h { z1.h }, p0/z, [x0]
 ; VBITS_GE_512-NEXT:    ld1h { z2.h }, p0/z, [x1]
 ; VBITS_GE_512-NEXT:    and z0.h, z0.h, #0x1
 ; VBITS_GE_512-NEXT:    cmpne p1.h, p1/z, z0.h, #0
 ; VBITS_GE_512-NEXT:    sel z0.h, p1, z1.h, z2.h
 ; VBITS_GE_512-NEXT:    st1h { z0.h }, p0, [x0]
 ; VBITS_GE_512-NEXT:    mov sp, x29
 ; VBITS_GE_512-NEXT:    ldp x29, x30, [sp], #16 // 16-byte Folded Reload

 ; VBITS_GE_1024:       // %bb.0:
 ; VBITS_GE_1024-NEXT:    stp x29, x30, [sp, #-16]! // 16-byte Folded Spill
 ; VBITS_GE_1024-NEXT:    sub x9, sp, #240
 ; VBITS_GE_1024-NEXT:    mov x29, sp
 ; VBITS_GE_1024-NEXT:    and sp, x9, #0xffffffffffffff80
 ; VBITS_GE_1024-NEXT:    .cfi_def_cfa w29, 16
 ; VBITS_GE_1024-NEXT:    .cfi_offset w30, -8
 ; VBITS_GE_1024-NEXT:    .cfi_offset w29, -16
-; VBITS_GE_1024-NEXT:    ldr x9, [x2]
-; VBITS_GE_1024-NEXT:    mov x8, sp
+; VBITS_GE_1024-NEXT:    ldr x8, [x2]
 ; VBITS_GE_1024-NEXT:    ptrue p0.h, vl64
 ; VBITS_GE_1024-NEXT:    ptrue p1.h
-; VBITS_GE_1024-NEXT:    asr x10, x9, #63
-; VBITS_GE_1024-NEXT:    sbfx x11, x9, #62, #1
-; VBITS_GE_1024-NEXT:    sbfx x12, x9, #61, #1
-; VBITS_GE_1024-NEXT:    strh w10, [sp, #126]
-; VBITS_GE_1024-NEXT:    sbfx x10, x9, #60, #1
-; VBITS_GE_1024-NEXT:    strh w11, [sp, #124]
-; VBITS_GE_1024-NEXT:    sbfx x11, x9, #59, #1
-; VBITS_GE_1024-NEXT:    strh w12, [sp, #122]
-; VBITS_GE_1024-NEXT:    sbfx x12, x9, #58, #1
-; VBITS_GE_1024-NEXT:    strh w10, [sp, #120]
-; VBITS_GE_1024-NEXT:    sbfx x10, x9, #57, #1
-; VBITS_GE_1024-NEXT:    strh w11, [sp, #118]
-; VBITS_GE_1024-NEXT:    sbfx x11, x9, #56, #1
-; VBITS_GE_1024-NEXT:    strh w12, [sp, #116]
-; VBITS_GE_1024-NEXT:    sbfx x12, x9, #55, #1
-; VBITS_GE_1024-NEXT:    strh w10, [sp, #114]
-; VBITS_GE_1024-NEXT:    sbfx x10, x9, #54, #1
-; VBITS_GE_1024-NEXT:    strh w11, [sp, #112]
-; VBITS_GE_1024-NEXT:    sbfx x11, x9, #53, #1
-; VBITS_GE_1024-NEXT:    strh w12, [sp, #110]
-; VBITS_GE_1024-NEXT:    sbfx x12, x9, #52, #1
-; VBITS_GE_1024-NEXT:    strh w10, [sp, #108]
-; VBITS_GE_1024-NEXT:    sbfx x10, x9, #51, #1
-; VBITS_GE_1024-NEXT:    strh w11, [sp, #106]
-; VBITS_GE_1024-NEXT:    sbfx x11, x9, #50, #1
-; VBITS_GE_1024-NEXT:    strh w12, [sp, #104]
-; VBITS_GE_1024-NEXT:    sbfx x12, x9, #49, #1
-; VBITS_GE_1024-NEXT:    strh w10, [sp, #102]
-; VBITS_GE_1024-NEXT:    sbfx x10, x9, #48, #1
-; VBITS_GE_1024-NEXT:    strh w11, [sp, #100]
-; VBITS_GE_1024-NEXT:    sbfx x11, x9, #47, #1
-; VBITS_GE_1024-NEXT:    strh w12, [sp, #98]
-; VBITS_GE_1024-NEXT:    sbfx x12, x9, #46, #1
-; VBITS_GE_1024-NEXT:    strh w10, [sp, #96]
-; VBITS_GE_1024-NEXT:    sbfx x10, x9, #45, #1
-; VBITS_GE_1024-NEXT:    strh w11, [sp, #94]
-; VBITS_GE_1024-NEXT:    sbfx x11, x9, #44, #1
-; VBITS_GE_1024-NEXT:    strh w12, [sp, #92]
-; VBITS_GE_1024-NEXT:    sbfx x12, x9, #43, #1
-; VBITS_GE_1024-NEXT:    strh w10, [sp, #90]
-; VBITS_GE_1024-NEXT:    sbfx x10, x9, #42, #1
-; VBITS_GE_1024-NEXT:    strh w11, [sp, #88]
-; VBITS_GE_1024-NEXT:    sbfx x11, x9, #41, #1
-; VBITS_GE_1024-NEXT:    strh w12, [sp, #86]
-; VBITS_GE_1024-NEXT:    sbfx x12, x9, #40, #1
-; VBITS_GE_1024-NEXT:    strh w10, [sp, #84]
-; VBITS_GE_1024-NEXT:    sbfx x10, x9, #39, #1
-; VBITS_GE_1024-NEXT:    strh w11, [sp, #82]
-; VBITS_GE_1024-NEXT:    sbfx x11, x9, #38, #1
-; VBITS_GE_1024-NEXT:    strh w12, [sp, #80]
-; VBITS_GE_1024-NEXT:    sbfx x12, x9, #37, #1
-; VBITS_GE_1024-NEXT:    strh w10, [sp, #78]
-; VBITS_GE_1024-NEXT:    sbfx x10, x9, #36, #1
-; VBITS_GE_1024-NEXT:    strh w11, [sp, #76]
-; VBITS_GE_1024-NEXT:    sbfx x11, x9, #35, #1
-; VBITS_GE_1024-NEXT:    strh w12, [sp, #74]
-; VBITS_GE_1024-NEXT:    sbfx x12, x9, #34, #1
-; VBITS_GE_1024-NEXT:    strh w10, [sp, #72]
-; VBITS_GE_1024-NEXT:    sbfx x10, x9, #33, #1
-; VBITS_GE_1024-NEXT:    strh w11, [sp, #70]
-; VBITS_GE_1024-NEXT:    sbfx x11, x9, #32, #1
-; VBITS_GE_1024-NEXT:    strh w12, [sp, #68]
-; VBITS_GE_1024-NEXT:    asr w12, w9, #31
-; VBITS_GE_1024-NEXT:    strh w10, [sp, #66]
-; VBITS_GE_1024-NEXT:    sbfx w10, w9, #30, #1
-; VBITS_GE_1024-NEXT:    strh w11, [sp, #64]
-; VBITS_GE_1024-NEXT:    sbfx w11, w9, #29, #1
-; VBITS_GE_1024-NEXT:    strh w12, [sp, #62]
-; VBITS_GE_1024-NEXT:    sbfx w12, w9, #28, #1
-; VBITS_GE_1024-NEXT:    strh w10, [sp, #60]
-; VBITS_GE_1024-NEXT:    sbfx w10, w9, #27, #1
-; VBITS_GE_1024-NEXT:    strh w11, [sp, #58]
-; VBITS_GE_1024-NEXT:    sbfx w11, w9, #26, #1
-; VBITS_GE_1024-NEXT:    strh w12, [sp, #56]
-; VBITS_GE_1024-NEXT:    sbfx w12, w9, #25, #1
-; VBITS_GE_1024-NEXT:    strh w10, [sp, #54]
-; VBITS_GE_1024-NEXT:    sbfx w10, w9, #24, #1
-; VBITS_GE_1024-NEXT:    strh w11, [sp, #52]
-; VBITS_GE_1024-NEXT:    sbfx w11, w9, #23, #1
-; VBITS_GE_1024-NEXT:    strh w12, [sp, #50]
-; VBITS_GE_1024-NEXT:    sbfx w12, w9, #22, #1
-; VBITS_GE_1024-NEXT:    strh w10, [sp, #48]
-; VBITS_GE_1024-NEXT:    sbfx w10, w9, #21, #1
-; VBITS_GE_1024-NEXT:    strh w11, [sp, #46]
-; VBITS_GE_1024-NEXT:    sbfx w11, w9, #20, #1
-; VBITS_GE_1024-NEXT:    strh w12, [sp, #44]
-; VBITS_GE_1024-NEXT:    sbfx w12, w9, #19, #1
-; VBITS_GE_1024-NEXT:    strh w10, [sp, #42]
-; VBITS_GE_1024-NEXT:    sbfx w10, w9, #18, #1
-; VBITS_GE_1024-NEXT:    strh w11, [sp, #40]
-; VBITS_GE_1024-NEXT:    sbfx w11, w9, #17, #1
-; VBITS_GE_1024-NEXT:    strh w12, [sp, #38]
-; VBITS_GE_1024-NEXT:    sbfx w12, w9, #16, #1
-; VBITS_GE_1024-NEXT:    strh w10, [sp, #36]
-; VBITS_GE_1024-NEXT:    sbfx w10, w9, #15, #1
-; VBITS_GE_1024-NEXT:    strh w11, [sp, #34]
-; VBITS_GE_1024-NEXT:    sbfx w11, w9, #14, #1
-; VBITS_GE_1024-NEXT:    strh w12, [sp, #32]
-; VBITS_GE_1024-NEXT:    sbfx w12, w9, #13, #1
-; VBITS_GE_1024-NEXT:    strh w10, [sp, #30]
-; VBITS_GE_1024-NEXT:    sbfx w10, w9, #12, #1
-; VBITS_GE_1024-NEXT:    strh w11, [sp, #28]
-; VBITS_GE_1024-NEXT:    sbfx w11, w9, #11, #1
-; VBITS_GE_1024-NEXT:    strh w12, [sp, #26]
-; VBITS_GE_1024-NEXT:    sbfx w12, w9, #10, #1
-; VBITS_GE_1024-NEXT:    strh w10, [sp, #24]
-; VBITS_GE_1024-NEXT:    sbfx w10, w9, #9, #1
-; VBITS_GE_1024-NEXT:    strh w11, [sp, #22]
-; VBITS_GE_1024-NEXT:    sbfx w11, w9, #8, #1
-; VBITS_GE_1024-NEXT:    strh w12, [sp, #20]
-; VBITS_GE_1024-NEXT:    sbfx w12, w9, #7, #1
-; VBITS_GE_1024-NEXT:    strh w10, [sp, #18]
-; VBITS_GE_1024-NEXT:    sbfx w10, w9, #6, #1
-; VBITS_GE_1024-NEXT:    strh w11, [sp, #16]
-; VBITS_GE_1024-NEXT:    sbfx w11, w9, #5, #1
-; VBITS_GE_1024-NEXT:    strh w12, [sp, #14]
-; VBITS_GE_1024-NEXT:    sbfx w12, w9, #4, #1
-; VBITS_GE_1024-NEXT:    strh w10, [sp, #12]
-; VBITS_GE_1024-NEXT:    sbfx w10, w9, #3, #1
-; VBITS_GE_1024-NEXT:    strh w11, [sp, #10]
-; VBITS_GE_1024-NEXT:    sbfx w11, w9, #2, #1
-; VBITS_GE_1024-NEXT:    strh w12, [sp, #8]
-; VBITS_GE_1024-NEXT:    sbfx w12, w9, #1, #1
-; VBITS_GE_1024-NEXT:    sbfx w9, w9, #0, #1
-; VBITS_GE_1024-NEXT:    strh w10, [sp, #6]
-; VBITS_GE_1024-NEXT:    strh w11, [sp, #4]
-; VBITS_GE_1024-NEXT:    strh w12, [sp, #2]
-; VBITS_GE_1024-NEXT:    strh w9, [sp]
-; VBITS_GE_1024-NEXT:    ld1h { z0.h }, p0/z, [x8]
+; VBITS_GE_1024-NEXT:    asr x9, x8, #63
+; VBITS_GE_1024-NEXT:    sbfx x10, x8, #62, #1
+; VBITS_GE_1024-NEXT:    sbfx x11, x8, #61, #1
+; VBITS_GE_1024-NEXT:    strh w9, [sp, #126]
+; VBITS_GE_1024-NEXT:    sbfx x9, x8, #60, #1
+; VBITS_GE_1024-NEXT:    strh w10, [sp, #124]
+; VBITS_GE_1024-NEXT:    sbfx x10, x8, #59, #1
+; VBITS_GE_1024-NEXT:    strh w11, [sp, #122]
+; VBITS_GE_1024-NEXT:    sbfx x11, x8, #58, #1
+; VBITS_GE_1024-NEXT:    strh w9, [sp, #120]
+; VBITS_GE_1024-NEXT:    sbfx x9, x8, #57, #1
+; VBITS_GE_1024-NEXT:    strh w10, [sp, #118]
+; VBITS_GE_1024-NEXT:    sbfx x10, x8, #56, #1
+; VBITS_GE_1024-NEXT:    strh w11, [sp, #116]
+; VBITS_GE_1024-NEXT:    sbfx x11, x8, #55, #1
+; VBITS_GE_1024-NEXT:    strh w9, [sp, #114]
+; VBITS_GE_1024-NEXT:    sbfx x9, x8, #54, #1
+; VBITS_GE_1024-NEXT:    strh w10, [sp, #112]
+; VBITS_GE_1024-NEXT:    sbfx x10, x8, #53, #1
+; VBITS_GE_1024-NEXT:    strh w11, [sp, #110]
+; VBITS_GE_1024-NEXT:    sbfx x11, x8, #52, #1
+; VBITS_GE_1024-NEXT:    strh w9, [sp, #108]
+; VBITS_GE_1024-NEXT:    sbfx x9, x8, #51, #1
+; VBITS_GE_1024-NEXT:    strh w10, [sp, #106]
+; VBITS_GE_1024-NEXT:    sbfx x10, x8, #50, #1
+; VBITS_GE_1024-NEXT:    strh w11, [sp, #104]
+; VBITS_GE_1024-NEXT:    sbfx x11, x8, #49, #1
+; VBITS_GE_1024-NEXT:    strh w9, [sp, #102]
+; VBITS_GE_1024-NEXT:    sbfx x9, x8, #48, #1
+; VBITS_GE_1024-NEXT:    strh w10, [sp, #100]
+; VBITS_GE_1024-NEXT:    sbfx x10, x8, #47, #1
+; VBITS_GE_1024-NEXT:    strh w11, [sp, #98]
+; VBITS_GE_1024-NEXT:    sbfx x11, x8, #46, #1
+; VBITS_GE_1024-NEXT:    strh w9, [sp, #96]
+; VBITS_GE_1024-NEXT:    sbfx x9, x8, #45, #1
+; VBITS_GE_1024-NEXT:    strh w10, [sp, #94]
+; VBITS_GE_1024-NEXT:    sbfx x10, x8, #44, #1
+; VBITS_GE_1024-NEXT:    strh w11, [sp, #92]
+; VBITS_GE_1024-NEXT:    sbfx x11, x8, #43, #1
+; VBITS_GE_1024-NEXT:    strh w9, [sp, #90]
+; VBITS_GE_1024-NEXT:    sbfx x9, x8, #42, #1
+; VBITS_GE_1024-NEXT:    strh w10, [sp, #88]
+; VBITS_GE_1024-NEXT:    sbfx x10, x8, #41, #1
+; VBITS_GE_1024-NEXT:    strh w11, [sp, #86]
+; VBITS_GE_1024-NEXT:    sbfx x11, x8, #40, #1
+; VBITS_GE_1024-NEXT:    strh w9, [sp, #84]
+; VBITS_GE_1024-NEXT:    sbfx x9, x8, #39, #1
+; VBITS_GE_1024-NEXT:    strh w10, [sp, #82]
+; VBITS_GE_1024-NEXT:    sbfx x10, x8, #38, #1
+; VBITS_GE_1024-NEXT:    strh w11, [sp, #80]
+; VBITS_GE_1024-NEXT:    sbfx x11, x8, #37, #1
+; VBITS_GE_1024-NEXT:    strh w9, [sp, #78]
+; VBITS_GE_1024-NEXT:    sbfx x9, x8, #36, #1
+; VBITS_GE_1024-NEXT:    strh w10, [sp, #76]
+; VBITS_GE_1024-NEXT:    sbfx x10, x8, #35, #1
+; VBITS_GE_1024-NEXT:    strh w11, [sp, #74]
+; VBITS_GE_1024-NEXT:    sbfx x11, x8, #34, #1
+; VBITS_GE_1024-NEXT:    strh w9, [sp, #72]
+; VBITS_GE_1024-NEXT:    sbfx x9, x8, #33, #1
+; VBITS_GE_1024-NEXT:    strh w10, [sp, #70]
+; VBITS_GE_1024-NEXT:    sbfx x10, x8, #32, #1
+; VBITS_GE_1024-NEXT:    strh w11, [sp, #68]
+; VBITS_GE_1024-NEXT:    asr w11, w8, #31
+; VBITS_GE_1024-NEXT:    strh w9, [sp, #66]
+; VBITS_GE_1024-NEXT:    sbfx w9, w8, #30, #1
+; VBITS_GE_1024-NEXT:    strh w10, [sp, #64]
+; VBITS_GE_1024-NEXT:    sbfx w10, w8, #29, #1
+; VBITS_GE_1024-NEXT:    strh w11, [sp, #62]
+; VBITS_GE_1024-NEXT:    sbfx w11, w8, #28, #1
+; VBITS_GE_1024-NEXT:    strh w9, [sp, #60]
+; VBITS_GE_1024-NEXT:    sbfx w9, w8, #27, #1
+; VBITS_GE_1024-NEXT:    strh w10, [sp, #58]
+; VBITS_GE_1024-NEXT:    sbfx w10, w8, #26, #1
+; VBITS_GE_1024-NEXT:    strh w11, [sp, #56]
+; VBITS_GE_1024-NEXT:    sbfx w11, w8, #25, #1
+; VBITS_GE_1024-NEXT:    strh w9, [sp, #54]
+; VBITS_GE_1024-NEXT:    sbfx w9, w8, #24, #1
+; VBITS_GE_1024-NEXT:    strh w10, [sp, #52]
+; VBITS_GE_1024-NEXT:    sbfx w10, w8, #23, #1
+; VBITS_GE_1024-NEXT:    strh w11, [sp, #50]
+; VBITS_GE_1024-NEXT:    sbfx w11, w8, #22, #1
+; VBITS_GE_1024-NEXT:    strh w9, [sp, #48]
+; VBITS_GE_1024-NEXT:    sbfx w9, w8, #21, #1
+; VBITS_GE_1024-NEXT:    strh w10, [sp, #46]
+; VBITS_GE_1024-NEXT:    sbfx w10, w8, #20, #1
+; VBITS_GE_1024-NEXT:    strh w11, [sp, #44]
+; VBITS_GE_1024-NEXT:    sbfx w11, w8, #19, #1
+; VBITS_GE_1024-NEXT:    strh w9, [sp, #42]
+; VBITS_GE_1024-NEXT:    sbfx w9, w8, #18, #1
+; VBITS_GE_1024-NEXT:    strh w10, [sp, #40]
+; VBITS_GE_1024-NEXT:    sbfx w10, w8, #17, #1
+; VBITS_GE_1024-NEXT:    strh w11, [sp, #38]
+; VBITS_GE_1024-NEXT:    sbfx w11, w8, #16, #1
+; VBITS_GE_1024-NEXT:    strh w9, [sp, #36]
+; VBITS_GE_1024-NEXT:    sbfx w9, w8, #15, #1
+; VBITS_GE_1024-NEXT:    strh w10, [sp, #34]
+; VBITS_GE_1024-NEXT:    sbfx w10, w8, #14, #1
+; VBITS_GE_1024-NEXT:    strh w11, [sp, #32]
+; VBITS_GE_1024-NEXT:    sbfx w11, w8, #13, #1
+; VBITS_GE_1024-NEXT:    strh w9, [sp, #30]
+; VBITS_GE_1024-NEXT:    sbfx w9, w8, #12, #1
+; VBITS_GE_1024-NEXT:    strh w10, [sp, #28]
+; VBITS_GE_1024-NEXT:    sbfx w10, w8, #11, #1
+; VBITS_GE_1024-NEXT:    strh w11, [sp, #26]
+; VBITS_GE_1024-NEXT:    sbfx w11, w8, #10, #1
+; VBITS_GE_1024-NEXT:    strh w9, [sp, #24]
+; VBITS_GE_1024-NEXT:    sbfx w9, w8, #9, #1
+; VBITS_GE_1024-NEXT:    strh w10, [sp, #22]
+; VBITS_GE_1024-NEXT:    sbfx w10, w8, #8, #1
+; VBITS_GE_1024-NEXT:    strh w11, [sp, #20]
+; VBITS_GE_1024-NEXT:    sbfx w11, w8, #7, #1
+; VBITS_GE_1024-NEXT:    strh w9, [sp, #18]
+; VBITS_GE_1024-NEXT:    sbfx w9, w8, #6, #1
+; VBITS_GE_1024-NEXT:    strh w10, [sp, #16]
+; VBITS_GE_1024-NEXT:    sbfx w10, w8, #5, #1
+; VBITS_GE_1024-NEXT:    strh w11, [sp, #14]
+; VBITS_GE_1024-NEXT:    sbfx w11, w8, #4, #1
+; VBITS_GE_1024-NEXT:    strh w9, [sp, #12]
+; VBITS_GE_1024-NEXT:    sbfx w9, w8, #3, #1
+; VBITS_GE_1024-NEXT:    strh w10, [sp, #10]
+; VBITS_GE_1024-NEXT:    sbfx w10, w8, #2, #1
+; VBITS_GE_1024-NEXT:    strh w11, [sp, #8]
+; VBITS_GE_1024-NEXT:    sbfx w11, w8, #1, #1
+; VBITS_GE_1024-NEXT:    sbfx w8, w8, #0, #1
+; VBITS_GE_1024-NEXT:    strh w9, [sp, #6]
+; VBITS_GE_1024-NEXT:    strh w10, [sp, #4]
+; VBITS_GE_1024-NEXT:    strh w11, [sp, #2]
+; VBITS_GE_1024-NEXT:    strh w8, [sp]
+; VBITS_GE_1024-NEXT:    ld1h { z0.h }, p0/z, [sp]
 ; VBITS_GE_1024-NEXT:    ld1h { z1.h }, p0/z, [x0]
 ; VBITS_GE_1024-NEXT:    ld1h { z2.h }, p0/z, [x1]
 ; VBITS_GE_1024-NEXT:    and z0.h, z0.h, #0x1
 ; VBITS_GE_1024-NEXT:    cmpne p1.h, p1/z, z0.h, #0
 ; VBITS_GE_1024-NEXT:    sel z0.h, p1, z1.h, z2.h
 ; VBITS_GE_1024-NEXT:    st1h { z0.h }, p0, [x0]
 ; VBITS_GE_1024-NEXT:    mov sp, x29
 ; VBITS_GE_1024-NEXT:    ldp x29, x30, [sp], #16 // 16-byte Folded Reload

 ; VBITS_GE_2048:       // %bb.0:
 ; VBITS_GE_2048-NEXT:    stp x29, x30, [sp, #-16]! // 16-byte Folded Spill
 ; VBITS_GE_2048-NEXT:    sub x9, sp, #496
 ; VBITS_GE_2048-NEXT:    mov x29, sp
 ; VBITS_GE_2048-NEXT:    and sp, x9, #0xffffffffffffff00
 ; VBITS_GE_2048-NEXT:    .cfi_def_cfa w29, 16
 ; VBITS_GE_2048-NEXT:    .cfi_offset w30, -8
 ; VBITS_GE_2048-NEXT:    .cfi_offset w29, -16
-; VBITS_GE_2048-NEXT:    ldr x9, [x2, #8]
-; VBITS_GE_2048-NEXT:    mov x8, sp
+; VBITS_GE_2048-NEXT:    ldr x8, [x2, #8]
 ; VBITS_GE_2048-NEXT:    ptrue p0.h, vl128
 ; VBITS_GE_2048-NEXT:    ptrue p1.h
-; VBITS_GE_2048-NEXT:    asr x10, x9, #63
-; VBITS_GE_2048-NEXT:    sbfx x11, x9, #62, #1
-; VBITS_GE_2048-NEXT:    sbfx x12, x9, #61, #1
-; VBITS_GE_2048-NEXT:    strh w10, [sp, #254]
-; VBITS_GE_2048-NEXT:    sbfx x10, x9, #60, #1
-; VBITS_GE_2048-NEXT:    strh w11, [sp, #252]
-; VBITS_GE_2048-NEXT:    sbfx x11, x9, #59, #1
-; VBITS_GE_2048-NEXT:    strh w12, [sp, #250]
-; VBITS_GE_2048-NEXT:    sbfx x12, x9, #58, #1
-; VBITS_GE_2048-NEXT:    strh w10, [sp, #248]
-; VBITS_GE_2048-NEXT:    sbfx x10, x9, #57, #1
-; VBITS_GE_2048-NEXT:    strh w11, [sp, #246]
-; VBITS_GE_2048-NEXT:    sbfx x11, x9, #56, #1
-; VBITS_GE_2048-NEXT:    strh w12, [sp, #244]
-; VBITS_GE_2048-NEXT:    sbfx x12, x9, #55, #1
-; VBITS_GE_2048-NEXT:    strh w10, [sp, #242]
-; VBITS_GE_2048-NEXT:    sbfx x10, x9, #54, #1
-; VBITS_GE_2048-NEXT:    strh w11, [sp, #240]
-; VBITS_GE_2048-NEXT:    sbfx x11, x9, #53, #1
-; VBITS_GE_2048-NEXT:    strh w12, [sp, #238]
-; VBITS_GE_2048-NEXT:    sbfx x12, x9, #52, #1
-; VBITS_GE_2048-NEXT:    strh w10, [sp, #236]
-; VBITS_GE_2048-NEXT:    sbfx x10, x9, #51, #1
-; VBITS_GE_2048-NEXT:    strh w11, [sp, #234]
-; VBITS_GE_2048-NEXT:    sbfx x11, x9, #50, #1
-; VBITS_GE_2048-NEXT:    strh w12, [sp, #232]
-; VBITS_GE_2048-NEXT:    sbfx x12, x9, #49, #1
-; VBITS_GE_2048-NEXT:    strh w10, [sp, #230]
-; VBITS_GE_2048-NEXT:    sbfx x10, x9, #48, #1
-; VBITS_GE_2048-NEXT:    strh w11, [sp, #228]
-; VBITS_GE_2048-NEXT:    sbfx x11, x9, #47, #1
-; VBITS_GE_2048-NEXT:    strh w12, [sp, #226]
-; VBITS_GE_2048-NEXT:    sbfx x12, x9, #46, #1
-; VBITS_GE_2048-NEXT:    strh w10, [sp, #224]
-; VBITS_GE_2048-NEXT:    sbfx x10, x9, #45, #1
-; VBITS_GE_2048-NEXT:    strh w11, [sp, #222]
-; VBITS_GE_2048-NEXT:    sbfx x11, x9, #44, #1
-; VBITS_GE_2048-NEXT:    strh w12, [sp, #220]
-; VBITS_GE_2048-NEXT:    sbfx x12, x9, #43, #1
-; VBITS_GE_2048-NEXT:    strh w10, [sp, #218]
-; VBITS_GE_2048-NEXT:    sbfx x10, x9, #42, #1
-; VBITS_GE_2048-NEXT:    strh w11, [sp, #216]
-; VBITS_GE_2048-NEXT:    sbfx x11, x9, #41, #1
-; VBITS_GE_2048-NEXT:    strh w12, [sp, #214]
-; VBITS_GE_2048-NEXT:    sbfx x12, x9, #40, #1
-; VBITS_GE_2048-NEXT:    strh w10, [sp, #212]
-; VBITS_GE_2048-NEXT:    sbfx x10, x9, #39, #1
-; VBITS_GE_2048-NEXT:    strh w11, [sp, #210]
-; VBITS_GE_2048-NEXT:    sbfx x11, x9, #38, #1
-; VBITS_GE_2048-NEXT:    strh w12, [sp, #208]
-; VBITS_GE_2048-NEXT:    sbfx x12, x9, #37, #1
-; VBITS_GE_2048-NEXT:    strh w10, [sp, #206]
-; VBITS_GE_2048-NEXT:    sbfx x10, x9, #36, #1
-; VBITS_GE_2048-NEXT:    strh w11, [sp, #204]
-; VBITS_GE_2048-NEXT:    sbfx x11, x9, #35, #1
-; VBITS_GE_2048-NEXT:    strh w12, [sp, #202]
-; VBITS_GE_2048-NEXT:    sbfx x12, x9, #34, #1
-; VBITS_GE_2048-NEXT:    strh w10, [sp, #200]
-; VBITS_GE_2048-NEXT:    sbfx x10, x9, #33, #1
-; VBITS_GE_2048-NEXT:    strh w11, [sp, #198]
-; VBITS_GE_2048-NEXT:    sbfx x11, x9, #32, #1
-; VBITS_GE_2048-NEXT:    strh w12, [sp, #196]
-; VBITS_GE_2048-NEXT:    asr w12, w9, #31
-; VBITS_GE_2048-NEXT:    strh w10, [sp, #194]
-; VBITS_GE_2048-NEXT:    sbfx w10, w9, #30, #1
-; VBITS_GE_2048-NEXT:    strh w11, [sp, #192]
-; VBITS_GE_2048-NEXT:    sbfx w11, w9, #29, #1
-; VBITS_GE_2048-NEXT:    strh w12, [sp, #190]
-; VBITS_GE_2048-NEXT:    sbfx w12, w9, #28, #1
-; VBITS_GE_2048-NEXT:    strh w10, [sp, #188]
-; VBITS_GE_2048-NEXT:    sbfx w10, w9, #27, #1
-; VBITS_GE_2048-NEXT:    strh w11, [sp, #186]
-; VBITS_GE_2048-NEXT:    sbfx w11, w9, #26, #1
-; VBITS_GE_2048-NEXT:    strh w12, [sp, #184]
-; VBITS_GE_2048-NEXT:    sbfx w12, w9, #25, #1
-; VBITS_GE_2048-NEXT:    strh w10, [sp, #182]
-; VBITS_GE_2048-NEXT:    sbfx w10, w9, #24, #1
-; VBITS_GE_2048-NEXT:    strh w11, [sp, #180]
-; VBITS_GE_2048-NEXT:    sbfx w11, w9, #23, #1
-; VBITS_GE_2048-NEXT:    strh w12, [sp, #178]
-; VBITS_GE_2048-NEXT:    sbfx w12, w9, #22, #1
-; VBITS_GE_2048-NEXT:    strh w10, [sp, #176]
-; VBITS_GE_2048-NEXT:    sbfx w10, w9, #21, #1
-; VBITS_GE_2048-NEXT:    strh w11, [sp, #174]
-; VBITS_GE_2048-NEXT:    sbfx w11, w9, #20, #1
-; VBITS_GE_2048-NEXT:    strh w12, [sp, #172]
-; VBITS_GE_2048-NEXT:    sbfx w12, w9, #19, #1
-; VBITS_GE_2048-NEXT:    strh w10, [sp, #170]
-; VBITS_GE_2048-NEXT:    sbfx w10, w9, #18, #1
-; VBITS_GE_2048-NEXT:    strh w11, [sp, #168]
-; VBITS_GE_2048-NEXT:    sbfx w11, w9, #17, #1
-; VBITS_GE_2048-NEXT:    strh w12, [sp, #166]
-; VBITS_GE_2048-NEXT:    sbfx w12, w9, #16, #1
-; VBITS_GE_2048-NEXT:    strh w10, [sp, #164]
-; VBITS_GE_2048-NEXT:    sbfx w10, w9, #15, #1
-; VBITS_GE_2048-NEXT:    strh w11, [sp, #162]
-; VBITS_GE_2048-NEXT:    sbfx w11, w9, #14, #1
-; VBITS_GE_2048-NEXT:    strh w12, [sp, #160]
-; VBITS_GE_2048-NEXT:    sbfx w12, w9, #13, #1
-; VBITS_GE_2048-NEXT:    strh w10, [sp, #158]
-; VBITS_GE_2048-NEXT:    sbfx w10, w9, #12, #1
-; VBITS_GE_2048-NEXT:    strh w11, [sp, #156]
-; VBITS_GE_2048-NEXT:    sbfx w11, w9, #11, #1
-; VBITS_GE_2048-NEXT:    strh w12, [sp, #154]
-; VBITS_GE_2048-NEXT:    sbfx w12, w9, #10, #1
-; VBITS_GE_2048-NEXT:    strh w10, [sp, #152]
-; VBITS_GE_2048-NEXT:    sbfx w10, w9, #9, #1
-; VBITS_GE_2048-NEXT:    strh w11, [sp, #150]
-; VBITS_GE_2048-NEXT:    sbfx w11, w9, #8, #1
-; VBITS_GE_2048-NEXT:    strh w12, [sp, #148]
-; VBITS_GE_2048-NEXT:    sbfx w12, w9, #7, #1
-; VBITS_GE_2048-NEXT:    strh w10, [sp, #146]
-; VBITS_GE_2048-NEXT:    sbfx w10, w9, #6, #1
-; VBITS_GE_2048-NEXT:    strh w11, [sp, #144]
-; VBITS_GE_2048-NEXT:    sbfx w11, w9, #5, #1
-; VBITS_GE_2048-NEXT:    strh w12, [sp, #142]
-; VBITS_GE_2048-NEXT:    sbfx w12, w9, #4, #1
-; VBITS_GE_2048-NEXT:    strh w10, [sp, #140]
-; VBITS_GE_2048-NEXT:    sbfx w10, w9, #3, #1
-; VBITS_GE_2048-NEXT:    strh w11, [sp, #138]
-; VBITS_GE_2048-NEXT:    sbfx w11, w9, #2, #1
-; VBITS_GE_2048-NEXT:    strh w12, [sp, #136]
-; VBITS_GE_2048-NEXT:    sbfx w12, w9, #1, #1
-; VBITS_GE_2048-NEXT:    sbfx w9, w9, #0, #1
-; VBITS_GE_2048-NEXT:    strh w10, [sp, #134]
-; VBITS_GE_2048-NEXT:    strh w11, [sp, #132]
-; VBITS_GE_2048-NEXT:    strh w12, [sp, #130]
-; VBITS_GE_2048-NEXT:    strh w9, [sp, #128]
-; VBITS_GE_2048-NEXT:    ldr x9, [x2]
-; VBITS_GE_2048-NEXT:    asr x10, x9, #63
-; VBITS_GE_2048-NEXT:    sbfx x11, x9, #62, #1
-; VBITS_GE_2048-NEXT:    sbfx x12, x9, #61, #1
-; VBITS_GE_2048-NEXT:    strh w10, [sp, #126]
-; VBITS_GE_2048-NEXT:    sbfx x10, x9, #60, #1
-; VBITS_GE_2048-NEXT:    strh w11, [sp, #124]
-; VBITS_GE_2048-NEXT:    sbfx x11, x9, #59, #1
-; VBITS_GE_2048-NEXT:    strh w12, [sp, #122]
-; VBITS_GE_2048-NEXT:    sbfx x12, x9, #58, #1
-; VBITS_GE_2048-NEXT:    strh w10, [sp, #120]
-; VBITS_GE_2048-NEXT:    sbfx x10, x9, #57, #1
-; VBITS_GE_2048-NEXT:    strh w11, [sp, #118]
-; VBITS_GE_2048-NEXT:    sbfx x11, x9, #56, #1
-; VBITS_GE_2048-NEXT:    strh w12, [sp, #116]
-; VBITS_GE_2048-NEXT:    sbfx x12, x9, #55, #1
-; VBITS_GE_2048-NEXT:    strh w10, [sp, #114]
-; VBITS_GE_2048-NEXT:    sbfx x10, x9, #54, #1
-; VBITS_GE_2048-NEXT:    strh w11, [sp, #112]
-; VBITS_GE_2048-NEXT:    sbfx x11, x9, #53, #1
-; VBITS_GE_2048-NEXT:    strh w12, [sp, #110]
-; VBITS_GE_2048-NEXT:    sbfx x12, x9, #52, #1
-; VBITS_GE_2048-NEXT:    strh w10, [sp, #108]
-; VBITS_GE_2048-NEXT:    sbfx x10, x9, #51, #1
-; VBITS_GE_2048-NEXT:    strh w11, [sp, #106]
-; VBITS_GE_2048-NEXT:    sbfx x11, x9, #50, #1
-; VBITS_GE_2048-NEXT:    strh w12, [sp, #104]
-; VBITS_GE_2048-NEXT:    sbfx x12, x9, #49, #1
-; VBITS_GE_2048-NEXT:    strh w10, [sp, #102]
-; VBITS_GE_2048-NEXT:    sbfx x10, x9, #48, #1
-; VBITS_GE_2048-NEXT:    strh w11, [sp, #100]
-; VBITS_GE_2048-NEXT:    sbfx x11, x9, #47, #1
-; VBITS_GE_2048-NEXT:    strh w12, [sp, #98]
-; VBITS_GE_2048-NEXT:    sbfx x12, x9, #46, #1
-; VBITS_GE_2048-NEXT:    strh w10, [sp, #96]
-; VBITS_GE_2048-NEXT:    sbfx x10, x9, #45, #1
-; VBITS_GE_2048-NEXT:    strh w11, [sp, #94]
-; VBITS_GE_2048-NEXT:    sbfx x11, x9, #44, #1
-; VBITS_GE_2048-NEXT:    strh w12, [sp, #92]
-; VBITS_GE_2048-NEXT:    sbfx x12, x9, #43, #1
-; VBITS_GE_2048-NEXT:    strh w10, [sp, #90]
-; VBITS_GE_2048-NEXT:    sbfx x10, x9, #42, #1
-; VBITS_GE_2048-NEXT:    strh w11, [sp, #88]
-; VBITS_GE_2048-NEXT:    sbfx x11, x9, #41, #1
-; VBITS_GE_2048-NEXT:    strh w12, [sp, #86]
-; VBITS_GE_2048-NEXT:    sbfx x12, x9, #40, #1
-; VBITS_GE_2048-NEXT:    strh w10, [sp, #84]
-; VBITS_GE_2048-NEXT:    sbfx x10, x9, #39, #1
-; VBITS_GE_2048-NEXT:    strh w11, [sp, #82]
-; VBITS_GE_2048-NEXT:    sbfx x11, x9, #38, #1
-; VBITS_GE_2048-NEXT:    strh w12, [sp, #80]
-; VBITS_GE_2048-NEXT:    sbfx x12, x9, #37, #1
-; VBITS_GE_2048-NEXT:    strh w10, [sp, #78]
-; VBITS_GE_2048-NEXT:    sbfx x10, x9, #36, #1
-; VBITS_GE_2048-NEXT:    strh w11, [sp, #76]
-; VBITS_GE_2048-NEXT:    sbfx x11, x9, #35, #1
-; VBITS_GE_2048-NEXT:    strh w12, [sp, #74]
-; VBITS_GE_2048-NEXT:    sbfx x12, x9, #34, #1
-; VBITS_GE_2048-NEXT:    strh w10, [sp, #72]
-; VBITS_GE_2048-NEXT:    sbfx x10, x9, #33, #1
-; VBITS_GE_2048-NEXT:    strh w11, [sp, #70]
-; VBITS_GE_2048-NEXT:    sbfx x11, x9, #32, #1
-; VBITS_GE_2048-NEXT:    strh w12, [sp, #68]
-; VBITS_GE_2048-NEXT:    asr w12, w9, #31
-; VBITS_GE_2048-NEXT:    strh w10, [sp, #66]
-; VBITS_GE_2048-NEXT:    sbfx w10, w9, #30, #1
-; VBITS_GE_2048-NEXT:    strh w11, [sp, #64]
-; VBITS_GE_2048-NEXT:    sbfx w11, w9, #29, #1
-; VBITS_GE_2048-NEXT:    strh w12, [sp, #62]
-; VBITS_GE_2048-NEXT:    sbfx w12, w9, #28, #1
-; VBITS_GE_2048-NEXT:    strh w10, [sp, #60]
-; VBITS_GE_2048-NEXT:    sbfx w10, w9, #27, #1
-; VBITS_GE_2048-NEXT:    strh w11, [sp, #58]
-; VBITS_GE_2048-NEXT:    sbfx w11, w9, #26, #1
-; VBITS_GE_2048-NEXT:    strh w12, [sp, #56]
-; VBITS_GE_2048-NEXT:    sbfx w12, w9, #25, #1
-; VBITS_GE_2048-NEXT:    strh w10, [sp, #54]
-; VBITS_GE_2048-NEXT:    sbfx w10, w9, #24, #1
-; VBITS_GE_2048-NEXT:    strh w11, [sp, #52]
-; VBITS_GE_2048-NEXT:    sbfx w11, w9, #23, #1
-; VBITS_GE_2048-NEXT:    strh w12, [sp, #50]
-; VBITS_GE_2048-NEXT:    sbfx w12, w9, #22, #1
-; VBITS_GE_2048-NEXT:    strh w10, [sp, #48]
-; VBITS_GE_2048-NEXT:    sbfx w10, w9, #21, #1
-; VBITS_GE_2048-NEXT:    strh w11, [sp, #46]
-; VBITS_GE_2048-NEXT:    sbfx w11, w9, #20, #1
-; VBITS_GE_2048-NEXT:    strh w12, [sp, #44]
-; VBITS_GE_2048-NEXT:    sbfx w12, w9, #19, #1
-; VBITS_GE_2048-NEXT:    strh w10, [sp, #42]
-; VBITS_GE_2048-NEXT:    sbfx w10, w9, #18, #1
-; VBITS_GE_2048-NEXT:    strh w11, [sp, #40]
-; VBITS_GE_2048-NEXT:    sbfx w11, w9, #17, #1
-; VBITS_GE_2048-NEXT:    strh w12, [sp, #38]
-; VBITS_GE_2048-NEXT:    sbfx w12, w9, #16, #1
-; VBITS_GE_2048-NEXT:    strh w10, [sp, #36]
-; VBITS_GE_2048-NEXT:    sbfx w10, w9, #15, #1
-; VBITS_GE_2048-NEXT:    strh w11, [sp, #34]
-; VBITS_GE_2048-NEXT:    sbfx w11, w9, #14, #1
-; VBITS_GE_2048-NEXT:    strh w12, [sp, #32]
-; VBITS_GE_2048-NEXT:    sbfx w12, w9, #13, #1
-; VBITS_GE_2048-NEXT:    strh w10, [sp, #30]
-; VBITS_GE_2048-NEXT:    sbfx w10, w9, #12, #1
-; VBITS_GE_2048-NEXT:    strh w11, [sp, #28]
-; VBITS_GE_2048-NEXT:    sbfx w11, w9, #11, #1
-; VBITS_GE_2048-NEXT:    strh w12, [sp, #26]
-; VBITS_GE_2048-NEXT:    sbfx w12, w9, #10, #1
-; VBITS_GE_2048-NEXT:    strh w10, [sp, #24]
-; VBITS_GE_2048-NEXT:    sbfx w10, w9, #9, #1
-; VBITS_GE_2048-NEXT:    strh w11, [sp, #22]
-; VBITS_GE_2048-NEXT:    sbfx w11, w9, #8, #1
-; VBITS_GE_2048-NEXT:    strh w12, [sp, #20]
-; VBITS_GE_2048-NEXT:    sbfx w12, w9, #7, #1
-; VBITS_GE_2048-NEXT:    strh w10, [sp, #18]
-; VBITS_GE_2048-NEXT:    sbfx w10, w9, #6, #1
-; VBITS_GE_2048-NEXT:    strh w11, [sp, #16]
-; VBITS_GE_2048-NEXT:    sbfx w11, w9, #5, #1
-; VBITS_GE_2048-NEXT:    strh w12, [sp, #14]
-; VBITS_GE_2048-NEXT:    sbfx w12, w9, #4, #1
-; VBITS_GE_2048-NEXT:    strh w10, [sp, #12]
-; VBITS_GE_2048-NEXT:    sbfx w10, w9, #3, #1
-; VBITS_GE_2048-NEXT:    strh w11, [sp, #10]
-; VBITS_GE_2048-NEXT:    sbfx w11, w9, #2, #1
-; VBITS_GE_2048-NEXT:    strh w12, [sp, #8]
-; VBITS_GE_2048-NEXT:    sbfx w12, w9, #1, #1
-; VBITS_GE_2048-NEXT:    sbfx w9, w9, #0, #1
-; VBITS_GE_2048-NEXT:    strh w10, [sp, #6]
-; VBITS_GE_2048-NEXT:    strh w11, [sp, #4]
-; VBITS_GE_2048-NEXT:    strh w12, [sp, #2]
-; VBITS_GE_2048-NEXT:    strh w9, [sp]
-; VBITS_GE_2048-NEXT:    ld1h { z0.h }, p0/z, [x8]
+; VBITS_GE_2048-NEXT:    asr x9, x8, #63
+; VBITS_GE_2048-NEXT:    sbfx x10, x8, #62, #1
+; VBITS_GE_2048-NEXT:    sbfx x11, x8, #61, #1
+; VBITS_GE_2048-NEXT:    strh w9, [sp, #254]
+; VBITS_GE_2048-NEXT:    sbfx x9, x8, #60, #1
+; VBITS_GE_2048-NEXT:    strh w10, [sp, #252]
+; VBITS_GE_2048-NEXT:    sbfx x10, x8, #59, #1
+; VBITS_GE_2048-NEXT:    strh w11, [sp, #250]
+; VBITS_GE_2048-NEXT:    sbfx x11, x8, #58, #1
+; VBITS_GE_2048-NEXT:    strh w9, [sp, #248]
+; VBITS_GE_2048-NEXT:    sbfx x9, x8, #57, #1
+; VBITS_GE_2048-NEXT:    strh w10, [sp, #246]
+; VBITS_GE_2048-NEXT:    sbfx x10, x8, #56, #1
+; VBITS_GE_2048-NEXT:    strh w11, [sp, #244]
+; VBITS_GE_2048-NEXT:    sbfx x11, x8, #55, #1
+; VBITS_GE_2048-NEXT:    strh w9, [sp, #242]
+; VBITS_GE_2048-NEXT:    sbfx x9, x8, #54, #1
+; VBITS_GE_2048-NEXT:    strh w10, [sp, #240]
+; VBITS_GE_2048-NEXT:    sbfx x10, x8, #53, #1
+; VBITS_GE_2048-NEXT:    strh w11, [sp, #238]
+; VBITS_GE_2048-NEXT:    sbfx x11, x8, #52, #1
+; VBITS_GE_2048-NEXT:    strh w9, [sp, #236]
+; VBITS_GE_2048-NEXT:    sbfx x9, x8, #51, #1
+; VBITS_GE_2048-NEXT:    strh w10, [sp, #234]
+; VBITS_GE_2048-NEXT:    sbfx x10, x8, #50, #1
+; VBITS_GE_2048-NEXT:    strh w11, [sp, #232]
+; VBITS_GE_2048-NEXT:    sbfx x11, x8, #49, #1
+; VBITS_GE_2048-NEXT:    strh w9, [sp, #230]
+; VBITS_GE_2048-NEXT:    sbfx x9, x8, #48, #1
+; VBITS_GE_2048-NEXT:    strh w10, [sp, #228]
+; VBITS_GE_2048-NEXT:    sbfx x10, x8, #47, #1
+; VBITS_GE_2048-NEXT:    strh w11, [sp, #226]
+; VBITS_GE_2048-NEXT:    sbfx x11, x8, #46, #1
+; VBITS_GE_2048-NEXT:    strh w9, [sp, #224]
+; VBITS_GE_2048-NEXT:    sbfx x9, x8, #45, #1
+; VBITS_GE_2048-NEXT:    strh w10, [sp, #222]
+; VBITS_GE_2048-NEXT:    sbfx x10, x8, #44, #1
+; VBITS_GE_2048-NEXT:    strh w11, [sp, #220]
+; VBITS_GE_2048-NEXT:    sbfx x11, x8, #43, #1
+; VBITS_GE_2048-NEXT:    strh w9, [sp, #218]
+; VBITS_GE_2048-NEXT:    sbfx x9, x8, #42, #1
+; VBITS_GE_2048-NEXT:    strh w10, [sp, #216]
+; VBITS_GE_2048-NEXT:    sbfx x10, x8, #41, #1
+; VBITS_GE_2048-NEXT:    strh w11, [sp, #214]
+; VBITS_GE_2048-NEXT:    sbfx x11, x8, #40, #1
+; VBITS_GE_2048-NEXT:    strh w9, [sp, #212]
+; VBITS_GE_2048-NEXT:    sbfx x9, x8, #39, #1
+; VBITS_GE_2048-NEXT:    strh w10, [sp, #210]
+; VBITS_GE_2048-NEXT:    sbfx x10, x8, #38, #1
+; VBITS_GE_2048-NEXT:    strh w11, [sp, #208]
+; VBITS_GE_2048-NEXT:    sbfx x11, x8, #37, #1
+; VBITS_GE_2048-NEXT:    strh w9, [sp, #206]
+; VBITS_GE_2048-NEXT:    sbfx x9, x8, #36, #1
+; VBITS_GE_2048-NEXT:    strh w10, [sp, #204]
+; VBITS_GE_2048-NEXT:    sbfx x10, x8, #35, #1
+; VBITS_GE_2048-NEXT:    strh w11, [sp, #202]
+; VBITS_GE_2048-NEXT:    sbfx x11, x8, #34, #1
+; VBITS_GE_2048-NEXT:    strh w9, [sp, #200]
+; VBITS_GE_2048-NEXT:    sbfx x9, x8, #33, #1
+; VBITS_GE_2048-NEXT:    strh w10, [sp, #198]
+; VBITS_GE_2048-NEXT:    sbfx x10, x8, #32, #1
+; VBITS_GE_2048-NEXT:    strh w11, [sp, #196]
+; VBITS_GE_2048-NEXT:    asr w11, w8, #31
+; VBITS_GE_2048-NEXT:    strh w9, [sp, #194]
+; VBITS_GE_2048-NEXT:    sbfx w9, w8, #30, #1
+; VBITS_GE_2048-NEXT:    strh w10, [sp, #192]
+; VBITS_GE_2048-NEXT:    sbfx w10, w8, #29, #1
+; VBITS_GE_2048-NEXT:    strh w11, [sp, #190]
+; VBITS_GE_2048-NEXT:    sbfx w11, w8, #28, #1
+; VBITS_GE_2048-NEXT:    strh w9, [sp, #188]
+; VBITS_GE_2048-NEXT:    sbfx w9, w8, #27, #1
+; VBITS_GE_2048-NEXT:    strh w10, [sp, #186]
+; VBITS_GE_2048-NEXT:    sbfx w10, w8, #26, #1
+; VBITS_GE_2048-NEXT:    strh w11, [sp, #184]
+; VBITS_GE_2048-NEXT:    sbfx w11, w8, #25, #1
+; VBITS_GE_2048-NEXT:    strh w9, [sp, #182]
+; VBITS_GE_2048-NEXT:    sbfx w9, w8, #24, #1
+; VBITS_GE_2048-NEXT:    strh w10, [sp, #180]
+; VBITS_GE_2048-NEXT:    sbfx w10, w8, #23, #1
+; VBITS_GE_2048-NEXT:    strh w11, [sp, #178]
+; VBITS_GE_2048-NEXT:    sbfx w11, w8, #22, #1
+; VBITS_GE_2048-NEXT:    strh w9, [sp, #176]
+; VBITS_GE_2048-NEXT:    sbfx w9, w8, #21, #1
+; VBITS_GE_2048-NEXT:    strh w10, [sp, #174]
+; VBITS_GE_2048-NEXT:    sbfx w10, w8, #20, #1
+; VBITS_GE_2048-NEXT:    strh w11, [sp, #172]
+; VBITS_GE_2048-NEXT:    sbfx w11, w8, #19, #1
+; VBITS_GE_2048-NEXT:    strh w9, [sp, #170]
+; VBITS_GE_2048-NEXT:    sbfx w9, w8, #18, #1
+; VBITS_GE_2048-NEXT:    strh w10, [sp, #168]
+; VBITS_GE_2048-NEXT:    sbfx w10, w8, #17, #1
+; VBITS_GE_2048-NEXT:    strh w11, [sp, #166]
+; VBITS_GE_2048-NEXT:    sbfx w11, w8, #16, #1
+; VBITS_GE_2048-NEXT:    strh w9, [sp, #164]
+; VBITS_GE_2048-NEXT:    sbfx w9, w8, #15, #1
+; VBITS_GE_2048-NEXT:    strh w10, [sp, #162]
+; VBITS_GE_2048-NEXT:    sbfx w10, w8, #14, #1
+; VBITS_GE_2048-NEXT:    strh w11, [sp, #160]
+; VBITS_GE_2048-NEXT:    sbfx w11, w8, #13, #1
+; VBITS_GE_2048-NEXT:    strh w9, [sp, #158]
+; VBITS_GE_2048-NEXT:    sbfx w9, w8, #12, #1
+; VBITS_GE_2048-NEXT:    strh w10, [sp, #156]
+; VBITS_GE_2048-NEXT:    sbfx w10, w8, #11, #1
+; VBITS_GE_2048-NEXT:    strh w11, [sp, #154]
+; VBITS_GE_2048-NEXT:    sbfx w11, w8, #10, #1
+; VBITS_GE_2048-NEXT:    strh w9, [sp, #152]
+; VBITS_GE_2048-NEXT:    sbfx w9, w8, #9, #1
+; VBITS_GE_2048-NEXT:    strh w10, [sp, #150]
+; VBITS_GE_2048-NEXT:    sbfx w10, w8, #8, #1
+; VBITS_GE_2048-NEXT:    strh w11, [sp, #148]
+; VBITS_GE_2048-NEXT:    sbfx w11, w8, #7, #1
+; VBITS_GE_2048-NEXT:    strh w9, [sp, #146]
+; VBITS_GE_2048-NEXT:    sbfx w9, w8, #6, #1
+; VBITS_GE_2048-NEXT:    strh w10, [sp, #144]
+; VBITS_GE_2048-NEXT:    sbfx w10, w8, #5, #1
+; VBITS_GE_2048-NEXT:    strh w11, [sp, #142]
+; VBITS_GE_2048-NEXT:    sbfx w11, w8, #4, #1
+; VBITS_GE_2048-NEXT:    strh w9, [sp, #140]
+; VBITS_GE_2048-NEXT:    sbfx w9, w8, #3, #1
+; VBITS_GE_2048-NEXT:    strh w10, [sp, #138]
+; VBITS_GE_2048-NEXT:    sbfx w10, w8, #2, #1
+; VBITS_GE_2048-NEXT:    strh w11, [sp, #136]
+; VBITS_GE_2048-NEXT:    sbfx w11, w8, #1, #1
+; VBITS_GE_2048-NEXT:    sbfx w8, w8, #0, #1
+; VBITS_GE_2048-NEXT:    strh w9, [sp, #134]
+; VBITS_GE_2048-NEXT:    strh w10, [sp, #132]
+; VBITS_GE_2048-NEXT:    strh w11, [sp, #130]
+; VBITS_GE_2048-NEXT:    strh w8, [sp, #128]
+; VBITS_GE_2048-NEXT:    ldr x8, [x2]
+; VBITS_GE_2048-NEXT:    asr x9, x8, #63
+; VBITS_GE_2048-NEXT:    sbfx x10, x8, #62, #1
+; VBITS_GE_2048-NEXT:    sbfx x11, x8, #61, #1
+; VBITS_GE_2048-NEXT:    strh w9, [sp, #126]
+; VBITS_GE_2048-NEXT:    sbfx x9, x8, #60, #1
+; VBITS_GE_2048-NEXT:    strh w10, [sp, #124]
+; VBITS_GE_2048-NEXT:    sbfx x10, x8, #59, #1
+; VBITS_GE_2048-NEXT:    strh w11, [sp, #122]
+; VBITS_GE_2048-NEXT:    sbfx x11, x8, #58, #1
+; VBITS_GE_2048-NEXT:    strh w9, [sp, #120]
+; VBITS_GE_2048-NEXT:    sbfx x9, x8, #57, #1
+; VBITS_GE_2048-NEXT:    strh w10, [sp, #118]
+; VBITS_GE_2048-NEXT:    sbfx x10, x8, #56, #1
+; VBITS_GE_2048-NEXT:    strh w11, [sp, #116]
+; VBITS_GE_2048-NEXT:    sbfx x11, x8, #55, #1
+; VBITS_GE_2048-NEXT:    strh w9, [sp, #114]
+; VBITS_GE_2048-NEXT:    sbfx x9, x8, #54, #1
+; VBITS_GE_2048-NEXT:    strh w10, [sp, #112]
+; VBITS_GE_2048-NEXT:    sbfx x10, x8, #53, #1
+; VBITS_GE_2048-NEXT:    strh w11, [sp, #110]
+; VBITS_GE_2048-NEXT:    sbfx x11, x8, #52, #1
+; VBITS_GE_2048-NEXT:    strh w9, [sp, #108]
+; VBITS_GE_2048-NEXT:    sbfx x9, x8, #51, #1
+; VBITS_GE_2048-NEXT:    strh w10, [sp, #106]
+; VBITS_GE_2048-NEXT:    sbfx x10, x8, #50, #1
+; VBITS_GE_2048-NEXT:    strh w11, [sp, #104]
+; VBITS_GE_2048-NEXT:    sbfx x11, x8, #49, #1
+; VBITS_GE_2048-NEXT:    strh w9, [sp, #102]
+; VBITS_GE_2048-NEXT:    sbfx x9, x8, #48, #1
+; VBITS_GE_2048-NEXT:    strh w10, [sp, #100]
+; VBITS_GE_2048-NEXT:    sbfx x10, x8, #47, #1
+; VBITS_GE_2048-NEXT:    strh w11, [sp, #98]
+; VBITS_GE_2048-NEXT:    sbfx x11, x8, #46, #1
+; VBITS_GE_2048-NEXT:    strh w9, [sp, #96]
+; VBITS_GE_2048-NEXT:    sbfx x9, x8, #45, #1
+; VBITS_GE_2048-NEXT:    strh w10, [sp, #94]
+; VBITS_GE_2048-NEXT:    sbfx x10, x8, #44, #1
+; VBITS_GE_2048-NEXT:    strh w11, [sp, #92]
+; VBITS_GE_2048-NEXT:    sbfx x11, x8, #43, #1
+; VBITS_GE_2048-NEXT:    strh w9, [sp, #90]
+; VBITS_GE_2048-NEXT:    sbfx x9, x8, #42, #1
+; VBITS_GE_2048-NEXT:    strh w10, [sp, #88]
+; VBITS_GE_2048-NEXT:    sbfx x10, x8, #41, #1
+; VBITS_GE_2048-NEXT:    strh w11, [sp, #86]
+; VBITS_GE_2048-NEXT:    sbfx x11, x8, #40, #1
+; VBITS_GE_2048-NEXT:    strh w9, [sp, #84]
+; VBITS_GE_2048-NEXT:    sbfx x9, x8, #39, #1
+; VBITS_GE_2048-NEXT:    strh w10, [sp, #82]
+; VBITS_GE_2048-NEXT:    sbfx x10, x8, #38, #1
+; VBITS_GE_2048-NEXT:    strh w11, [sp, #80]
+; VBITS_GE_2048-NEXT:    sbfx x11, x8, #37, #1
+; VBITS_GE_2048-NEXT:    strh w9, [sp, #78]
+; VBITS_GE_2048-NEXT:    sbfx x9, x8, #36, #1
+; VBITS_GE_2048-NEXT:    strh w10, [sp, #76]
+; VBITS_GE_2048-NEXT:    sbfx x10, x8, #35, #1
+; VBITS_GE_2048-NEXT:    strh w11, [sp, #74]
+; VBITS_GE_2048-NEXT:    sbfx x11, x8, #34, #1
+; VBITS_GE_2048-NEXT:    strh w9, [sp, #72]
+; VBITS_GE_2048-NEXT:    sbfx x9, x8, #33, #1
+; VBITS_GE_2048-NEXT:    strh w10, [sp, #70]
+; VBITS_GE_2048-NEXT:    sbfx x10, x8, #32, #1
+; VBITS_GE_2048-NEXT:    strh w11, [sp, #68]
+; VBITS_GE_2048-NEXT:    asr w11, w8, #31
+; VBITS_GE_2048-NEXT:    strh w9, [sp, #66]
+; VBITS_GE_2048-NEXT:    sbfx w9, w8, #30, #1
+; VBITS_GE_2048-NEXT:    strh w10, [sp, #64]
+; VBITS_GE_2048-NEXT:    sbfx w10, w8, #29, #1
+; VBITS_GE_2048-NEXT:    strh w11, [sp, #62]
+; VBITS_GE_2048-NEXT:    sbfx w11, w8, #28, #1
+; VBITS_GE_2048-NEXT:    strh w9, [sp, #60]
+; VBITS_GE_2048-NEXT:    sbfx w9, w8, #27, #1
+; VBITS_GE_2048-NEXT:    strh w10, [sp, #58]
+; VBITS_GE_2048-NEXT:    sbfx w10, w8, #26, #1
+; VBITS_GE_2048-NEXT:    strh w11, [sp, #56]
+; VBITS_GE_2048-NEXT:    sbfx w11, w8, #25, #1
+; VBITS_GE_2048-NEXT:    strh w9, [sp, #54]
+; VBITS_GE_2048-NEXT:    sbfx w9, w8, #24, #1
+; VBITS_GE_2048-NEXT:    strh w10, [sp, #52]
+; VBITS_GE_2048-NEXT:    sbfx w10, w8, #23, #1
+; VBITS_GE_2048-NEXT:    strh w11, [sp, #50]
+; VBITS_GE_2048-NEXT:    sbfx w11, w8, #22, #1
+; VBITS_GE_2048-NEXT:    strh w9, [sp, #48]
+; VBITS_GE_2048-NEXT:    sbfx w9, w8, #21, #1
+; VBITS_GE_2048-NEXT:    strh w10, [sp, #46]
+; VBITS_GE_2048-NEXT:    sbfx w10, w8, #20, #1
+; VBITS_GE_2048-NEXT:    strh w11, [sp, #44]
+; VBITS_GE_2048-NEXT:    sbfx w11, w8, #19, #1
+; VBITS_GE_2048-NEXT:    strh w9, [sp, #42]
+; VBITS_GE_2048-NEXT:    sbfx w9, w8, #18, #1
+; VBITS_GE_2048-NEXT:    strh w10, [sp, #40]
+; VBITS_GE_2048-NEXT:    sbfx w10, w8, #17, #1
+; VBITS_GE_2048-NEXT:    strh w11, [sp, #38]
+; VBITS_GE_2048-NEXT:    sbfx w11, w8, #16, #1
+; VBITS_GE_2048-NEXT:    strh w9, [sp, #36]
+; VBITS_GE_2048-NEXT:    sbfx w9, w8, #15, #1
+; VBITS_GE_2048-NEXT:    strh w10, [sp, #34]
+; VBITS_GE_2048-NEXT:    sbfx w10, w8, #14, #1
+; VBITS_GE_2048-NEXT:    strh w11, [sp, #32]
+; VBITS_GE_2048-NEXT:    sbfx w11, w8, #13, #1
+; VBITS_GE_2048-NEXT:    strh w9, [sp, #30]
+; VBITS_GE_2048-NEXT:    sbfx w9, w8, #12, #1
+; VBITS_GE_2048-NEXT:    strh w10, [sp, #28]
+; VBITS_GE_2048-NEXT:    sbfx w10, w8, #11, #1
+; VBITS_GE_2048-NEXT:    strh w11, [sp, #26]
+; VBITS_GE_2048-NEXT:    sbfx w11, w8, #10, #1
+; VBITS_GE_2048-NEXT:    strh w9, [sp, #24]
+; VBITS_GE_2048-NEXT:    sbfx w9, w8, #9, #1
+; VBITS_GE_2048-NEXT:    strh w10, [sp, #22]
+; VBITS_GE_2048-NEXT:    sbfx w10, w8, #8, #1
+; VBITS_GE_2048-NEXT:    strh w11, [sp, #20]
+; VBITS_GE_2048-NEXT:    sbfx w11, w8, #7, #1
+; VBITS_GE_2048-NEXT:    strh w9, [sp, #18]
+; VBITS_GE_2048-NEXT:    sbfx w9, w8, #6, #1
+; VBITS_GE_2048-NEXT:    strh w10, [sp, #16]
+; VBITS_GE_2048-NEXT:    sbfx w10, w8, #5, #1
+; VBITS_GE_2048-NEXT:    strh w11, [sp, #14]
+; VBITS_GE_2048-NEXT:    sbfx w11, w8, #4, #1
+; VBITS_GE_2048-NEXT:    strh w9, [sp, #12]
+; VBITS_GE_2048-NEXT:    sbfx w9, w8, #3, #1
+; VBITS_GE_2048-NEXT:    strh w10, [sp, #10]
+; VBITS_GE_2048-NEXT:    sbfx w10, w8, #2, #1
+; VBITS_GE_2048-NEXT:    strh w11, [sp, #8]
+; VBITS_GE_2048-NEXT:    sbfx w11, w8, #1, #1
+; VBITS_GE_2048-NEXT:    sbfx w8, w8, #0, #1
+; VBITS_GE_2048-NEXT:    strh w9, [sp, #6]
+; VBITS_GE_2048-NEXT:    strh w10, [sp, #4]
+; VBITS_GE_2048-NEXT:    strh w11, [sp, #2]
+; VBITS_GE_2048-NEXT:    strh w8, [sp]
+; VBITS_GE_2048-NEXT:    ld1h { z0.h }, p0/z, [sp]
 ; VBITS_GE_2048-NEXT:    ld1h { z1.h }, p0/z, [x0]
 ; VBITS_GE_2048-NEXT:    ld1h { z2.h }, p0/z, [x1]
 ; VBITS_GE_2048-NEXT:    and z0.h, z0.h, #0x1
 ; VBITS_GE_2048-NEXT:    cmpne p1.h, p1/z, z0.h, #0
 ; VBITS_GE_2048-NEXT:    sel z0.h, p1, z1.h, z2.h
 ; VBITS_GE_2048-NEXT:    st1h { z0.h }, p0, [x0]
 ; VBITS_GE_2048-NEXT:    mov sp, x29
 ; VBITS_GE_2048-NEXT:    ldp x29, x30, [sp], #16 // 16-byte Folded Reload

 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    stp x29, x30, [sp, #-16]! // 16-byte Folded Spill
 ; CHECK-NEXT:    sub x9, sp, #48
 ; CHECK-NEXT:    mov x29, sp
 ; CHECK-NEXT:    and sp, x9, #0xffffffffffffffe0
 ; CHECK-NEXT:    .cfi_def_cfa w29, 16
 ; CHECK-NEXT:    .cfi_offset w30, -8
 ; CHECK-NEXT:    .cfi_offset w29, -16
-; CHECK-NEXT:    ldrb w9, [x2]
-; CHECK-NEXT:    mov x8, sp
+; CHECK-NEXT:    ldrb w8, [x2]
 ; CHECK-NEXT:    ptrue p0.s, vl8
 ; CHECK-NEXT:    ptrue p1.s
-; CHECK-NEXT:    sbfx w10, w9, #7, #1
-; CHECK-NEXT:    sbfx w11, w9, #6, #1
-; CHECK-NEXT:    sbfx w12, w9, #5, #1
-; CHECK-NEXT:    sbfx w13, w9, #4, #1
-; CHECK-NEXT:    stp w11, w10, [sp, #24]
-; CHECK-NEXT:    sbfx w10, w9, #3, #1
-; CHECK-NEXT:    sbfx w11, w9, #2, #1
-; CHECK-NEXT:    stp w13, w12, [sp, #16]
-; CHECK-NEXT:    sbfx w12, w9, #1, #1
-; CHECK-NEXT:    sbfx w9, w9, #0, #1
-; CHECK-NEXT:    stp w11, w10, [sp, #8]
-; CHECK-NEXT:    stp w9, w12, [sp]
-; CHECK-NEXT:    ld1w { z0.s }, p0/z, [x8]
+; CHECK-NEXT:    sbfx w9, w8, #7, #1
+; CHECK-NEXT:    sbfx w10, w8, #6, #1
+; CHECK-NEXT:    sbfx w11, w8, #5, #1
+; CHECK-NEXT:    sbfx w12, w8, #4, #1
+; CHECK-NEXT:    stp w10, w9, [sp, #24]
+; CHECK-NEXT:    sbfx w9, w8, #3, #1
+; CHECK-NEXT:    sbfx w10, w8, #2, #1
+; CHECK-NEXT:    stp w12, w11, [sp, #16]
+; CHECK-NEXT:    sbfx w11, w8, #1, #1
+; CHECK-NEXT:    sbfx w8, w8, #0, #1
+; CHECK-NEXT:    stp w10, w9, [sp, #8]
+; CHECK-NEXT:    stp w8, w11, [sp]
+; CHECK-NEXT:    ld1w { z0.s }, p0/z, [sp]
 ; CHECK-NEXT:    ld1w { z1.s }, p0/z, [x0]
 ; CHECK-NEXT:    ld1w { z2.s }, p0/z, [x1]
 ; CHECK-NEXT:    and z0.s, z0.s, #0x1
 ; CHECK-NEXT:    cmpne p1.s, p1/z, z0.s, #0
 ; CHECK-NEXT:    sel z0.s, p1, z1.s, z2.s
 ; CHECK-NEXT:    st1w { z0.s }, p0, [x0]
 ; CHECK-NEXT:    mov sp, x29
 ; CHECK-NEXT:    ldp x29, x30, [sp], #16 // 16-byte Folded Reload

 ; VBITS_GE_512:       // %bb.0:
 ; VBITS_GE_512-NEXT:    stp x29, x30, [sp, #-16]! // 16-byte Folded Spill
 ; VBITS_GE_512-NEXT:    sub x9, sp, #112
 ; VBITS_GE_512-NEXT:    mov x29, sp
 ; VBITS_GE_512-NEXT:    and sp, x9, #0xffffffffffffffc0
 ; VBITS_GE_512-NEXT:    .cfi_def_cfa w29, 16
 ; VBITS_GE_512-NEXT:    .cfi_offset w30, -8
 ; VBITS_GE_512-NEXT:    .cfi_offset w29, -16
-; VBITS_GE_512-NEXT:    ldrh w9, [x2]
-; VBITS_GE_512-NEXT:    mov x8, sp
+; VBITS_GE_512-NEXT:    ldrh w8, [x2]
 ; VBITS_GE_512-NEXT:    ptrue p0.s, vl16
 ; VBITS_GE_512-NEXT:    ptrue p1.s
-; VBITS_GE_512-NEXT:    sbfx w10, w9, #15, #1
-; VBITS_GE_512-NEXT:    sbfx w11, w9, #14, #1
-; VBITS_GE_512-NEXT:    sbfx w12, w9, #13, #1
-; VBITS_GE_512-NEXT:    sbfx w13, w9, #12, #1
-; VBITS_GE_512-NEXT:    stp w11, w10, [sp, #56]
-; VBITS_GE_512-NEXT:    sbfx w10, w9, #11, #1
-; VBITS_GE_512-NEXT:    sbfx w11, w9, #10, #1
-; VBITS_GE_512-NEXT:    stp w13, w12, [sp, #48]
-; VBITS_GE_512-NEXT:    sbfx w12, w9, #9, #1
-; VBITS_GE_512-NEXT:    sbfx w13, w9, #8, #1
-; VBITS_GE_512-NEXT:    stp w11, w10, [sp, #40]
-; VBITS_GE_512-NEXT:    sbfx w10, w9, #7, #1
-; VBITS_GE_512-NEXT:    sbfx w11, w9, #6, #1
-; VBITS_GE_512-NEXT:    stp w13, w12, [sp, #32]
-; VBITS_GE_512-NEXT:    sbfx w12, w9, #5, #1
-; VBITS_GE_512-NEXT:    sbfx w13, w9, #4, #1
-; VBITS_GE_512-NEXT:    stp w11, w10, [sp, #24]
-; VBITS_GE_512-NEXT:    sbfx w10, w9, #3, #1
-; VBITS_GE_512-NEXT:    sbfx w11, w9, #2, #1
-; VBITS_GE_512-NEXT:    stp w13, w12, [sp, #16]
-; VBITS_GE_512-NEXT:    sbfx w12, w9, #1, #1
-; VBITS_GE_512-NEXT:    sbfx w9, w9, #0, #1
-; VBITS_GE_512-NEXT:    stp w11, w10, [sp, #8]
-; VBITS_GE_512-NEXT:    stp w9, w12, [sp]
-; VBITS_GE_512-NEXT:    ld1w { z0.s }, p0/z, [x8]
+; VBITS_GE_512-NEXT:    sbfx w9, w8, #15, #1
+; VBITS_GE_512-NEXT:    sbfx w10, w8, #14, #1
+; VBITS_GE_512-NEXT:    sbfx w11, w8, #13, #1
+; VBITS_GE_512-NEXT:    sbfx w12, w8, #12, #1
+; VBITS_GE_512-NEXT:    stp w10, w9, [sp, #56]
+; VBITS_GE_512-NEXT:    sbfx w9, w8, #11, #1
+; VBITS_GE_512-NEXT:    sbfx w10, w8, #10, #1
+; VBITS_GE_512-NEXT:    stp w12, w11, [sp, #48]
+; VBITS_GE_512-NEXT:    sbfx w11, w8, #9, #1
+; VBITS_GE_512-NEXT:    sbfx w12, w8, #8, #1
+; VBITS_GE_512-NEXT:    stp w10, w9, [sp, #40]
+; VBITS_GE_512-NEXT:    sbfx w9, w8, #7, #1
+; VBITS_GE_512-NEXT:    sbfx w10, w8, #6, #1
+; VBITS_GE_512-NEXT:    stp w12, w11, [sp, #32]
+; VBITS_GE_512-NEXT:    sbfx w11, w8, #5, #1
+; VBITS_GE_512-NEXT:    sbfx w12, w8, #4, #1
+; VBITS_GE_512-NEXT:    stp w10, w9, [sp, #24]
+; VBITS_GE_512-NEXT:    sbfx w9, w8, #3, #1
+; VBITS_GE_512-NEXT:    sbfx w10, w8, #2, #1
+; VBITS_GE_512-NEXT:    stp w12, w11, [sp, #16]
+; VBITS_GE_512-NEXT:    sbfx w11, w8, #1, #1
+; VBITS_GE_512-NEXT:    sbfx w8, w8, #0, #1
+; VBITS_GE_512-NEXT:    stp w10, w9, [sp, #8]
+; VBITS_GE_512-NEXT:    stp w8, w11, [sp]
+; VBITS_GE_512-NEXT:    ld1w { z0.s }, p0/z, [sp]
 ; VBITS_GE_512-NEXT:    ld1w { z1.s }, p0/z, [x0]
 ; VBITS_GE_512-NEXT:    ld1w { z2.s }, p0/z, [x1]
 ; VBITS_GE_512-NEXT:    and z0.s, z0.s, #0x1
 ; VBITS_GE_512-NEXT:    cmpne p1.s, p1/z, z0.s, #0
 ; VBITS_GE_512-NEXT:    sel z0.s, p1, z1.s, z2.s
 ; VBITS_GE_512-NEXT:    st1w { z0.s }, p0, [x0]
 ; VBITS_GE_512-NEXT:    mov sp, x29
 ; VBITS_GE_512-NEXT:    ldp x29, x30, [sp], #16 // 16-byte Folded Reload

 ; VBITS_GE_1024:       // %bb.0:
 ; VBITS_GE_1024-NEXT:    stp x29, x30, [sp, #-16]! // 16-byte Folded Spill
 ; VBITS_GE_1024-NEXT:    sub x9, sp, #240
 ; VBITS_GE_1024-NEXT:    mov x29, sp
 ; VBITS_GE_1024-NEXT:    and sp, x9, #0xffffffffffffff80
 ; VBITS_GE_1024-NEXT:    .cfi_def_cfa w29, 16
 ; VBITS_GE_1024-NEXT:    .cfi_offset w30, -8
 ; VBITS_GE_1024-NEXT:    .cfi_offset w29, -16
-; VBITS_GE_1024-NEXT:    ldr w9, [x2]
-; VBITS_GE_1024-NEXT:    mov x8, sp
+; VBITS_GE_1024-NEXT:    ldr w8, [x2]
 ; VBITS_GE_1024-NEXT:    ptrue p0.s, vl32
 ; VBITS_GE_1024-NEXT:    ptrue p1.s
-; VBITS_GE_1024-NEXT:    asr w10, w9, #31
-; VBITS_GE_1024-NEXT:    sbfx w11, w9, #30, #1
-; VBITS_GE_1024-NEXT:    sbfx w12, w9, #29, #1
-; VBITS_GE_1024-NEXT:    sbfx w13, w9, #28, #1
-; VBITS_GE_1024-NEXT:    stp w11, w10, [sp, #120]
-; VBITS_GE_1024-NEXT:    sbfx w10, w9, #27, #1
-; VBITS_GE_1024-NEXT:    sbfx w11, w9, #26, #1
-; VBITS_GE_1024-NEXT:    stp w13, w12, [sp, #112]
-; VBITS_GE_1024-NEXT:    sbfx w12, w9, #25, #1
-; VBITS_GE_1024-NEXT:    sbfx w13, w9, #24, #1
-; VBITS_GE_1024-NEXT:    stp w11, w10, [sp, #104]
-; VBITS_GE_1024-NEXT:    sbfx w10, w9, #23, #1
-; VBITS_GE_1024-NEXT:    sbfx w11, w9, #22, #1
-; VBITS_GE_1024-NEXT:    stp w13, w12, [sp, #96]
-; VBITS_GE_1024-NEXT:    sbfx w12, w9, #21, #1
-; VBITS_GE_1024-NEXT:    sbfx w13, w9, #20, #1
-; VBITS_GE_1024-NEXT:    stp w11, w10, [sp, #88]
-; VBITS_GE_1024-NEXT:    sbfx w10, w9, #19, #1
-; VBITS_GE_1024-NEXT:    sbfx w11, w9, #18, #1
-; VBITS_GE_1024-NEXT:    stp w13, w12, [sp, #80]
-; VBITS_GE_1024-NEXT:    sbfx w12, w9, #17, #1
-; VBITS_GE_1024-NEXT:    sbfx w13, w9, #16, #1
-; VBITS_GE_1024-NEXT:    stp w11, w10, [sp, #72]
-; VBITS_GE_1024-NEXT:    sbfx w10, w9, #15, #1
-; VBITS_GE_1024-NEXT:    sbfx w11, w9, #14, #1
-; VBITS_GE_1024-NEXT:    stp w13, w12, [sp, #64]
-; VBITS_GE_1024-NEXT:    sbfx w12, w9, #13, #1
-; VBITS_GE_1024-NEXT:    sbfx w13, w9, #12, #1
-; VBITS_GE_1024-NEXT:    stp w11, w10, [sp, #56]
-; VBITS_GE_1024-NEXT:    sbfx w10, w9, #11, #1
-; VBITS_GE_1024-NEXT:    sbfx w11, w9, #10, #1
-; VBITS_GE_1024-NEXT:    stp w13, w12, [sp, #48]
-; VBITS_GE_1024-NEXT:    sbfx w12, w9, #9, #1
-; VBITS_GE_1024-NEXT:    sbfx w13, w9, #8, #1
-; VBITS_GE_1024-NEXT:    stp w11, w10, [sp, #40]
-; VBITS_GE_1024-NEXT:    sbfx w10, w9, #7, #1
-; VBITS_GE_1024-NEXT:    sbfx w11, w9, #6, #1
-; VBITS_GE_1024-NEXT:    stp w13, w12, [sp, #32]
-; VBITS_GE_1024-NEXT:    sbfx w12, w9, #5, #1
-; VBITS_GE_1024-NEXT:    sbfx w13, w9, #4, #1
-; VBITS_GE_1024-NEXT:    stp w11, w10, [sp, #24]
-; VBITS_GE_1024-NEXT:    sbfx w10, w9, #3, #1
-; VBITS_GE_1024-NEXT:    sbfx w11, w9, #2, #1
-; VBITS_GE_1024-NEXT:    stp w13, w12, [sp, #16]
-; VBITS_GE_1024-NEXT:    sbfx w12, w9, #1, #1
-; VBITS_GE_1024-NEXT:    sbfx w9, w9, #0, #1
-; VBITS_GE_1024-NEXT:    stp w11, w10, [sp, #8]
-; VBITS_GE_1024-NEXT:    stp w9, w12, [sp]
-; VBITS_GE_1024-NEXT:    ld1w { z0.s }, p0/z, [x8]
+; VBITS_GE_1024-NEXT:    asr w9, w8, #31
+; VBITS_GE_1024-NEXT:    sbfx w10, w8, #30, #1
+; VBITS_GE_1024-NEXT:    sbfx w11, w8, #29, #1
+; VBITS_GE_1024-NEXT:    sbfx w12, w8, #28, #1
+; VBITS_GE_1024-NEXT:    stp w10, w9, [sp, #120]
+; VBITS_GE_1024-NEXT:    sbfx w9, w8, #27, #1
+; VBITS_GE_1024-NEXT:    sbfx w10, w8, #26, #1
+; VBITS_GE_1024-NEXT:    stp w12, w11, [sp, #112]
+; VBITS_GE_1024-NEXT:    sbfx w11, w8, #25, #1
+; VBITS_GE_1024-NEXT:    sbfx w12, w8, #24, #1
+; VBITS_GE_1024-NEXT:    stp w10, w9, [sp, #104]
+; VBITS_GE_1024-NEXT:    sbfx w9, w8, #23, #1
+; VBITS_GE_1024-NEXT:    sbfx w10, w8, #22, #1
+; VBITS_GE_1024-NEXT:    stp w12, w11, [sp, #96]
+; VBITS_GE_1024-NEXT:    sbfx w11, w8, #21, #1
+; VBITS_GE_1024-NEXT:    sbfx w12, w8, #20, #1
+; VBITS_GE_1024-NEXT:    stp w10, w9, [sp, #88]
+; VBITS_GE_1024-NEXT:    sbfx w9, w8, #19, #1
+; VBITS_GE_1024-NEXT:    sbfx w10, w8, #18, #1
+; VBITS_GE_1024-NEXT:    stp w12, w11, [sp, #80]
+; VBITS_GE_1024-NEXT:    sbfx w11, w8, #17, #1
+; VBITS_GE_1024-NEXT:    sbfx w12, w8, #16, #1
+; VBITS_GE_1024-NEXT:    stp w10, w9, [sp, #72]
+; VBITS_GE_1024-NEXT:    sbfx w9, w8, #15, #1
+; VBITS_GE_1024-NEXT:    sbfx w10, w8, #14, #1
+; VBITS_GE_1024-NEXT:    stp w12, w11, [sp, #64]
+; VBITS_GE_1024-NEXT:    sbfx w11, w8, #13, #1
+; VBITS_GE_1024-NEXT:    sbfx w12, w8, #12, #1
+; VBITS_GE_1024-NEXT:    stp w10, w9, [sp, #56]
+; VBITS_GE_1024-NEXT:    sbfx w9, w8, #11, #1
+; VBITS_GE_1024-NEXT:    sbfx w10, w8, #10, #1
+; VBITS_GE_1024-NEXT:    stp w12, w11, [sp, #48]
+; VBITS_GE_1024-NEXT:    sbfx w11, w8, #9, #1
+; VBITS_GE_1024-NEXT:    sbfx w12, w8, #8, #1
+; VBITS_GE_1024-NEXT:    stp w10, w9, [sp, #40]
+; VBITS_GE_1024-NEXT:    sbfx w9, w8, #7, #1
+; VBITS_GE_1024-NEXT:    sbfx w10, w8, #6, #1
+; VBITS_GE_1024-NEXT:    stp w12, w11, [sp, #32]
+; VBITS_GE_1024-NEXT:    sbfx w11, w8, #5, #1
+; VBITS_GE_1024-NEXT:    sbfx w12, w8, #4, #1
+; VBITS_GE_1024-NEXT:    stp w10, w9, [sp, #24]
+; VBITS_GE_1024-NEXT:    sbfx w9, w8, #3, #1
+; VBITS_GE_1024-NEXT:    sbfx w10, w8, #2, #1
+; VBITS_GE_1024-NEXT:    stp w12, w11, [sp, #16]
+; VBITS_GE_1024-NEXT:    sbfx w11, w8, #1, #1
+; VBITS_GE_1024-NEXT:    sbfx w8, w8, #0, #1
+; VBITS_GE_1024-NEXT:    stp w10, w9, [sp, #8]
+; VBITS_GE_1024-NEXT:    stp w8, w11, [sp]
+; VBITS_GE_1024-NEXT:    ld1w { z0.s }, p0/z, [sp]
 ; VBITS_GE_1024-NEXT:    ld1w { z1.s }, p0/z, [x0]
 ; VBITS_GE_1024-NEXT:    ld1w { z2.s }, p0/z, [x1]
 ; VBITS_GE_1024-NEXT:    and z0.s, z0.s, #0x1
 ; VBITS_GE_1024-NEXT:    cmpne p1.s, p1/z, z0.s, #0
 ; VBITS_GE_1024-NEXT:    sel z0.s, p1, z1.s, z2.s
 ; VBITS_GE_1024-NEXT:    st1w { z0.s }, p0, [x0]
 ; VBITS_GE_1024-NEXT:    mov sp, x29
 ; VBITS_GE_1024-NEXT:    ldp x29, x30, [sp], #16 // 16-byte Folded Reload

 ; VBITS_GE_2048:       // %bb.0:
 ; VBITS_GE_2048-NEXT:    stp x29, x30, [sp, #-16]! // 16-byte Folded Spill
 ; VBITS_GE_2048-NEXT:    sub x9, sp, #496
 ; VBITS_GE_2048-NEXT:    mov x29, sp
 ; VBITS_GE_2048-NEXT:    and sp, x9, #0xffffffffffffff00
 ; VBITS_GE_2048-NEXT:    .cfi_def_cfa w29, 16
 ; VBITS_GE_2048-NEXT:    .cfi_offset w30, -8
 ; VBITS_GE_2048-NEXT:    .cfi_offset w29, -16
-; VBITS_GE_2048-NEXT:    ldr x9, [x2]
-; VBITS_GE_2048-NEXT:    mov x8, sp
+; VBITS_GE_2048-NEXT:    ldr x8, [x2]
 ; VBITS_GE_2048-NEXT:    ptrue p0.s, vl64
 ; VBITS_GE_2048-NEXT:    ptrue p1.s
-; VBITS_GE_2048-NEXT:    asr x10, x9, #63
-; VBITS_GE_2048-NEXT:    sbfx x11, x9, #62, #1
-; VBITS_GE_2048-NEXT:    sbfx x12, x9, #61, #1
-; VBITS_GE_2048-NEXT:    sbfx x13, x9, #60, #1
-; VBITS_GE_2048-NEXT:    stp w11, w10, [sp, #248]
-; VBITS_GE_2048-NEXT:    sbfx x10, x9, #59, #1
-; VBITS_GE_2048-NEXT:    sbfx x11, x9, #58, #1
-; VBITS_GE_2048-NEXT:    stp w13, w12, [sp, #240]
-; VBITS_GE_2048-NEXT:    sbfx x12, x9, #57, #1
-; VBITS_GE_2048-NEXT:    sbfx x13, x9, #56, #1
-; VBITS_GE_2048-NEXT:    stp w11, w10, [sp, #232]
-; VBITS_GE_2048-NEXT:    sbfx x10, x9, #55, #1
-; VBITS_GE_2048-NEXT:    sbfx x11, x9, #54, #1
-; VBITS_GE_2048-NEXT:    stp w13, w12, [sp, #224]
-; VBITS_GE_2048-NEXT:    sbfx x12, x9, #53, #1
-; VBITS_GE_2048-NEXT:    sbfx x13, x9, #52, #1
-; VBITS_GE_2048-NEXT:    stp w11, w10, [sp, #216]
-; VBITS_GE_2048-NEXT:    sbfx x10, x9, #51, #1
-; VBITS_GE_2048-NEXT:    sbfx x11, x9, #50, #1
-; VBITS_GE_2048-NEXT:    stp w13, w12, [sp, #208]
-; VBITS_GE_2048-NEXT:    sbfx x12, x9, #49, #1
-; VBITS_GE_2048-NEXT:    sbfx x13, x9, #48, #1
-; VBITS_GE_2048-NEXT:    stp w11, w10, [sp, #200]
-; VBITS_GE_2048-NEXT:    sbfx x10, x9, #47, #1
-; VBITS_GE_2048-NEXT:    sbfx x11, x9, #46, #1
-; VBITS_GE_2048-NEXT:    stp w13, w12, [sp, #192]
-; VBITS_GE_2048-NEXT:    sbfx x12, x9, #45, #1
-; VBITS_GE_2048-NEXT:    sbfx x13, x9, #44, #1
-; VBITS_GE_2048-NEXT:    stp w11, w10, [sp, #184]
-; VBITS_GE_2048-NEXT:    sbfx x10, x9, #43, #1
-; VBITS_GE_2048-NEXT:    sbfx x11, x9, #42, #1
-; VBITS_GE_2048-NEXT:    stp w13, w12, [sp, #176]
-; VBITS_GE_2048-NEXT:    sbfx x12, x9, #41, #1
-; VBITS_GE_2048-NEXT:    sbfx x13, x9, #40, #1
-; VBITS_GE_2048-NEXT:    stp w11, w10, [sp, #168]
-; VBITS_GE_2048-NEXT:    sbfx x10, x9, #39, #1
-; VBITS_GE_2048-NEXT:    sbfx x11, x9, #38, #1
-; VBITS_GE_2048-NEXT:    stp w13, w12, [sp, #160]
-; VBITS_GE_2048-NEXT:    sbfx x12, x9, #37, #1
-; VBITS_GE_2048-NEXT:    sbfx x13, x9, #36, #1
-; VBITS_GE_2048-NEXT:    stp w11, w10, [sp, #152]
-; VBITS_GE_2048-NEXT:    sbfx x10, x9, #35, #1
-; VBITS_GE_2048-NEXT:    sbfx x11, x9, #34, #1
-; VBITS_GE_2048-NEXT:    stp w13, w12, [sp, #144]
-; VBITS_GE_2048-NEXT:    sbfx x12, x9, #33, #1
-; VBITS_GE_2048-NEXT:    sbfx x13, x9, #32, #1
-; VBITS_GE_2048-NEXT:    stp w11, w10, [sp, #136]
-; VBITS_GE_2048-NEXT:    asr w10, w9, #31
-; VBITS_GE_2048-NEXT:    sbfx w11, w9, #30, #1
-; VBITS_GE_2048-NEXT:    stp w13, w12, [sp, #128]
-; VBITS_GE_2048-NEXT:    sbfx w12, w9, #29, #1
-; VBITS_GE_2048-NEXT:    sbfx w13, w9, #28, #1
-; VBITS_GE_2048-NEXT:    stp w11, w10, [sp, #120]
-; VBITS_GE_2048-NEXT:    sbfx w10, w9, #27, #1
-; VBITS_GE_2048-NEXT:    sbfx w11, w9, #26, #1
-; VBITS_GE_2048-NEXT:    stp w13, w12, [sp, #112]
-; VBITS_GE_2048-NEXT:    sbfx w12, w9, #25, #1
-; VBITS_GE_2048-NEXT:    sbfx w13, w9, #24, #1
-; VBITS_GE_2048-NEXT:    stp w11, w10, [sp, #104]
-; VBITS_GE_2048-NEXT:    sbfx w10, w9, #23, #1
-; VBITS_GE_2048-NEXT:    sbfx w11, w9, #22, #1
-; VBITS_GE_2048-NEXT:    stp w13, w12, [sp, #96]
-; VBITS_GE_2048-NEXT:    sbfx w12, w9, #21, #1
-; VBITS_GE_2048-NEXT:    sbfx w13, w9, #20, #1
-; VBITS_GE_2048-NEXT:    stp w11, w10, [sp, #88]
-; VBITS_GE_2048-NEXT:    sbfx w10, w9, #19, #1
-; VBITS_GE_2048-NEXT:    sbfx w11, w9, #18, #1
-; VBITS_GE_2048-NEXT:    stp w13, w12, [sp, #80]
-; VBITS_GE_2048-NEXT:    sbfx w12, w9, #17, #1
-; VBITS_GE_2048-NEXT:    sbfx w13, w9, #16, #1
-; VBITS_GE_2048-NEXT:    stp w11, w10, [sp, #72]
-; VBITS_GE_2048-NEXT:    sbfx w10, w9, #15, #1
-; VBITS_GE_2048-NEXT:    sbfx w11, w9, #14, #1
-; VBITS_GE_2048-NEXT:    stp w13, w12, [sp, #64]
-; VBITS_GE_2048-NEXT:    sbfx w12, w9, #13, #1
-; VBITS_GE_2048-NEXT:    sbfx w13, w9, #12, #1
-; VBITS_GE_2048-NEXT:    stp w11, w10, [sp, #56]
-; VBITS_GE_2048-NEXT:    sbfx w10, w9, #11, #1
-; VBITS_GE_2048-NEXT:    sbfx w11, w9, #10, #1
-; VBITS_GE_2048-NEXT:    stp w13, w12, [sp, #48]
-; VBITS_GE_2048-NEXT:    sbfx w12, w9, #9, #1
-; VBITS_GE_2048-NEXT:    sbfx w13, w9, #8, #1
-; VBITS_GE_2048-NEXT:    stp w11, w10, [sp, #40]
-; VBITS_GE_2048-NEXT:    sbfx w10, w9, #7, #1
-; VBITS_GE_2048-NEXT:    sbfx w11, w9, #6, #1
-; VBITS_GE_2048-NEXT:    stp w13, w12, [sp, #32]
-; VBITS_GE_2048-NEXT:    sbfx w12, w9, #5, #1
-; VBITS_GE_2048-NEXT:    sbfx w13, w9, #4, #1
-; VBITS_GE_2048-NEXT:    stp w11, w10, [sp, #24]
-; VBITS_GE_2048-NEXT:    sbfx w10, w9, #3, #1
-; VBITS_GE_2048-NEXT:    sbfx w11, w9, #2, #1
-; VBITS_GE_2048-NEXT:    stp w13, w12, [sp, #16]
-; VBITS_GE_2048-NEXT:    sbfx w12, w9, #1, #1
-; VBITS_GE_2048-NEXT:    sbfx w9, w9, #0, #1
-; VBITS_GE_2048-NEXT:    stp w11, w10, [sp, #8]
-; VBITS_GE_2048-NEXT:    stp w9, w12, [sp]
-; VBITS_GE_2048-NEXT:    ld1w { z0.s }, p0/z, [x8]
+; VBITS_GE_2048-NEXT:    asr x9, x8, #63
+; VBITS_GE_2048-NEXT:    sbfx x10, x8, #62, #1
+; VBITS_GE_2048-NEXT:    sbfx x11, x8, #61, #1
+; VBITS_GE_2048-NEXT:    sbfx x12, x8, #60, #1
+; VBITS_GE_2048-NEXT:    stp w10, w9, [sp, #248]
+; VBITS_GE_2048-NEXT:    sbfx x9, x8, #59, #1
+; VBITS_GE_2048-NEXT:    sbfx x10, x8, #58, #1
+; VBITS_GE_2048-NEXT:    stp w12, w11, [sp, #240]
+; VBITS_GE_2048-NEXT:    sbfx x11, x8, #57, #1
+; VBITS_GE_2048-NEXT:    sbfx x12, x8, #56, #1
+; VBITS_GE_2048-NEXT:    stp w10, w9, [sp, #232]
+; VBITS_GE_2048-NEXT:    sbfx x9, x8, #55, #1
+; VBITS_GE_2048-NEXT:    sbfx x10, x8, #54, #1
+; VBITS_GE_2048-NEXT:    stp w12, w11, [sp, #224]
+; VBITS_GE_2048-NEXT:    sbfx x11, x8, #53, #1
+; VBITS_GE_2048-NEXT:    sbfx x12, x8, #52, #1
+; VBITS_GE_2048-NEXT:    stp w10, w9, [sp, #216]
+; VBITS_GE_2048-NEXT:    sbfx x9, x8, #51, #1
+; VBITS_GE_2048-NEXT:    sbfx x10, x8, #50, #1
+; VBITS_GE_2048-NEXT:    stp w12, w11, [sp, #208]
+; VBITS_GE_2048-NEXT:    sbfx x11, x8, #49, #1
+; VBITS_GE_2048-NEXT:    sbfx x12, x8, #48, #1
+; VBITS_GE_2048-NEXT:    stp w10, w9, [sp, #200]
+; VBITS_GE_2048-NEXT:    sbfx x9, x8, #47, #1
+; VBITS_GE_2048-NEXT:    sbfx x10, x8, #46, #1
+; VBITS_GE_2048-NEXT:    stp w12, w11, [sp, #192]
+; VBITS_GE_2048-NEXT:    sbfx x11, x8, #45, #1
+; VBITS_GE_2048-NEXT:    sbfx x12, x8, #44, #1
+; VBITS_GE_2048-NEXT:    stp w10, w9, [sp, #184]
+; VBITS_GE_2048-NEXT:    sbfx x9, x8, #43, #1
+; VBITS_GE_2048-NEXT:    sbfx x10, x8, #42, #1
+; VBITS_GE_2048-NEXT:    stp w12, w11, [sp, #176]
+; VBITS_GE_2048-NEXT:    sbfx x11, x8, #41, #1
+; VBITS_GE_2048-NEXT:    sbfx x12, x8, #40, #1
+; VBITS_GE_2048-NEXT:    stp w10, w9, [sp, #168]
+; VBITS_GE_2048-NEXT:    sbfx x9, x8, #39, #1
+; VBITS_GE_2048-NEXT:    sbfx x10, x8, #38, #1
+; VBITS_GE_2048-NEXT:    stp w12, w11, [sp, #160]
+; VBITS_GE_2048-NEXT:    sbfx x11, x8, #37, #1
+; VBITS_GE_2048-NEXT:    sbfx x12, x8, #36, #1
+; VBITS_GE_2048-NEXT:    stp w10, w9, [sp, #152]
+; VBITS_GE_2048-NEXT:    sbfx x9, x8, #35, #1
+; VBITS_GE_2048-NEXT:    sbfx x10, x8, #34, #1
+; VBITS_GE_2048-NEXT:    stp w12, w11, [sp, #144]
+; VBITS_GE_2048-NEXT:    sbfx x11, x8, #33, #1
+; VBITS_GE_2048-NEXT:    sbfx x12, x8, #32, #1
+; VBITS_GE_2048-NEXT:    stp w10, w9, [sp, #136]
+; VBITS_GE_2048-NEXT:    asr w9, w8, #31
+; VBITS_GE_2048-NEXT:    sbfx w10, w8, #30, #1
+; VBITS_GE_2048-NEXT:    stp w12, w11, [sp, #128]
+; VBITS_GE_2048-NEXT:    sbfx w11, w8, #29, #1
+; VBITS_GE_2048-NEXT:    sbfx w12, w8, #28, #1
+; VBITS_GE_2048-NEXT:    stp w10, w9, [sp, #120]
+; VBITS_GE_2048-NEXT:    sbfx w9, w8, #27, #1
+; VBITS_GE_2048-NEXT:    sbfx w10, w8, #26, #1
+; VBITS_GE_2048-NEXT:    stp w12, w11, [sp, #112]
+; VBITS_GE_2048-NEXT:    sbfx w11, w8, #25, #1
+; VBITS_GE_2048-NEXT:    sbfx w12, w8, #24, #1
+; VBITS_GE_2048-NEXT:    stp w10, w9, [sp, #104]
+; VBITS_GE_2048-NEXT:    sbfx w9, w8, #23, #1
+; VBITS_GE_2048-NEXT:    sbfx w10, w8, #22, #1
+; VBITS_GE_2048-NEXT:    stp w12, w11, [sp, #96]
+; VBITS_GE_2048-NEXT:    sbfx w11, w8, #21, #1
+; VBITS_GE_2048-NEXT:    sbfx w12, w8, #20, #1
+; VBITS_GE_2048-NEXT:    stp w10, w9, [sp, #88]
+; VBITS_GE_2048-NEXT:    sbfx w9, w8, #19, #1
+; VBITS_GE_2048-NEXT:    sbfx w10, w8, #18, #1
+; VBITS_GE_2048-NEXT:    stp w12, w11, [sp, #80]
+; VBITS_GE_2048-NEXT:    sbfx w11, w8, #17, #1
+; VBITS_GE_2048-NEXT:    sbfx w12, w8, #16, #1
+; VBITS_GE_2048-NEXT:    stp w10, w9, [sp, #72]
+; VBITS_GE_2048-NEXT:    sbfx w9, w8, #15, #1
+; VBITS_GE_2048-NEXT:    sbfx w10, w8, #14, #1
+; VBITS_GE_2048-NEXT:    stp w12, w11, [sp, #64]
+; VBITS_GE_2048-NEXT:    sbfx w11, w8, #13, #1
+; VBITS_GE_2048-NEXT:    sbfx w12, w8, #12, #1
+; VBITS_GE_2048-NEXT:    stp w10, w9, [sp, #56]
+; VBITS_GE_2048-NEXT:    sbfx w9, w8, #11, #1
+; VBITS_GE_2048-NEXT:    sbfx w10, w8, #10, #1
+; VBITS_GE_2048-NEXT:    stp w12, w11, [sp, #48]
+; VBITS_GE_2048-NEXT:    sbfx w11, w8, #9, #1
+; VBITS_GE_2048-NEXT:    sbfx w12, w8, #8, #1
+; VBITS_GE_2048-NEXT:    stp w10, w9, [sp, #40]
+; VBITS_GE_2048-NEXT:    sbfx w9, w8, #7, #1
+; VBITS_GE_2048-NEXT:    sbfx w10, w8, #6, #1
+; VBITS_GE_2048-NEXT:    stp w12, w11, [sp, #32]
+; VBITS_GE_2048-NEXT:    sbfx w11, w8, #5, #1
+; VBITS_GE_2048-NEXT:    sbfx w12, w8, #4, #1
+; VBITS_GE_2048-NEXT:    stp w10, w9, [sp, #24]
+; VBITS_GE_2048-NEXT:    sbfx w9, w8, #3, #1
+; VBITS_GE_2048-NEXT:    sbfx w10, w8, #2, #1
+; VBITS_GE_2048-NEXT:    stp w12, w11, [sp, #16]
+; VBITS_GE_2048-NEXT:    sbfx w11, w8, #1, #1
+; VBITS_GE_2048-NEXT:    sbfx w8, w8, #0, #1
+; VBITS_GE_2048-NEXT:    stp w10, w9, [sp, #8]
+; VBITS_GE_2048-NEXT:    stp w8, w11, [sp]
+; VBITS_GE_2048-NEXT:    ld1w { z0.s }, p0/z, [sp]
 ; VBITS_GE_2048-NEXT:    ld1w { z1.s }, p0/z, [x0]
 ; VBITS_GE_2048-NEXT:    ld1w { z2.s }, p0/z, [x1]
 ; VBITS_GE_2048-NEXT:    and z0.s, z0.s, #0x1
 ; VBITS_GE_2048-NEXT:    cmpne p1.s, p1/z, z0.s, #0
 ; VBITS_GE_2048-NEXT:    sel z0.s, p1, z1.s, z2.s
 ; VBITS_GE_2048-NEXT:    st1w { z0.s }, p0, [x0]
 ; VBITS_GE_2048-NEXT:    mov sp, x29
 ; VBITS_GE_2048-NEXT:    ldp x29, x30, [sp], #16 // 16-byte Folded Reload

 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    stp x29, x30, [sp, #-16]! // 16-byte Folded Spill
 ; CHECK-NEXT:    sub x9, sp, #48
 ; CHECK-NEXT:    mov x29, sp
 ; CHECK-NEXT:    and sp, x9, #0xffffffffffffffe0
 ; CHECK-NEXT:    .cfi_def_cfa w29, 16
 ; CHECK-NEXT:    .cfi_offset w30, -8
 ; CHECK-NEXT:    .cfi_offset w29, -16
-; CHECK-NEXT:    ldrb w9, [x2]
-; CHECK-NEXT:    mov x8, sp
+; CHECK-NEXT:    ldrb w8, [x2]
 ; CHECK-NEXT:    ptrue p0.d, vl4
 ; CHECK-NEXT:    ptrue p1.d
-; CHECK-NEXT:    lsr w10, w9, #3
-; CHECK-NEXT:    lsr w11, w9, #2
-; CHECK-NEXT:    sbfx x12, x9, #0, #1
-; CHECK-NEXT:    lsr w9, w9, #1
-; CHECK-NEXT:    sbfx x10, x10, #0, #1
-; CHECK-NEXT:    sbfx x11, x11, #0, #1
+; CHECK-NEXT:    lsr w9, w8, #3
+; CHECK-NEXT:    lsr w10, w8, #2
+; CHECK-NEXT:    sbfx x11, x8, #0, #1
+; CHECK-NEXT:    lsr w8, w8, #1
 ; CHECK-NEXT:    sbfx x9, x9, #0, #1
-; CHECK-NEXT:    stp x11, x10, [sp, #16]
-; CHECK-NEXT:    stp x12, x9, [sp]
-; CHECK-NEXT:    ld1d { z0.d }, p0/z, [x8]
+; CHECK-NEXT:    sbfx x10, x10, #0, #1
+; CHECK-NEXT:    sbfx x8, x8, #0, #1
+; CHECK-NEXT:    stp x10, x9, [sp, #16]
+; CHECK-NEXT:    stp x11, x8, [sp]
+; CHECK-NEXT:    ld1d { z0.d }, p0/z, [sp]
 ; CHECK-NEXT:    ld1d { z1.d }, p0/z, [x0]
 ; CHECK-NEXT:    ld1d { z2.d }, p0/z, [x1]
 ; CHECK-NEXT:    and z0.d, z0.d, #0x1
 ; CHECK-NEXT:    cmpne p1.d, p1/z, z0.d, #0
 ; CHECK-NEXT:    sel z0.d, p1, z1.d, z2.d
 ; CHECK-NEXT:    st1d { z0.d }, p0, [x0]
 ; CHECK-NEXT:    mov sp, x29
 ; CHECK-NEXT:    ldp x29, x30, [sp], #16 // 16-byte Folded Reload

 ; VBITS_GE_512:       // %bb.0:
 ; VBITS_GE_512-NEXT:    stp x29, x30, [sp, #-16]! // 16-byte Folded Spill
 ; VBITS_GE_512-NEXT:    sub x9, sp, #112
 ; VBITS_GE_512-NEXT:    mov x29, sp
 ; VBITS_GE_512-NEXT:    and sp, x9, #0xffffffffffffffc0
 ; VBITS_GE_512-NEXT:    .cfi_def_cfa w29, 16
 ; VBITS_GE_512-NEXT:    .cfi_offset w30, -8
 ; VBITS_GE_512-NEXT:    .cfi_offset w29, -16
-; VBITS_GE_512-NEXT:    ldrb w9, [x2]
-; VBITS_GE_512-NEXT:    mov x8, sp
+; VBITS_GE_512-NEXT:    ldrb w8, [x2]
 ; VBITS_GE_512-NEXT:    ptrue p0.d, vl8
 ; VBITS_GE_512-NEXT:    ptrue p1.d
-; VBITS_GE_512-NEXT:    lsr w10, w9, #7
-; VBITS_GE_512-NEXT:    lsr w11, w9, #6
-; VBITS_GE_512-NEXT:    lsr w12, w9, #5
-; VBITS_GE_512-NEXT:    lsr w13, w9, #4
+; VBITS_GE_512-NEXT:    lsr w9, w8, #7
+; VBITS_GE_512-NEXT:    lsr w10, w8, #6
+; VBITS_GE_512-NEXT:    lsr w11, w8, #5
+; VBITS_GE_512-NEXT:    lsr w12, w8, #4
+; VBITS_GE_512-NEXT:    sbfx x9, x9, #0, #1
 ; VBITS_GE_512-NEXT:    sbfx x10, x10, #0, #1
 ; VBITS_GE_512-NEXT:    sbfx x11, x11, #0, #1
 ; VBITS_GE_512-NEXT:    sbfx x12, x12, #0, #1
-; VBITS_GE_512-NEXT:    sbfx x13, x13, #0, #1
-; VBITS_GE_512-NEXT:    lsr w14, w9, #3
-; VBITS_GE_512-NEXT:    stp x11, x10, [sp, #48]
-; VBITS_GE_512-NEXT:    lsr w10, w9, #2
-; VBITS_GE_512-NEXT:    stp x13, x12, [sp, #32]
-; VBITS_GE_512-NEXT:    sbfx x12, x9, #0, #1
-; VBITS_GE_512-NEXT:    lsr w9, w9, #1
-; VBITS_GE_512-NEXT:    sbfx x11, x14, #0, #1
-; VBITS_GE_512-NEXT:    sbfx x10, x10, #0, #1
+; VBITS_GE_512-NEXT:    lsr w13, w8, #3
+; VBITS_GE_512-NEXT:    stp x10, x9, [sp, #48]
+; VBITS_GE_512-NEXT:    lsr w9, w8, #2
+; VBITS_GE_512-NEXT:    stp x12, x11, [sp, #32]
+; VBITS_GE_512-NEXT:    sbfx x11, x8, #0, #1
+; VBITS_GE_512-NEXT:    lsr w8, w8, #1
+; VBITS_GE_512-NEXT:    sbfx x10, x13, #0, #1
 ; VBITS_GE_512-NEXT:    sbfx x9, x9, #0, #1
-; VBITS_GE_512-NEXT:    stp x10, x11, [sp, #16]
-; VBITS_GE_512-NEXT:    stp x12, x9, [sp]
-; VBITS_GE_512-NEXT:    ld1d { z0.d }, p0/z, [x8]
+; VBITS_GE_512-NEXT:    sbfx x8, x8, #0, #1
+; VBITS_GE_512-NEXT:    stp x9, x10, [sp, #16]
+; VBITS_GE_512-NEXT:    stp x11, x8, [sp]
+; VBITS_GE_512-NEXT:    ld1d { z0.d }, p0/z, [sp]
 ; VBITS_GE_512-NEXT:    ld1d { z1.d }, p0/z, [x0]
 ; VBITS_GE_512-NEXT:    ld1d { z2.d }, p0/z, [x1]
 ; VBITS_GE_512-NEXT:    and z0.d, z0.d, #0x1
 ; VBITS_GE_512-NEXT:    cmpne p1.d, p1/z, z0.d, #0
 ; VBITS_GE_512-NEXT:    sel z0.d, p1, z1.d, z2.d
 ; VBITS_GE_512-NEXT:    st1d { z0.d }, p0, [x0]
 ; VBITS_GE_512-NEXT:    mov sp, x29
 ; VBITS_GE_512-NEXT:    ldp x29, x30, [sp], #16 // 16-byte Folded Reload

 ; VBITS_GE_1024:       // %bb.0:
 ; VBITS_GE_1024-NEXT:    stp x29, x30, [sp, #-16]! // 16-byte Folded Spill
 ; VBITS_GE_1024-NEXT:    sub x9, sp, #240
 ; VBITS_GE_1024-NEXT:    mov x29, sp
 ; VBITS_GE_1024-NEXT:    and sp, x9, #0xffffffffffffff80
 ; VBITS_GE_1024-NEXT:    .cfi_def_cfa w29, 16
 ; VBITS_GE_1024-NEXT:    .cfi_offset w30, -8
 ; VBITS_GE_1024-NEXT:    .cfi_offset w29, -16
-; VBITS_GE_1024-NEXT:    ldrh w9, [x2]
-; VBITS_GE_1024-NEXT:    mov x8, sp
+; VBITS_GE_1024-NEXT:    ldrh w8, [x2]
 ; VBITS_GE_1024-NEXT:    ptrue p0.d, vl16
 ; VBITS_GE_1024-NEXT:    ptrue p1.d
-; VBITS_GE_1024-NEXT:    lsr w10, w9, #15
-; VBITS_GE_1024-NEXT:    lsr w11, w9, #14
-; VBITS_GE_1024-NEXT:    lsr w12, w9, #13
-; VBITS_GE_1024-NEXT:    lsr w13, w9, #12
+; VBITS_GE_1024-NEXT:    lsr w9, w8, #15
+; VBITS_GE_1024-NEXT:    lsr w10, w8, #14
+; VBITS_GE_1024-NEXT:    lsr w11, w8, #13
+; VBITS_GE_1024-NEXT:    lsr w12, w8, #12
+; VBITS_GE_1024-NEXT:    sbfx x9, x9, #0, #1
 ; VBITS_GE_1024-NEXT:    sbfx x10, x10, #0, #1
 ; VBITS_GE_1024-NEXT:    sbfx x11, x11, #0, #1
 ; VBITS_GE_1024-NEXT:    sbfx x12, x12, #0, #1
-; VBITS_GE_1024-NEXT:    sbfx x13, x13, #0, #1
-; VBITS_GE_1024-NEXT:    lsr w14, w9, #11
-; VBITS_GE_1024-NEXT:    lsr w15, w9, #10
-; VBITS_GE_1024-NEXT:    stp x11, x10, [sp, #112]
-; VBITS_GE_1024-NEXT:    lsr w10, w9, #9
-; VBITS_GE_1024-NEXT:    stp x13, x12, [sp, #96]
-; VBITS_GE_1024-NEXT:    lsr w13, w9, #8
+; VBITS_GE_1024-NEXT:    lsr w13, w8, #11
+; VBITS_GE_1024-NEXT:    lsr w14, w8, #10
+; VBITS_GE_1024-NEXT:    stp x10, x9, [sp, #112]
+; VBITS_GE_1024-NEXT:    lsr w9, w8, #9
+; VBITS_GE_1024-NEXT:    stp x12, x11, [sp, #96]
+; VBITS_GE_1024-NEXT:    lsr w12, w8, #8
+; VBITS_GE_1024-NEXT:    sbfx x10, x13, #0, #1
 ; VBITS_GE_1024-NEXT:    sbfx x11, x14, #0, #1
-; VBITS_GE_1024-NEXT:    sbfx x12, x15, #0, #1
-; VBITS_GE_1024-NEXT:    sbfx x10, x10, #0, #1
-; VBITS_GE_1024-NEXT:    sbfx x13, x13, #0, #1
-; VBITS_GE_1024-NEXT:    lsr w14, w9, #3
-; VBITS_GE_1024-NEXT:    stp x12, x11, [sp, #80]
-; VBITS_GE_1024-NEXT:    lsr w11, w9, #6
-; VBITS_GE_1024-NEXT:    stp x13, x10, [sp, #64]
-; VBITS_GE_1024-NEXT:    lsr w10, w9, #7
-; VBITS_GE_1024-NEXT:    lsr w12, w9, #5
-; VBITS_GE_1024-NEXT:    lsr w13, w9, #4
+; VBITS_GE_1024-NEXT:    sbfx x9, x9, #0, #1
+; VBITS_GE_1024-NEXT:    sbfx x12, x12, #0, #1
+; VBITS_GE_1024-NEXT:    lsr w13, w8, #3
+; VBITS_GE_1024-NEXT:    stp x11, x10, [sp, #80]
+; VBITS_GE_1024-NEXT:    lsr w10, w8, #6
+; VBITS_GE_1024-NEXT:    stp x12, x9, [sp, #64]
+; VBITS_GE_1024-NEXT:    lsr w9, w8, #7
+; VBITS_GE_1024-NEXT:    lsr w11, w8, #5
+; VBITS_GE_1024-NEXT:    lsr w12, w8, #4
+; VBITS_GE_1024-NEXT:    sbfx x9, x9, #0, #1
 ; VBITS_GE_1024-NEXT:    sbfx x10, x10, #0, #1
 ; VBITS_GE_1024-NEXT:    sbfx x11, x11, #0, #1
 ; VBITS_GE_1024-NEXT:    sbfx x12, x12, #0, #1
-; VBITS_GE_1024-NEXT:    sbfx x13, x13, #0, #1
-; VBITS_GE_1024-NEXT:    stp x11, x10, [sp, #48]
-; VBITS_GE_1024-NEXT:    lsr w11, w9, #2
-; VBITS_GE_1024-NEXT:    stp x13, x12, [sp, #32]
-; VBITS_GE_1024-NEXT:    sbfx x12, x9, #0, #1
-; VBITS_GE_1024-NEXT:    lsr w9, w9, #1
-; VBITS_GE_1024-NEXT:    sbfx x10, x14, #0, #1
-; VBITS_GE_1024-NEXT:    sbfx x11, x11, #0, #1
-; VBITS_GE_1024-NEXT:    sbfx x9, x9, #0, #1
-; VBITS_GE_1024-NEXT:    stp x11, x10, [sp, #16]
-; VBITS_GE_1024-NEXT:    stp x12, x9, [sp]
-; VBITS_GE_1024-NEXT:    ld1d { z0.d }, p0/z, [x8]
+; VBITS_GE_1024-NEXT:    stp x10, x9, [sp, #48]
+; VBITS_GE_1024-NEXT:    lsr w10, w8, #2
+; VBITS_GE_1024-NEXT:    stp x12, x11, [sp, #32]
+; VBITS_GE_1024-NEXT:    sbfx x11, x8, #0, #1
+; VBITS_GE_1024-NEXT:    lsr w8, w8, #1
+; VBITS_GE_1024-NEXT:    sbfx x9, x13, #0, #1
+; VBITS_GE_1024-NEXT:    sbfx x10, x10, #0, #1
+; VBITS_GE_1024-NEXT:    sbfx x8, x8, #0, #1
+; VBITS_GE_1024-NEXT:    stp x10, x9, [sp, #16]
+; VBITS_GE_1024-NEXT:    stp x11, x8, [sp]
+; VBITS_GE_1024-NEXT:    ld1d { z0.d }, p0/z, [sp]
 ; VBITS_GE_1024-NEXT:    ld1d { z1.d }, p0/z, [x0]
 ; VBITS_GE_1024-NEXT:    ld1d { z2.d }, p0/z, [x1]
 ; VBITS_GE_1024-NEXT:    and z0.d, z0.d, #0x1
 ; VBITS_GE_1024-NEXT:    cmpne p1.d, p1/z, z0.d, #0
 ; VBITS_GE_1024-NEXT:    sel z0.d, p1, z1.d, z2.d
 ; VBITS_GE_1024-NEXT:    st1d { z0.d }, p0, [x0]
 ; VBITS_GE_1024-NEXT:    mov sp, x29
 ; VBITS_GE_1024-NEXT:    ldp x29, x30, [sp], #16 // 16-byte Folded Reload

 ; VBITS_GE_2048:       // %bb.0:
 ; VBITS_GE_2048-NEXT:    stp x29, x30, [sp, #-16]! // 16-byte Folded Spill
 ; VBITS_GE_2048-NEXT:    sub x9, sp, #496
 ; VBITS_GE_2048-NEXT:    mov x29, sp
 ; VBITS_GE_2048-NEXT:    and sp, x9, #0xffffffffffffff00
 ; VBITS_GE_2048-NEXT:    .cfi_def_cfa w29, 16
 ; VBITS_GE_2048-NEXT:    .cfi_offset w30, -8
 ; VBITS_GE_2048-NEXT:    .cfi_offset w29, -16
-; VBITS_GE_2048-NEXT:    ldr w9, [x2]
-; VBITS_GE_2048-NEXT:    mov x8, sp
+; VBITS_GE_2048-NEXT:    ldr w8, [x2]
 ; VBITS_GE_2048-NEXT:    ptrue p0.d, vl32
 ; VBITS_GE_2048-NEXT:    ptrue p1.d
-; VBITS_GE_2048-NEXT:    ubfx x10, x9, #31, #1
-; VBITS_GE_2048-NEXT:    ubfx x11, x9, #30, #2
+; VBITS_GE_2048-NEXT:    ubfx x9, x8, #31, #1
+; VBITS_GE_2048-NEXT:    ubfx x10, x8, #30, #2
+; VBITS_GE_2048-NEXT:    // kill: def $w9 killed $w9 killed $x9 def $x9
 ; VBITS_GE_2048-NEXT:    // kill: def $w10 killed $w10 killed $x10 def $x10
-; VBITS_GE_2048-NEXT:    // kill: def $w11 killed $w11 killed $x11 def $x11
-; VBITS_GE_2048-NEXT:    ubfx x12, x9, #29, #3
-; VBITS_GE_2048-NEXT:    ubfx x13, x9, #28, #4
+; VBITS_GE_2048-NEXT:    ubfx x11, x8, #29, #3
+; VBITS_GE_2048-NEXT:    ubfx x12, x8, #28, #4
+; VBITS_GE_2048-NEXT:    sbfx x9, x9, #0, #1
 ; VBITS_GE_2048-NEXT:    sbfx x10, x10, #0, #1
-; VBITS_GE_2048-NEXT:    sbfx x11, x11, #0, #1
+; VBITS_GE_2048-NEXT:    // kill: def $w11 killed $w11 killed $x11 def $x11
 ; VBITS_GE_2048-NEXT:    // kill: def $w12 killed $w12 killed $x12 def $x12
+; VBITS_GE_2048-NEXT:    ubfx x13, x8, #27, #5
+; VBITS_GE_2048-NEXT:    ubfx x14, x8, #26, #6
 ; VBITS_GE_2048-NEXT:    // kill: def $w13 killed $w13 killed $x13 def $x13
-; VBITS_GE_2048-NEXT:    ubfx x14, x9, #27, #5
-; VBITS_GE_2048-NEXT:    ubfx x15, x9, #26, #6
 ; VBITS_GE_2048-NEXT:    // kill: def $w14 killed $w14 killed $x14 def $x14
-; VBITS_GE_2048-NEXT:    // kill: def $w15 killed $w15 killed $x15 def $x15
-; VBITS_GE_2048-NEXT:    stp x11, x10, [sp, #240]
-; VBITS_GE_2048-NEXT:    sbfx x10, x12, #0, #1
+; VBITS_GE_2048-NEXT:    stp x10, x9, [sp, #240]
+; VBITS_GE_2048-NEXT:    sbfx x9, x11, #0, #1
+; VBITS_GE_2048-NEXT:    sbfx x11, x12, #0, #1
 ; VBITS_GE_2048-NEXT:    sbfx x12, x13, #0, #1
-; VBITS_GE_2048-NEXT:    sbfx x13, x14, #0, #1
-; VBITS_GE_2048-NEXT:    ubfx x11, x9, #25, #7
-; VBITS_GE_2048-NEXT:    ubfx x14, x9, #23, #9
-; VBITS_GE_2048-NEXT:    // kill: def $w11 killed $w11 killed $x11 def $x11
-; VBITS_GE_2048-NEXT:    // kill: def $w14 killed $w14 killed $x14 def $x14
-; VBITS_GE_2048-NEXT:    stp x12, x10, [sp, #224]
-; VBITS_GE_2048-NEXT:    sbfx x10, x15, #0, #1
-; VBITS_GE_2048-NEXT:    ubfx x12, x9, #24, #8
-; VBITS_GE_2048-NEXT:    // kill: def $w12 killed $w12 killed $x12 def $x12
-; VBITS_GE_2048-NEXT:    stp x10, x13, [sp, #208]
-; VBITS_GE_2048-NEXT:    sbfx x10, x11, #0, #1
-; VBITS_GE_2048-NEXT:    sbfx x12, x12, #0, #1
-; VBITS_GE_2048-NEXT:    ubfx x11, x9, #22, #10
-; VBITS_GE_2048-NEXT:    sbfx x13, x14, #0, #1
-; VBITS_GE_2048-NEXT:    // kill: def $w11 killed $w11 killed $x11 def $x11
-; VBITS_GE_2048-NEXT:    ubfx x14, x9, #21, #11
-; VBITS_GE_2048-NEXT:    // kill: def $w14 killed $w14 killed $x14 def $x14
-; VBITS_GE_2048-NEXT:    stp x12, x10, [sp, #192]
-; VBITS_GE_2048-NEXT:    sbfx x10, x11, #0, #1
-; VBITS_GE_2048-NEXT:    ubfx x11, x9, #20, #12
-; VBITS_GE_2048-NEXT:    ubfx x12, x9, #19, #13
+; VBITS_GE_2048-NEXT:    ubfx x10, x8, #25, #7
+; VBITS_GE_2048-NEXT:    ubfx x13, x8, #23, #9
+; VBITS_GE_2048-NEXT:    // kill: def $w10 killed $w10 killed $x10 def $x10
+; VBITS_GE_2048-NEXT:    // kill: def $w13 killed $w13 killed $x13 def $x13
+; VBITS_GE_2048-NEXT:    stp x11, x9, [sp, #224]
+; VBITS_GE_2048-NEXT:    sbfx x9, x14, #0, #1
+; VBITS_GE_2048-NEXT:    ubfx x11, x8, #24, #8
 ; VBITS_GE_2048-NEXT:    // kill: def $w11 killed $w11 killed $x11 def $x11
-; VBITS_GE_2048-NEXT:    // kill: def $w12 killed $w12 killed $x12 def $x12
-; VBITS_GE_2048-NEXT:    stp x10, x13, [sp, #176]
-; VBITS_GE_2048-NEXT:    sbfx x10, x14, #0, #1
+; VBITS_GE_2048-NEXT:    stp x9, x12, [sp, #208]
+; VBITS_GE_2048-NEXT:    sbfx x9, x10, #0, #1
 ; VBITS_GE_2048-NEXT:    sbfx x11, x11, #0, #1
-; VBITS_GE_2048-NEXT:    ubfx x13, x9, #18, #14
-; VBITS_GE_2048-NEXT:    sbfx x12, x12, #0, #1
+; VBITS_GE_2048-NEXT:    ubfx x10, x8, #22, #10
+; VBITS_GE_2048-NEXT:    sbfx x12, x13, #0, #1
+; VBITS_GE_2048-NEXT:    // kill: def $w10 killed $w10 killed $x10 def $x10
+; VBITS_GE_2048-NEXT:    ubfx x13, x8, #21, #11
 ; VBITS_GE_2048-NEXT:    // kill: def $w13 killed $w13 killed $x13 def $x13
-; VBITS_GE_2048-NEXT:    ubfx x14, x9, #17, #15
-; VBITS_GE_2048-NEXT:    // kill: def $w14 killed $w14 killed $x14 def $x14
-; VBITS_GE_2048-NEXT:    stp x11, x10, [sp, #160]
-; VBITS_GE_2048-NEXT:    sbfx x10, x13, #0, #1
-; VBITS_GE_2048-NEXT:    ubfx x11, x9, #16, #16
-; VBITS_GE_2048-NEXT:    ubfx x13, x9, #15, #17
+; VBITS_GE_2048-NEXT:    stp x11, x9, [sp, #192]
+; VBITS_GE_2048-NEXT:    sbfx x9, x10, #0, #1
+; VBITS_GE_2048-NEXT:    ubfx x10, x8, #20, #12
+; VBITS_GE_2048-NEXT:    ubfx x11, x8, #19, #13
+; VBITS_GE_2048-NEXT:    // kill: def $w10 killed $w10 killed $x10 def $x10
 ; VBITS_GE_2048-NEXT:    // kill: def $w11 killed $w11 killed $x11 def $x11
-; VBITS_GE_2048-NEXT:    // kill: def $w13 killed $w13 killed $x13 def $x13
-; VBITS_GE_2048-NEXT:    stp x10, x12, [sp, #144]
-; VBITS_GE_2048-NEXT:    sbfx x10, x14, #0, #1
+; VBITS_GE_2048-NEXT:    stp x9, x12, [sp, #176]
+; VBITS_GE_2048-NEXT:    sbfx x9, x13, #0, #1
+; VBITS_GE_2048-NEXT:    sbfx x10, x10, #0, #1
+; VBITS_GE_2048-NEXT:    ubfx x12, x8, #18, #14
 ; VBITS_GE_2048-NEXT:    sbfx x11, x11, #0, #1
-; VBITS_GE_2048-NEXT:    ubfx x12, x9, #14, #18
-; VBITS_GE_2048-NEXT:    sbfx x13, x13, #0, #1
 ; VBITS_GE_2048-NEXT:    // kill: def $w12 killed $w12 killed $x12 def $x12
-; VBITS_GE_2048-NEXT:    ubfx x14, x9, #13, #19
-; VBITS_GE_2048-NEXT:    // kill: def $w14 killed $w14 killed $x14 def $x14
-; VBITS_GE_2048-NEXT:    stp x11, x10, [sp, #128]
-; VBITS_GE_2048-NEXT:    sbfx x10, x12, #0, #1
-; VBITS_GE_2048-NEXT:    ubfx x11, x9, #12, #20
-; VBITS_GE_2048-NEXT:    ubfx x12, x9, #11, #21
-; VBITS_GE_2048-NEXT:    // kill: def $w11 killed $w11 killed $x11 def $x11
+; VBITS_GE_2048-NEXT:    ubfx x13, x8, #17, #15
+; VBITS_GE_2048-NEXT:    // kill: def $w13 killed $w13 killed $x13 def $x13
+; VBITS_GE_2048-NEXT:    stp x10, x9, [sp, #160]
+; VBITS_GE_2048-NEXT:    sbfx x9, x12, #0, #1
+; VBITS_GE_2048-NEXT:    ubfx x10, x8, #16, #16
+; VBITS_GE_2048-NEXT:    ubfx x12, x8, #15, #17
+; VBITS_GE_2048-NEXT:    // kill: def $w10 killed $w10 killed $x10 def $x10
 ; VBITS_GE_2048-NEXT:    // kill: def $w12 killed $w12 killed $x12 def $x12
-; VBITS_GE_2048-NEXT:    stp x10, x13, [sp, #112]
-; VBITS_GE_2048-NEXT:    sbfx x10, x14, #0, #1
-; VBITS_GE_2048-NEXT:    sbfx x11, x11, #0, #1
-; VBITS_GE_2048-NEXT:    ubfx x13, x9, #10, #22
+; VBITS_GE_2048-NEXT:    stp x9, x11, [sp, #144]
+; VBITS_GE_2048-NEXT:    sbfx x9, x13, #0, #1
+; VBITS_GE_2048-NEXT:    sbfx x10, x10, #0, #1
+; VBITS_GE_2048-NEXT:    ubfx x11, x8, #14, #18
 ; VBITS_GE_2048-NEXT:    sbfx x12, x12, #0, #1
-; VBITS_GE_2048-NEXT:    // kill: def $w13 killed $w13 killed $x13 def $x13
-; VBITS_GE_2048-NEXT:    ubfx x14, x9, #9, #23
-; VBITS_GE_2048-NEXT:    // kill: def $w14 killed $w14 killed $x14 def $x14
-; VBITS_GE_2048-NEXT:    stp x11, x10, [sp, #96]
-; VBITS_GE_2048-NEXT:    sbfx x10, x13, #0, #1
-; VBITS_GE_2048-NEXT:    ubfx x11, x9, #8, #24
-; VBITS_GE_2048-NEXT:    ubfx x13, x9, #7, #25
 ; VBITS_GE_2048-NEXT:    // kill: def $w11 killed $w11 killed $x11 def $x11
+; VBITS_GE_2048-NEXT:    ubfx x13, x8, #13, #19
 ; VBITS_GE_2048-NEXT:    // kill: def $w13 killed $w13 killed $x13 def $x13
-; VBITS_GE_2048-NEXT:    stp x10, x12, [sp, #80]
-; VBITS_GE_2048-NEXT:    sbfx x10, x14, #0, #1
+; VBITS_GE_2048-NEXT:    stp x10, x9, [sp, #128]
+; VBITS_GE_2048-NEXT:    sbfx x9, x11, #0, #1
+; VBITS_GE_2048-NEXT:    ubfx x10, x8, #12, #20
+; VBITS_GE_2048-NEXT:    ubfx x11, x8, #11, #21
+; VBITS_GE_2048-NEXT:    // kill: def $w10 killed $w10 killed $x10 def $x10
+; VBITS_GE_2048-NEXT:    // kill: def $w11 killed $w11 killed $x11 def $x11
+; VBITS_GE_2048-NEXT:    stp x9, x12, [sp, #112]
+; VBITS_GE_2048-NEXT:    sbfx x9, x13, #0, #1
+; VBITS_GE_2048-NEXT:    sbfx x10, x10, #0, #1
+; VBITS_GE_2048-NEXT:    ubfx x12, x8, #10, #22
 ; VBITS_GE_2048-NEXT:    sbfx x11, x11, #0, #1
-; VBITS_GE_2048-NEXT:    ubfx x12, x9, #6, #26
-; VBITS_GE_2048-NEXT:    sbfx x13, x13, #0, #1
 ; VBITS_GE_2048-NEXT:    // kill: def $w12 killed $w12 killed $x12 def $x12
-; VBITS_GE_2048-NEXT:    ubfx x14, x9, #5, #27
-; VBITS_GE_2048-NEXT:    // kill: def $w14 killed $w14 killed $x14 def $x14
-; VBITS_GE_2048-NEXT:    stp x11, x10, [sp, #64]
-; VBITS_GE_2048-NEXT:    sbfx x10, x12, #0, #1
-; VBITS_GE_2048-NEXT:    ubfx x11, x9, #4, #28
-; VBITS_GE_2048-NEXT:    ubfx x12, x9, #3, #29
-; VBITS_GE_2048-NEXT:    // kill: def $w11 killed $w11 killed $x11 def $x11
+; VBITS_GE_2048-NEXT:    ubfx x13, x8, #9, #23
+; VBITS_GE_2048-NEXT:    // kill: def $w13 killed $w13 killed $x13 def $x13
+; VBITS_GE_2048-NEXT:    stp x10, x9, [sp, #96]
+; VBITS_GE_2048-NEXT:    sbfx x9, x12, #0, #1
+; VBITS_GE_2048-NEXT:    ubfx x10, x8, #8, #24
+; VBITS_GE_2048-NEXT:    ubfx x12, x8, #7, #25
+; VBITS_GE_2048-NEXT:    // kill: def $w10 killed $w10 killed $x10 def $x10
 ; VBITS_GE_2048-NEXT:    // kill: def $w12 killed $w12 killed $x12 def $x12
-; VBITS_GE_2048-NEXT:    stp x10, x13, [sp, #48]
-; VBITS_GE_2048-NEXT:    sbfx x10, x14, #0, #1
-; VBITS_GE_2048-NEXT:    sbfx x11, x11, #0, #1
-; VBITS_GE_2048-NEXT:    ubfx x13, x9, #2, #30
-; VBITS_GE_2048-NEXT:    ubfx x14, x9, #1, #31
+; VBITS_GE_2048-NEXT:    stp x9, x11, [sp, #80]
+; VBITS_GE_2048-NEXT:    sbfx x9, x13, #0, #1
+; VBITS_GE_2048-NEXT:    sbfx x10, x10, #0, #1
+; VBITS_GE_2048-NEXT:    ubfx x11, x8, #6, #26
 ; VBITS_GE_2048-NEXT:    sbfx x12, x12, #0, #1
+; VBITS_GE_2048-NEXT:    // kill: def $w11 killed $w11 killed $x11 def $x11
+; VBITS_GE_2048-NEXT:    ubfx x13, x8, #5, #27
 ; VBITS_GE_2048-NEXT:    // kill: def $w13 killed $w13 killed $x13 def $x13
-; VBITS_GE_2048-NEXT:    sbfx x9, x9, #0, #1
-; VBITS_GE_2048-NEXT:    // kill: def $w14 killed $w14 killed $x14 def $x14
-; VBITS_GE_2048-NEXT:    stp x11, x10, [sp, #32]
+; VBITS_GE_2048-NEXT:    stp x10, x9, [sp, #64]
+; VBITS_GE_2048-NEXT:    sbfx x9, x11, #0, #1
+; VBITS_GE_2048-NEXT:    ubfx x10, x8, #4, #28
+; VBITS_GE_2048-NEXT:    ubfx x11, x8, #3, #29
+; VBITS_GE_2048-NEXT:    // kill: def $w10 killed $w10 killed $x10 def $x10
+; VBITS_GE_2048-NEXT:    // kill: def $w11 killed $w11 killed $x11 def $x11
+; VBITS_GE_2048-NEXT:    stp x9, x12, [sp, #48]
+; VBITS_GE_2048-NEXT:    sbfx x9, x13, #0, #1
+; VBITS_GE_2048-NEXT:    sbfx x10, x10, #0, #1
+; VBITS_GE_2048-NEXT:    ubfx x12, x8, #2, #30
+; VBITS_GE_2048-NEXT:    ubfx x13, x8, #1, #31
+; VBITS_GE_2048-NEXT:    sbfx x11, x11, #0, #1
+; VBITS_GE_2048-NEXT:    // kill: def $w12 killed $w12 killed $x12 def $x12
+; VBITS_GE_2048-NEXT:    sbfx x8, x8, #0, #1
+; VBITS_GE_2048-NEXT:    // kill: def $w13 killed $w13 killed $x13 def $x13
+; VBITS_GE_2048-NEXT:    stp x10, x9, [sp, #32]
+; VBITS_GE_2048-NEXT:    sbfx x9, x12, #0, #1
 ; VBITS_GE_2048-NEXT:    sbfx x10, x13, #0, #1
-; VBITS_GE_2048-NEXT:    sbfx x11, x14, #0, #1
-; VBITS_GE_2048-NEXT:    stp x10, x12, [sp, #16]
-; VBITS_GE_2048-NEXT:    stp x9, x11, [sp]
-; VBITS_GE_2048-NEXT:    ld1d { z0.d }, p0/z, [x8]
+; VBITS_GE_2048-NEXT:    stp x9, x11, [sp, #16]
+; VBITS_GE_2048-NEXT:    stp x8, x10, [sp]
+; VBITS_GE_2048-NEXT:    ld1d { z0.d }, p0/z, [sp]
 ; VBITS_GE_2048-NEXT:    ld1d { z1.d }, p0/z, [x0]
 ; VBITS_GE_2048-NEXT:    ld1d { z2.d }, p0/z, [x1]
 ; VBITS_GE_2048-NEXT:    and z0.d, z0.d, #0x1
 ; VBITS_GE_2048-NEXT:    cmpne p1.d, p1/z, z0.d, #0
 ; VBITS_GE_2048-NEXT:    sel z0.d, p1, z1.d, z2.d
 ; VBITS_GE_2048-NEXT:    st1d { z0.d }, p0, [x0]
 ; VBITS_GE_2048-NEXT:    mov sp, x29
 ; VBITS_GE_2048-NEXT:    ldp x29, x30, [sp], #16 // 16-byte Folded Reload

llvm/test/CodeGen/AArch64/sve-fixed-length-vector-shuffle.ll

 ; CHECK-NEXT:    stp x29, x30, [sp, #-16]! // 16-byte Folded Spill
 ; CHECK-NEXT:    sub x9, sp, #48
 ; CHECK-NEXT:    mov x29, sp
 ; CHECK-NEXT:    and sp, x9, #0xffffffffffffffe0
 ; CHECK-NEXT:    .cfi_def_cfa w29, 16
 ; CHECK-NEXT:    .cfi_offset w30, -8
 ; CHECK-NEXT:    .cfi_offset w29, -16
 ; CHECK-NEXT:    ptrue p0.d, vl4
-; CHECK-NEXT:    mov x8, sp
 ; CHECK-NEXT:    ld1d { z0.d }, p0/z, [x0]
 ; CHECK-NEXT:    ld1d { z1.d }, p0/z, [x1]
 ; CHECK-NEXT:    mov z2.d, z1.d[1]
 ; CHECK-NEXT:    stp d1, d2, [sp, #16]
 ; CHECK-NEXT:    mov z1.d, z0.d[3]
 ; CHECK-NEXT:    mov z0.d, z0.d[2]
 ; CHECK-NEXT:    stp d0, d1, [sp]
-; CHECK-NEXT:    ld1d { z0.d }, p0/z, [x8]
+; CHECK-NEXT:    ld1d { z0.d }, p0/z, [sp]
 ; CHECK-NEXT:    st1d { z0.d }, p0, [x0]
 ; CHECK-NEXT:    mov sp, x29
 ; CHECK-NEXT:    ldp x29, x30, [sp], #16 // 16-byte Folded Reload
 ; CHECK-NEXT:    ret
   %op1 = load <4 x double>, <4 x double>* %a
   %op2 = load <4 x double>, <4 x double>* %b
   %ret = shufflevector <4 x double> %op1, <4 x double> %op2, <4 x i32> <i32 2, i32 3, i32 4, i32 5>
   store <4 x double> %ret, <4 x double>* %a
   ret void
 }
 
 attributes #0 = { "target-features"="+sve" }

llvm/test/CodeGen/AArch64/sve-insert-element.ll

 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    str x29, [sp, #-16]! // 8-byte Folded Spill
 ; CHECK-NEXT:    addvl sp, sp, #-2
 ; CHECK-NEXT:    .cfi_escape 0x0f, 0x0c, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 16 + 16 * VG
 ; CHECK-NEXT:    .cfi_offset w29, -16
 ; CHECK-NEXT:    mov x8, #-1
 ; CHECK-NEXT:    // kill: def $w1 killed $w1 def $x1
 ; CHECK-NEXT:    sxtw x9, w1
-; CHECK-NEXT:    mov x10, sp
 ; CHECK-NEXT:    mov z0.b, p1/z, #1 // =0x1
 ; CHECK-NEXT:    ptrue p1.b
+; CHECK-NEXT:    st1b { z0.b }, p1, [sp, #1, mul vl]
+; CHECK-NEXT:    mov z0.b, p0/z, #1 // =0x1
 ; CHECK-NEXT:    addvl x8, x8, #2
+; CHECK-NEXT:    st1b { z0.b }, p1, [sp]
 ; CHECK-NEXT:    cmp x9, x8
-; CHECK-NEXT:    st1b { z0.b }, p1, [x10, #1, mul vl]
 ; CHECK-NEXT:    csel x8, x9, x8, lo
-; CHECK-NEXT:    mov z0.b, p0/z, #1 // =0x1
-; CHECK-NEXT:    st1b { z0.b }, p1, [sp]
-; CHECK-NEXT:    strb w0, [x10, x8]
+; CHECK-NEXT:    mov x9, sp
+; CHECK-NEXT:    strb w0, [x9, x8]
 ; CHECK-NEXT:    ld1b { z0.b }, p1/z, [sp]
-; CHECK-NEXT:    ld1b { z1.b }, p1/z, [x10, #1, mul vl]
+; CHECK-NEXT:    ld1b { z1.b }, p1/z, [sp, #1, mul vl]
 ; CHECK-NEXT:    and z0.b, z0.b, #0x1
 ; CHECK-NEXT:    and z1.b, z1.b, #0x1
 ; CHECK-NEXT:    cmpne p0.b, p1/z, z0.b, #0
 ; CHECK-NEXT:    cmpne p1.b, p1/z, z1.b, #0
 ; CHECK-NEXT:    addvl sp, sp, #2
 ; CHECK-NEXT:    ldr x29, [sp], #16 // 8-byte Folded Reload
 ; CHECK-NEXT:    ret
   %res = insertelement <vscale x 32 x i1> %val, i1 %elt, i32 %idx
   ret <vscale x 32 x i1> %res
 }

llvm/test/CodeGen/AArch64/sve-insert-vector.ll

 
 define void @insert_v2i64_nxv16i64(<2 x i64> %sv0, <2 x i64> %sv1, <vscale x 16 x i64>* %out) {
 ; CHECK-LABEL: insert_v2i64_nxv16i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    str x29, [sp, #-16]! // 8-byte Folded Spill
 ; CHECK-NEXT:    addvl sp, sp, #-4
 ; CHECK-NEXT:    .cfi_escape 0x0f, 0x0c, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0x20, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 16 + 32 * VG
 ; CHECK-NEXT:    .cfi_offset w29, -16
-; CHECK-NEXT:    mov x8, sp
 ; CHECK-NEXT:    ptrue p0.d
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
 ; CHECK-NEXT:    st1d { z0.d }, p0, [sp]
 ; CHECK-NEXT:    str q1, [sp, #32]
-; CHECK-NEXT:    ld1d { z0.d }, p0/z, [x8, #1, mul vl]
-; CHECK-NEXT:    ld1d { z1.d }, p0/z, [x8, #2, mul vl]
-; CHECK-NEXT:    ld1d { z2.d }, p0/z, [x8, #3, mul vl]
-; CHECK-NEXT:    ld1d { z3.d }, p0/z, [sp]
-; CHECK-NEXT:    st1d { z2.d }, p0, [x0, #3, mul vl]
-; CHECK-NEXT:    st1d { z1.d }, p0, [x0, #2, mul vl]
-; CHECK-NEXT:    st1d { z0.d }, p0, [x0, #1, mul vl]
-; CHECK-NEXT:    st1d { z3.d }, p0, [x0]
+; CHECK-NEXT:    ld1d { z0.d }, p0/z, [sp]
+; CHECK-NEXT:    ld1d { z1.d }, p0/z, [sp, #1, mul vl]
+; CHECK-NEXT:    ld1d { z2.d }, p0/z, [sp, #2, mul vl]
+; CHECK-NEXT:    ld1d { z3.d }, p0/z, [sp, #3, mul vl]
+; CHECK-NEXT:    st1d { z3.d }, p0, [x0, #3, mul vl]
+; CHECK-NEXT:    st1d { z2.d }, p0, [x0, #2, mul vl]
+; CHECK-NEXT:    st1d { z1.d }, p0, [x0, #1, mul vl]
+; CHECK-NEXT:    st1d { z0.d }, p0, [x0]
 ; CHECK-NEXT:    addvl sp, sp, #4
 ; CHECK-NEXT:    ldr x29, [sp], #16 // 8-byte Folded Reload
 ; CHECK-NEXT:    ret
   %v0 = call <vscale x 16 x i64> @llvm.experimental.vector.insert.v2i64.nxv16i64(<vscale x 16 x i64> undef, <2 x i64> %sv0, i64 0)
   %v = call <vscale x 16 x i64> @llvm.experimental.vector.insert.v2i64.nxv16i64(<vscale x 16 x i64> %v0, <2 x i64> %sv1, i64 4)
   store <vscale x 16 x i64> %v, <vscale x 16 x i64>* %out
   ret void
 }

 define void @insert_v2i64_nxv16i64_lo2(<2 x i64>* %psv, <vscale x 16 x i64>* %out) {
 ; CHECK-LABEL: insert_v2i64_nxv16i64_lo2:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    str x29, [sp, #-16]! // 8-byte Folded Spill
 ; CHECK-NEXT:    addvl sp, sp, #-2
 ; CHECK-NEXT:    .cfi_escape 0x0f, 0x0c, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 16 + 16 * VG
 ; CHECK-NEXT:    .cfi_offset w29, -16
 ; CHECK-NEXT:    ldr q0, [x0]
-; CHECK-NEXT:    mov x8, sp
 ; CHECK-NEXT:    ptrue p0.d
 ; CHECK-NEXT:    str q0, [sp, #16]
-; CHECK-NEXT:    ld1d { z0.d }, p0/z, [x8, #1, mul vl]
-; CHECK-NEXT:    ld1d { z1.d }, p0/z, [sp]
-; CHECK-NEXT:    st1d { z0.d }, p0, [x1, #1, mul vl]
-; CHECK-NEXT:    st1d { z1.d }, p0, [x1]
+; CHECK-NEXT:    ld1d { z0.d }, p0/z, [sp]
+; CHECK-NEXT:    ld1d { z1.d }, p0/z, [sp, #1, mul vl]
+; CHECK-NEXT:    st1d { z1.d }, p0, [x1, #1, mul vl]
+; CHECK-NEXT:    st1d { z0.d }, p0, [x1]
 ; CHECK-NEXT:    addvl sp, sp, #2
 ; CHECK-NEXT:    ldr x29, [sp], #16 // 8-byte Folded Reload
 ; CHECK-NEXT:    ret
   %sv = load <2 x i64>, <2 x i64>* %psv
   %v = call <vscale x 16 x i64> @llvm.experimental.vector.insert.v2i64.nxv16i64(<vscale x 16 x i64> undef, <2 x i64> %sv, i64 2)
   store <vscale x 16 x i64> %v, <vscale x 16 x i64>* %out
   ret void
 }

 }
 
 ; Test that the index is scaled by vscale if the subvector is scalable.
 define <vscale x 8 x half> @insert_nxv8f16_nxv2f16(<vscale x 8 x half> %vec, <vscale x 2 x half> %in) nounwind {
 ; CHECK-LABEL: insert_nxv8f16_nxv2f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    str x29, [sp, #-16]! // 8-byte Folded Spill
 ; CHECK-NEXT:    addvl sp, sp, #-1
-; CHECK-NEXT:    mov x8, sp
 ; CHECK-NEXT:    ptrue p0.h
 ; CHECK-NEXT:    ptrue p1.d
 ; CHECK-NEXT:    st1h { z0.h }, p0, [sp]
-; CHECK-NEXT:    st1h { z1.d }, p1, [x8, #1, mul vl]
+; CHECK-NEXT:    st1h { z1.d }, p1, [sp, #1, mul vl]
 ; CHECK-NEXT:    ld1h { z0.h }, p0/z, [sp]
 ; CHECK-NEXT:    addvl sp, sp, #1
 ; CHECK-NEXT:    ldr x29, [sp], #16 // 8-byte Folded Reload
 ; CHECK-NEXT:    ret
   %r = call <vscale x 8 x half> @llvm.experimental.vector.insert.nxv8f16.nxv2f16(<vscale x 8 x half> %vec, <vscale x 2 x half> %in, i64 2)
   ret <vscale x 8 x half> %r
 }
 

  ret <vscale x 3 x float> %v0
 }
 
 define <vscale x 6 x i32>  @insert_nxv6i32_nxv2i32(<vscale x 2 x i32> %sv0, <vscale x 2 x i32> %sv1) nounwind {
 ; CHECK-LABEL: insert_nxv6i32_nxv2i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    str x29, [sp, #-16]! // 8-byte Folded Spill
 ; CHECK-NEXT:    addvl sp, sp, #-2
-; CHECK-NEXT:    mov x8, sp
-; CHECK-NEXT:    uunpklo z2.d, z0.s
 ; CHECK-NEXT:    uzp1 z0.s, z0.s, z1.s
-; CHECK-NEXT:    ptrue p0.d
-; CHECK-NEXT:    ptrue p1.s
-; CHECK-NEXT:    st1w { z2.d }, p0, [x8, #2, mul vl]
-; CHECK-NEXT:    st1w { z0.s }, p1, [sp]
-; CHECK-NEXT:    ld1w { z1.s }, p1/z, [x8, #1, mul vl]
-; CHECK-NEXT:    ld1w { z0.s }, p1/z, [sp]
+; CHECK-NEXT:    ptrue p0.s
+; CHECK-NEXT:    uunpklo z1.d, z0.s
+; CHECK-NEXT:    ptrue p1.d
+; CHECK-NEXT:    st1w { z0.s }, p0, [sp]
+; CHECK-NEXT:    st1w { z1.d }, p1, [sp, #2, mul vl]
+; CHECK-NEXT:    ld1w { z0.s }, p0/z, [sp]
+; CHECK-NEXT:    ld1w { z1.s }, p0/z, [sp, #1, mul vl]
 ; CHECK-NEXT:    addvl sp, sp, #2
 ; CHECK-NEXT:    ldr x29, [sp], #16 // 8-byte Folded Reload
 ; CHECK-NEXT:    ret
   %v0 = call <vscale x 6 x i32> @llvm.experimental.vector.insert.nxv6i32.nxv2i32(<vscale x 6 x i32> undef, <vscale x 2 x i32> %sv0, i64 0)
   %v1 = call <vscale x 6 x i32> @llvm.experimental.vector.insert.nxv6i32.nxv2i32(<vscale x 6 x i32> %v0, <vscale x 2 x i32> %sv1, i64 2)
   ret <vscale x 6 x i32> %v1
 }
 

llvm/test/CodeGen/AArch64/sve-ldnf1.mir

+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve -run-pass=prologepilog -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s
+#
+# Test that prologepilog works for each of the LDNF1 instructions for stack-based objects.
+#
+--- |
+  define void @testcase_positive_offset() {
+    %dummy = alloca <vscale x 2 x i64>, align 8
+    %object = alloca <vscale x 2 x i64>, align 8
+    ; Reads from %object at offset 63 * readsize
+    ret void
+  }
+  define void @testcase_negative_offset() {
+    %dummy = alloca <vscale x 2 x i64>, align 8
+    %object = alloca <vscale x 2 x i64>, align 8
+    ; Reads from %object at offset 63 * readsize
+    ret void
+  }
+
+  define void @testcase_positive_offset_out_of_range() {
+    %dummy = alloca <vscale x 2 x i64>, align 8
+    %object = alloca <vscale x 2 x i64>, align 8
+    ; Reads from %object at offset 64 * readsize
+    ret void
+  }
+  define void @testcase_negative_offset_out_of_range() {
+    %dummy = alloca <vscale x 2 x i64>, align 8
+    %object = alloca <vscale x 2 x i64>, align 8
+    ; Reads from %object at offset -1 * readsize
+    ret void
+  }
+...
+---
+name:            testcase_positive_offset
+tracksRegLiveness: true
+stack:
+  - { id: 0, name: dummy, type: default, offset: 0, size: 32, alignment: 16, stack-id: scalable-vector }
+  - { id: 1, name: object, type: default, offset: 0, size: 32, alignment: 16, stack-id: scalable-vector }
+body:             |
+  bb.0 (%ir-block.0):
+    liveins: $p0
+
+    ; CHECK-LABEL: name: testcase_positive_offset
+    ; CHECK: liveins: $p0
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: early-clobber $sp = frame-setup STRXpre killed $fp, $sp, -16 :: (store (s64) into %stack.2)
+    ; CHECK-NEXT: $sp = frame-setup ADDVL_XXI $sp, -4
+    ; CHECK-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x0c, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0x20, 0x92, 0x2e, 0x00, 0x1e, 0x22
+    ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $w29, -16
+    ; CHECK-NEXT: renamable $z0 = LDNF1B_IMM renamable $p0, $sp, 7 :: (load (s8) from %ir.object, align 2)
+    ; CHECK-NEXT: renamable $z0 = LDNF1B_H_IMM renamable $p0, $sp, 7 :: (load (s8) from %ir.object, align 2)
+    ; CHECK-NEXT: renamable $z0 = LDNF1B_S_IMM renamable $p0, $sp, 7 :: (load (s8) from %ir.object, align 2)
+    ; CHECK-NEXT: renamable $z0 = LDNF1B_D_IMM renamable $p0, $sp, 7 :: (load (s8) from %ir.object, align 2)
+    ; CHECK-NEXT: renamable $z0 = LDNF1SB_H_IMM renamable $p0, $sp, 7 :: (load (s8) from %ir.object, align 2)
+    ; CHECK-NEXT: renamable $z0 = LDNF1SB_S_IMM renamable $p0, $sp, 7 :: (load (s8) from %ir.object, align 2)
+    ; CHECK-NEXT: renamable $z0 = LDNF1SB_D_IMM renamable $p0, $sp, 7 :: (load (s8) from %ir.object, align 2)
+    ; CHECK-NEXT: renamable $z0 = LDNF1H_IMM renamable $p0, $sp, 7 :: (load (s16) from %ir.object)
+    ; CHECK-NEXT: renamable $z0 = LDNF1H_S_IMM renamable $p0, $sp, 7 :: (load (s16) from %ir.object)
+    ; CHECK-NEXT: renamable $z0 = LDNF1H_D_IMM renamable $p0, $sp, 7 :: (load (s16) from %ir.object)
+    ; CHECK-NEXT: renamable $z0 = LDNF1SH_S_IMM renamable $p0, $sp, 7 :: (load (s16) from %ir.object)
+    ; CHECK-NEXT: renamable $z0 = LDNF1SH_D_IMM renamable $p0, $sp, 7 :: (load (s16) from %ir.object)
+    ; CHECK-NEXT: renamable $z0 = LDNF1W_IMM renamable $p0, $sp, 7 :: (load (s32) from %ir.object, align 8)
+    ; CHECK-NEXT: renamable $z0 = LDNF1W_D_IMM renamable $p0, $sp, 7 :: (load (s32) from %ir.object, align 8)
+    ; CHECK-NEXT: renamable $z0 = LDNF1SW_D_IMM renamable $p0, $sp, 7 :: (load (s32) from %ir.object, align 8)
+    ; CHECK-NEXT: renamable $z0 = LDNF1D_IMM renamable $p0, $sp, 7 :: (load (s64) from %ir.object)
+    ; CHECK-NEXT: $sp = frame-destroy ADDVL_XXI $sp, 4
+    ; CHECK-NEXT: early-clobber $sp, $fp = frame-destroy LDRXpost $sp, 16 :: (load (s64) from %stack.2)
+    ; CHECK-NEXT: RET_ReallyLR implicit $z0
+    renamable $z0 = LDNF1B_IMM renamable $p0, %stack.1.object, 7 :: (load 1 from %ir.object, align 2)
+    renamable $z0 = LDNF1B_H_IMM renamable $p0, %stack.1.object, 7 :: (load 1 from %ir.object, align 2)
+    renamable $z0 = LDNF1B_S_IMM renamable $p0, %stack.1.object, 7 :: (load 1 from %ir.object, align 2)
+    renamable $z0 = LDNF1B_D_IMM renamable $p0, %stack.1.object, 7 :: (load 1 from %ir.object, align 2)
+    renamable $z0 = LDNF1SB_H_IMM renamable $p0, %stack.1.object, 7 :: (load 1 from %ir.object, align 2)
+    renamable $z0 = LDNF1SB_S_IMM renamable $p0, %stack.1.object, 7 :: (load 1 from %ir.object, align 2)
+    renamable $z0 = LDNF1SB_D_IMM renamable $p0, %stack.1.object, 7 :: (load 1 from %ir.object, align 2)
+    renamable $z0 = LDNF1H_IMM renamable $p0, %stack.1.object, 7 :: (load 2 from %ir.object, align 2)
+    renamable $z0 = LDNF1H_S_IMM renamable $p0, %stack.1.object, 7 :: (load 2 from %ir.object, align 2)
+    renamable $z0 = LDNF1H_D_IMM renamable $p0, %stack.1.object, 7 :: (load 2 from %ir.object, align 2)
+    renamable $z0 = LDNF1SH_S_IMM renamable $p0, %stack.1.object, 7 :: (load 2 from %ir.object, align 2)
+    renamable $z0 = LDNF1SH_D_IMM renamable $p0, %stack.1.object, 7 :: (load 2 from %ir.object, align 2)
+    renamable $z0 = LDNF1W_IMM renamable $p0, %stack.1.object, 7 :: (load 4 from %ir.object, align 8)
+    renamable $z0 = LDNF1W_D_IMM renamable $p0, %stack.1.object, 7 :: (load 4 from %ir.object, align 8)
+    renamable $z0 = LDNF1SW_D_IMM renamable $p0, %stack.1.object, 7 :: (load 4 from %ir.object, align 8)
+    renamable $z0 = LDNF1D_IMM renamable $p0, %stack.1.object, 7 :: (load 8 from %ir.object, align 8)
+    RET_ReallyLR implicit $z0
+...
+
+---
+name:            testcase_negative_offset
+tracksRegLiveness: true
+stack:
+  - { id: 0, name: dummy, type: default, offset: 0, size: 32, alignment: 16, stack-id: scalable-vector }
+  - { id: 1, name: object, type: default, offset: 0, size: 32, alignment: 16, stack-id: scalable-vector }
+body:             |
+  bb.0 (%ir-block.0):
+    liveins: $p0
+
+    ; CHECK-LABEL: name: testcase_negative_offset
+    ; CHECK: liveins: $p0
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: early-clobber $sp = frame-setup STRXpre killed $fp, $sp, -16 :: (store (s64) into %stack.2)
+    ; CHECK-NEXT: $sp = frame-setup ADDVL_XXI $sp, -4
+    ; CHECK-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x0c, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0x20, 0x92, 0x2e, 0x00, 0x1e, 0x22
+    ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $w29, -16
+    ; CHECK-NEXT: renamable $z0 = LDNF1B_IMM renamable $p0, $sp, -8 :: (load (s8) from %ir.object, align 2)
+    ; CHECK-NEXT: renamable $z0 = LDNF1B_H_IMM renamable $p0, $sp, -8 :: (load (s8) from %ir.object, align 2)
+    ; CHECK-NEXT: renamable $z0 = LDNF1B_S_IMM renamable $p0, $sp, -8 :: (load (s8) from %ir.object, align 2)
+    ; CHECK-NEXT: renamable $z0 = LDNF1B_D_IMM renamable $p0, $sp, -8 :: (load (s8) from %ir.object, align 2)
+    ; CHECK-NEXT: renamable $z0 = LDNF1SB_H_IMM renamable $p0, $sp, -8 :: (load (s8) from %ir.object, align 2)
+    ; CHECK-NEXT: renamable $z0 = LDNF1SB_S_IMM renamable $p0, $sp, -8 :: (load (s8) from %ir.object, align 2)
+    ; CHECK-NEXT: renamable $z0 = LDNF1SB_D_IMM renamable $p0, $sp, -8 :: (load (s8) from %ir.object, align 2)
+    ; CHECK-NEXT: renamable $z0 = LDNF1H_IMM renamable $p0, $sp, -8 :: (load (s16) from %ir.object)
+    ; CHECK-NEXT: renamable $z0 = LDNF1H_S_IMM renamable $p0, $sp, -8 :: (load (s16) from %ir.object)
+    ; CHECK-NEXT: renamable $z0 = LDNF1H_D_IMM renamable $p0, $sp, -8 :: (load (s16) from %ir.object)
+    ; CHECK-NEXT: renamable $z0 = LDNF1SH_S_IMM renamable $p0, $sp, -8 :: (load (s16) from %ir.object)
+    ; CHECK-NEXT: renamable $z0 = LDNF1SH_D_IMM renamable $p0, $sp, -8 :: (load (s16) from %ir.object)
+    ; CHECK-NEXT: renamable $z0 = LDNF1W_IMM renamable $p0, $sp, -8 :: (load (s32) from %ir.object, align 8)
+    ; CHECK-NEXT: renamable $z0 = LDNF1W_D_IMM renamable $p0, $sp, -8 :: (load (s32) from %ir.object, align 8)
+    ; CHECK-NEXT: renamable $z0 = LDNF1SW_D_IMM renamable $p0, $sp, -8 :: (load (s32) from %ir.object, align 8)
+    ; CHECK-NEXT: renamable $z0 = LDNF1D_IMM renamable $p0, $sp, -8 :: (load (s64) from %ir.object)
+    ; CHECK-NEXT: $sp = frame-destroy ADDVL_XXI $sp, 4
+    ; CHECK-NEXT: early-clobber $sp, $fp = frame-destroy LDRXpost $sp, 16 :: (load (s64) from %stack.2)
+    ; CHECK-NEXT: RET_ReallyLR implicit $z0
+    renamable $z0 = LDNF1B_IMM renamable $p0, %stack.1.object, -8 :: (load 1 from %ir.object, align 2)
+    renamable $z0 = LDNF1B_H_IMM renamable $p0, %stack.1.object, -8 :: (load 1 from %ir.object, align 2)
+    renamable $z0 = LDNF1B_S_IMM renamable $p0, %stack.1.object, -8 :: (load 1 from %ir.object, align 2)
+    renamable $z0 = LDNF1B_D_IMM renamable $p0, %stack.1.object, -8 :: (load 1 from %ir.object, align 2)
+    renamable $z0 = LDNF1SB_H_IMM renamable $p0, %stack.1.object, -8 :: (load 1 from %ir.object, align 2)
+    renamable $z0 = LDNF1SB_S_IMM renamable $p0, %stack.1.object, -8 :: (load 1 from %ir.object, align 2)
+    renamable $z0 = LDNF1SB_D_IMM renamable $p0, %stack.1.object, -8 :: (load 1 from %ir.object, align 2)
+    renamable $z0 = LDNF1H_IMM renamable $p0, %stack.1.object, -8 :: (load 2 from %ir.object, align 2)
+    renamable $z0 = LDNF1H_S_IMM renamable $p0, %stack.1.object, -8 :: (load 2 from %ir.object, align 2)
+    renamable $z0 = LDNF1H_D_IMM renamable $p0, %stack.1.object, -8 :: (load 2 from %ir.object, align 2)
+    renamable $z0 = LDNF1SH_S_IMM renamable $p0, %stack.1.object, -8 :: (load 2 from %ir.object, align 2)
+    renamable $z0 = LDNF1SH_D_IMM renamable $p0, %stack.1.object, -8 :: (load 2 from %ir.object, align 2)
+    renamable $z0 = LDNF1W_IMM renamable $p0, %stack.1.object, -8 :: (load 4 from %ir.object, align 8)
+    renamable $z0 = LDNF1W_D_IMM renamable $p0, %stack.1.object, -8 :: (load 4 from %ir.object, align 8)
+    renamable $z0 = LDNF1SW_D_IMM renamable $p0, %stack.1.object, -8 :: (load 4 from %ir.object, align 8)
+    renamable $z0 = LDNF1D_IMM renamable $p0, %stack.1.object, -8 :: (load 8 from %ir.object, align 8)
+    RET_ReallyLR implicit $z0
+...
+
+---
+name:            testcase_positive_offset_out_of_range
+tracksRegLiveness: true
+stack:
+  - { id: 0, name: dummy, type: default, offset: 0, size: 32, alignment: 16, stack-id: scalable-vector }
+  - { id: 1, name: object, type: default, offset: 0, size: 32, alignment: 16, stack-id: scalable-vector }
+body:             |
+  bb.0 (%ir-block.0):
+    liveins: $p0
+
+    ; CHECK-LABEL: name: testcase_positive_offset_out_of_range
+    ; CHECK: liveins: $p0
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: early-clobber $sp = frame-setup STRXpre killed $fp, $sp, -16 :: (store (s64) into %stack.2)
+    ; CHECK-NEXT: $sp = frame-setup ADDVL_XXI $sp, -4
+    ; CHECK-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x0c, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0x20, 0x92, 0x2e, 0x00, 0x1e, 0x22
+    ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $w29, -16
+    ; CHECK-NEXT: $x8 = ADDVL_XXI $sp, 1
+    ; CHECK-NEXT: renamable $z0 = LDNF1B_IMM renamable $p0, killed $x8, 7 :: (load (s8) from %ir.object, align 2)
+    ; CHECK-NEXT: $x8 = ADDPL_XXI $sp, 4
+    ; CHECK-NEXT: renamable $z0 = LDNF1B_H_IMM renamable $p0, killed $x8, 7 :: (load (s8) from %ir.object, align 2)
+    ; CHECK-NEXT: $x8 = ADDPL_XXI $sp, 2
+    ; CHECK-NEXT: renamable $z0 = LDNF1B_S_IMM renamable $p0, killed $x8, 7 :: (load (s8) from %ir.object, align 2)
+    ; CHECK-NEXT: $x8 = ADDPL_XXI $sp, 1
+    ; CHECK-NEXT: renamable $z0 = LDNF1B_D_IMM renamable $p0, killed $x8, 7 :: (load (s8) from %ir.object, align 2)
+    ; CHECK-NEXT: $x8 = ADDPL_XXI $sp, 4
+    ; CHECK-NEXT: renamable $z0 = LDNF1SB_H_IMM renamable $p0, killed $x8, 7 :: (load (s8) from %ir.object, align 2)
+    ; CHECK-NEXT: $x8 = ADDPL_XXI $sp, 2
+    ; CHECK-NEXT: renamable $z0 = LDNF1SB_S_IMM renamable $p0, killed $x8, 7 :: (load (s8) from %ir.object, align 2)
+    ; CHECK-NEXT: $x8 = ADDPL_XXI $sp, 1
+    ; CHECK-NEXT: renamable $z0 = LDNF1SB_D_IMM renamable $p0, killed $x8, 7 :: (load (s8) from %ir.object, align 2)
+    ; CHECK-NEXT: $x8 = ADDVL_XXI $sp, 1
+    ; CHECK-NEXT: renamable $z0 = LDNF1H_IMM renamable $p0, killed $x8, 7 :: (load (s16) from %ir.object)
+    ; CHECK-NEXT: $x8 = ADDPL_XXI $sp, 4
+    ; CHECK-NEXT: renamable $z0 = LDNF1H_S_IMM renamable $p0, killed $x8, 7 :: (load (s16) from %ir.object)
+    ; CHECK-NEXT: $x8 = ADDPL_XXI $sp, 2
+    ; CHECK-NEXT: renamable $z0 = LDNF1H_D_IMM renamable $p0, killed $x8, 7 :: (load (s16) from %ir.object)
+    ; CHECK-NEXT: $x8 = ADDPL_XXI $sp, 4
+    ; CHECK-NEXT: renamable $z0 = LDNF1SH_S_IMM renamable $p0, killed $x8, 7 :: (load (s16) from %ir.object)
+    ; CHECK-NEXT: $x8 = ADDPL_XXI $sp, 2
+    ; CHECK-NEXT: renamable $z0 = LDNF1SH_D_IMM renamable $p0, killed $x8, 7 :: (load (s16) from %ir.object)
+    ; CHECK-NEXT: $x8 = ADDVL_XXI $sp, 1
+    ; CHECK-NEXT: renamable $z0 = LDNF1W_IMM renamable $p0, killed $x8, 7 :: (load (s32) from %ir.object, align 8)
+    ; CHECK-NEXT: $x8 = ADDPL_XXI $sp, 4
+    ; CHECK-NEXT: renamable $z0 = LDNF1W_D_IMM renamable $p0, killed $x8, 7 :: (load (s32) from %ir.object, align 8)
+    ; CHECK-NEXT: $x8 = ADDPL_XXI $sp, 4
+    ; CHECK-NEXT: renamable $z0 = LDNF1SW_D_IMM renamable $p0, killed $x8, 7 :: (load (s32) from %ir.object, align 8)
+    ; CHECK-NEXT: $sp = frame-destroy ADDVL_XXI $sp, 4
+    ; CHECK-NEXT: early-clobber $sp, $fp = frame-destroy LDRXpost $sp, 16 :: (load (s64) from %stack.2)
+    ; CHECK-NEXT: RET_ReallyLR implicit $z0
+    renamable $z0 = LDNF1B_IMM renamable $p0, %stack.1.object, 8 :: (load 1 from %ir.object, align 2)
+    renamable $z0 = LDNF1B_H_IMM renamable $p0, %stack.1.object, 8 :: (load 1 from %ir.object, align 2)
+    renamable $z0 = LDNF1B_S_IMM renamable $p0, %stack.1.object, 8 :: (load 1 from %ir.object, align 2)
+    renamable $z0 = LDNF1B_D_IMM renamable $p0, %stack.1.object, 8 :: (load 1 from %ir.object, align 2)
+    renamable $z0 = LDNF1SB_H_IMM renamable $p0, %stack.1.object, 8 :: (load 1 from %ir.object, align 2)
+    renamable $z0 = LDNF1SB_S_IMM renamable $p0, %stack.1.object, 8 :: (load 1 from %ir.object, align 2)
+    renamable $z0 = LDNF1SB_D_IMM renamable $p0, %stack.1.object, 8 :: (load 1 from %ir.object, align 2)
+    renamable $z0 = LDNF1H_IMM renamable $p0, %stack.1.object, 8 :: (load 2 from %ir.object, align 2)
+    renamable $z0 = LDNF1H_S_IMM renamable $p0, %stack.1.object, 8 :: (load 2 from %ir.object, align 2)
+    renamable $z0 = LDNF1H_D_IMM renamable $p0, %stack.1.object, 8 :: (load 2 from %ir.object, align 2)
+    renamable $z0 = LDNF1SH_S_IMM renamable $p0, %stack.1.object, 8 :: (load 2 from %ir.object, align 2)
+    renamable $z0 = LDNF1SH_D_IMM renamable $p0, %stack.1.object, 8 :: (load 2 from %ir.object, align 2)
+    renamable $z0 = LDNF1W_IMM renamable $p0, %stack.1.object, 8 :: (load 4 from %ir.object, align 8)
+    renamable $z0 = LDNF1W_D_IMM renamable $p0, %stack.1.object, 8 :: (load 4 from %ir.object, align 8)
+    renamable $z0 = LDNF1SW_D_IMM renamable $p0, %stack.1.object, 8 :: (load 4 from %ir.object, align 8)
+    RET_ReallyLR implicit $z0
+...
+
+---
+name:            testcase_negative_offset_out_of_range
+tracksRegLiveness: true
+stack:
+  - { id: 0, name: dummy, type: default, offset: 0, size: 32, alignment: 16, stack-id: scalable-vector }
+  - { id: 1, name: object, type: default, offset: 0, size: 32, alignment: 16, stack-id: scalable-vector }
+body:             |
+  bb.0 (%ir-block.0):
+    liveins: $p0
+
+    ; CHECK-LABEL: name: testcase_negative_offset_out_of_range
+    ; CHECK: liveins: $p0
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: early-clobber $sp = frame-setup STRXpre killed $fp, $sp, -16 :: (store (s64) into %stack.2)
+    ; CHECK-NEXT: $sp = frame-setup ADDVL_XXI $sp, -4
+    ; CHECK-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x0c, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0x20, 0x92, 0x2e, 0x00, 0x1e, 0x22
+    ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $w29, -16
+    ; CHECK-NEXT: $x8 = ADDVL_XXI $sp, -1
+    ; CHECK-NEXT: renamable $z0 = LDNF1B_IMM renamable $p0, killed $x8, -8 :: (load (s8) from %ir.object, align 2)
+    ; CHECK-NEXT: $x8 = ADDPL_XXI $sp, -4
+    ; CHECK-NEXT: renamable $z0 = LDNF1B_H_IMM renamable $p0, killed $x8, -8 :: (load (s8) from %ir.object, align 2)
+    ; CHECK-NEXT: $x8 = ADDPL_XXI $sp, -2
+    ; CHECK-NEXT: renamable $z0 = LDNF1B_S_IMM renamable $p0, killed $x8, -8 :: (load (s8) from %ir.object, align 2)
+    ; CHECK-NEXT: $x8 = ADDPL_XXI $sp, -1
+    ; CHECK-NEXT: renamable $z0 = LDNF1B_D_IMM renamable $p0, killed $x8, -8 :: (load (s8) from %ir.object, align 2)
+    ; CHECK-NEXT: $x8 = ADDPL_XXI $sp, -4
+    ; CHECK-NEXT: renamable $z0 = LDNF1SB_H_IMM renamable $p0, killed $x8, -8 :: (load (s8) from %ir.object, align 2)
+    ; CHECK-NEXT: $x8 = ADDPL_XXI $sp, -2
+    ; CHECK-NEXT: renamable $z0 = LDNF1SB_S_IMM renamable $p0, killed $x8, -8 :: (load (s8) from %ir.object, align 2)
+    ; CHECK-NEXT: $x8 = ADDPL_XXI $sp, -1
+    ; CHECK-NEXT: renamable $z0 = LDNF1SB_D_IMM renamable $p0, killed $x8, -8 :: (load (s8) from %ir.object, align 2)
+    ; CHECK-NEXT: $x8 = ADDVL_XXI $sp, -1
+    ; CHECK-NEXT: renamable $z0 = LDNF1H_IMM renamable $p0, killed $x8, -8 :: (load (s16) from %ir.object)
+    ; CHECK-NEXT: $x8 = ADDPL_XXI $sp, -4
+    ; CHECK-NEXT: renamable $z0 = LDNF1H_S_IMM renamable $p0, killed $x8, -8 :: (load (s16) from %ir.object)
+    ; CHECK-NEXT: $x8 = ADDPL_XXI $sp, -2
+    ; CHECK-NEXT: renamable $z0 = LDNF1H_D_IMM renamable $p0, killed $x8, -8 :: (load (s16) from %ir.object)
+    ; CHECK-NEXT: $x8 = ADDPL_XXI $sp, -4
+    ; CHECK-NEXT: renamable $z0 = LDNF1SH_S_IMM renamable $p0, killed $x8, -8 :: (load (s16) from %ir.object)
+    ; CHECK-NEXT: $x8 = ADDPL_XXI $sp, -2
+    ; CHECK-NEXT: renamable $z0 = LDNF1SH_D_IMM renamable $p0, killed $x8, -8 :: (load (s16) from %ir.object)
+    ; CHECK-NEXT: $x8 = ADDVL_XXI $sp, -1
+    ; CHECK-NEXT: renamable $z0 = LDNF1W_IMM renamable $p0, killed $x8, -8 :: (load (s32) from %ir.object, align 8)
+    ; CHECK-NEXT: $x8 = ADDPL_XXI $sp, -4
+    ; CHECK-NEXT: renamable $z0 = LDNF1W_D_IMM renamable $p0, killed $x8, -8 :: (load (s32) from %ir.object, align 8)
+    ; CHECK-NEXT: $x8 = ADDPL_XXI $sp, -4
+    ; CHECK-NEXT: renamable $z0 = LDNF1SW_D_IMM renamable $p0, killed $x8, -8 :: (load (s32) from %ir.object, align 8)
+    ; CHECK-NEXT: $sp = frame-destroy ADDVL_XXI $sp, 4
+    ; CHECK-NEXT: early-clobber $sp, $fp = frame-destroy LDRXpost $sp, 16 :: (load (s64) from %stack.2)
+    ; CHECK-NEXT: RET_ReallyLR implicit $z0
+    renamable $z0 = LDNF1B_IMM renamable $p0, %stack.1.object, -9 :: (load 1 from %ir.object, align 2)
+    renamable $z0 = LDNF1B_H_IMM renamable $p0, %stack.1.object, -9 :: (load 1 from %ir.object, align 2)
+    renamable $z0 = LDNF1B_S_IMM renamable $p0, %stack.1.object, -9 :: (load 1 from %ir.object, align 2)
+    renamable $z0 = LDNF1B_D_IMM renamable $p0, %stack.1.object, -9 :: (load 1 from %ir.object, align 2)
+    renamable $z0 = LDNF1SB_H_IMM renamable $p0, %stack.1.object, -9 :: (load 1 from %ir.object, align 2)
+    renamable $z0 = LDNF1SB_S_IMM renamable $p0, %stack.1.object, -9 :: (load 1 from %ir.object, align 2)
+    renamable $z0 = LDNF1SB_D_IMM renamable $p0, %stack.1.object, -9 :: (load 1 from %ir.object, align 2)
+    renamable $z0 = LDNF1H_IMM renamable $p0, %stack.1.object, -9 :: (load 2 from %ir.object, align 2)
+    renamable $z0 = LDNF1H_S_IMM renamable $p0, %stack.1.object, -9 :: (load 2 from %ir.object, align 2)
+    renamable $z0 = LDNF1H_D_IMM renamable $p0, %stack.1.object, -9 :: (load 2 from %ir.object, align 2)
+    renamable $z0 = LDNF1SH_S_IMM renamable $p0, %stack.1.object, -9 :: (load 2 from %ir.object, align 2)
+    renamable $z0 = LDNF1SH_D_IMM renamable $p0, %stack.1.object, -9 :: (load 2 from %ir.object, align 2)
+    renamable $z0 = LDNF1W_IMM renamable $p0, %stack.1.object, -9 :: (load 4 from %ir.object, align 8)
+    renamable $z0 = LDNF1W_D_IMM renamable $p0, %stack.1.object, -9 :: (load 4 from %ir.object, align 8)
+    renamable $z0 = LDNF1SW_D_IMM renamable $p0, %stack.1.object, -9 :: (load 4 from %ir.object, align 8)
+    RET_ReallyLR implicit $z0
+...

llvm/test/CodeGen/AArch64/sve-ldstnt1.mir

+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve -run-pass=prologepilog -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s
+#
+# Test that prologepilog works for each of the LDNT1/STNT1 instructions for stack-based objects.
+#
+--- |
+  define void @testcase_positive_offset() {
+    %dummy = alloca <vscale x 2 x i64>, align 8
+    %object = alloca <vscale x 2 x i64>, align 8
+    ; Reads from %object at offset 7 * readsize
+    ret void
+  }
+  define void @testcase_negative_offset() {
+    %dummy = alloca <vscale x 2 x i64>, align 8
+    %object = alloca <vscale x 2 x i64>, align 8
+    ; Reads from %object at offset -8 * readsize
+    ret void
+  }
+
+  define void @testcase_positive_offset_out_of_range() {
+    %dummy = alloca <vscale x 2 x i64>, align 8
+    %object = alloca <vscale x 2 x i64>, align 8
+    ; Reads from %object at offset 8 * readsize
+    ret void
+  }
+  define void @testcase_negative_offset_out_of_range() {
+    %dummy = alloca <vscale x 2 x i64>, align 8
+    %object = alloca <vscale x 2 x i64>, align 8
+    ; Reads from %object at offset -9 * readsize
+    ret void
+  }
+...
+---
+name:            testcase_positive_offset
+tracksRegLiveness: true
+stack:
+  - { id: 0, name: dummy, type: default, offset: 0, size: 32, alignment: 16, stack-id: scalable-vector }
+  - { id: 1, name: object, type: default, offset: 0, size: 32, alignment: 16, stack-id: scalable-vector }
+body:             |
+  bb.0 (%ir-block.0):
+    liveins: $p0
+
+    ; CHECK-LABEL: name: testcase_positive_offset
+    ; CHECK: liveins: $p0
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: early-clobber $sp = frame-setup STRXpre killed $fp, $sp, -16 :: (store (s64) into %stack.2)
+    ; CHECK-NEXT: $sp = frame-setup ADDVL_XXI $sp, -4
+    ; CHECK-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x0c, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0x20, 0x92, 0x2e, 0x00, 0x1e, 0x22
+    ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $w29, -16
+    ; CHECK-NEXT: renamable $z0 = LDNT1B_ZRI renamable $p0, $sp, 7 :: (load (s8) from %ir.object, align 2)
+    ; CHECK-NEXT: renamable $z0 = LDNT1H_ZRI renamable $p0, $sp, 7 :: (load (s16) from %ir.object)
+    ; CHECK-NEXT: renamable $z0 = LDNT1W_ZRI renamable $p0, $sp, 7 :: (load (s32) from %ir.object, align 8)
+    ; CHECK-NEXT: renamable $z0 = LDNT1D_ZRI renamable $p0, $sp, 7 :: (load (s64) from %ir.object)
+    ; CHECK-NEXT: STNT1B_ZRI renamable $z0, renamable $p0, $sp, 7 :: (store (s8) into %ir.object, align 8)
+    ; CHECK-NEXT: STNT1H_ZRI renamable $z0, renamable $p0, $sp, 7 :: (store (s16) into %ir.object, align 8)
+    ; CHECK-NEXT: STNT1W_ZRI renamable $z0, renamable $p0, $sp, 7 :: (store (s32) into %ir.object, align 8)
+    ; CHECK-NEXT: STNT1D_ZRI renamable $z0, renamable $p0, $sp, 7 :: (store (s64) into %ir.object)
+    ; CHECK-NEXT: $sp = frame-destroy ADDVL_XXI $sp, 4
+    ; CHECK-NEXT: early-clobber $sp, $fp = frame-destroy LDRXpost $sp, 16 :: (load (s64) from %stack.2)
+    ; CHECK-NEXT: RET_ReallyLR implicit $z0
+    renamable $z0 = LDNT1B_ZRI renamable $p0, %stack.1.object, 7 :: (load 1 from %ir.object, align 2)
+    renamable $z0 = LDNT1H_ZRI renamable $p0, %stack.1.object, 7 :: (load 2 from %ir.object, align 2)
+    renamable $z0 = LDNT1W_ZRI renamable $p0, %stack.1.object, 7 :: (load 4 from %ir.object, align 8)
+    renamable $z0 = LDNT1D_ZRI renamable $p0, %stack.1.object, 7 :: (load 8 from %ir.object, align 8)
+    STNT1B_ZRI renamable $z0, renamable $p0, %stack.1.object, 7 :: (store 1 into %ir.object, align 8)
+    STNT1H_ZRI renamable $z0, renamable $p0, %stack.1.object, 7 :: (store 2 into %ir.object, align 8)
+    STNT1W_ZRI renamable $z0, renamable $p0, %stack.1.object, 7 :: (store 4 into %ir.object, align 8)
+    STNT1D_ZRI renamable $z0, renamable $p0, %stack.1.object, 7 :: (store 8 into %ir.object, align 8)
+    RET_ReallyLR implicit $z0
+...
+
+---
+name:            testcase_negative_offset
+tracksRegLiveness: true
+stack:
+  - { id: 0, name: dummy, type: default, offset: 0, size: 32, alignment: 16, stack-id: scalable-vector }
+  - { id: 1, name: object, type: default, offset: 0, size: 32, alignment: 16, stack-id: scalable-vector }
+body:             |
+  bb.0 (%ir-block.0):
+    liveins: $p0
+
+    ; CHECK-LABEL: name: testcase_negative_offset
+    ; CHECK: liveins: $p0
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: early-clobber $sp = frame-setup STRXpre killed $fp, $sp, -16 :: (store (s64) into %stack.2)
+    ; CHECK-NEXT: $sp = frame-setup ADDVL_XXI $sp, -4
+    ; CHECK-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x0c, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0x20, 0x92, 0x2e, 0x00, 0x1e, 0x22
+    ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $w29, -16
+    ; CHECK-NEXT: renamable $z0 = LDNT1B_ZRI renamable $p0, $sp, -8 :: (load (s8) from %ir.object, align 2)
+    ; CHECK-NEXT: renamable $z0 = LDNT1H_ZRI renamable $p0, $sp, -8 :: (load (s16) from %ir.object)
+    ; CHECK-NEXT: renamable $z0 = LDNT1W_ZRI renamable $p0, $sp, -8 :: (load (s32) from %ir.object)
+    ; CHECK-NEXT: renamable $z0 = LDNT1D_ZRI renamable $p0, $sp, -8 :: (load (s64) from %ir.object)
+    ; CHECK-NEXT: STNT1B_ZRI renamable $z0, renamable $p0, $sp, -8 :: (store (s8) into %ir.object, align 8)
+    ; CHECK-NEXT: STNT1H_ZRI renamable $z0, renamable $p0, $sp, -8 :: (store (s16) into %ir.object, align 8)
+    ; CHECK-NEXT: STNT1W_ZRI renamable $z0, renamable $p0, $sp, -8 :: (store (s32) into %ir.object, align 8)
+    ; CHECK-NEXT: STNT1D_ZRI renamable $z0, renamable $p0, $sp, -8 :: (store (s64) into %ir.object)
+    ; CHECK-NEXT: $sp = frame-destroy ADDVL_XXI $sp, 4
+    ; CHECK-NEXT: early-clobber $sp, $fp = frame-destroy LDRXpost $sp, 16 :: (load (s64) from %stack.2)
+    ; CHECK-NEXT: RET_ReallyLR implicit $z0
+    renamable $z0 = LDNT1B_ZRI renamable $p0, %stack.1.object, -8 :: (load 1 from %ir.object, align 2)
+    renamable $z0 = LDNT1H_ZRI renamable $p0, %stack.1.object, -8 :: (load 2 from %ir.object, align 2)
+    renamable $z0 = LDNT1W_ZRI renamable $p0, %stack.1.object, -8 :: (load 4 from %ir.object, align 4)
+    renamable $z0 = LDNT1D_ZRI renamable $p0, %stack.1.object, -8 :: (load 8 from %ir.object, align 8)
+    STNT1B_ZRI renamable $z0, renamable $p0, %stack.1.object, -8 :: (store 1 into %ir.object, align 8)
+    STNT1H_ZRI renamable $z0, renamable $p0, %stack.1.object, -8 :: (store 2 into %ir.object, align 8)
+    STNT1W_ZRI renamable $z0, renamable $p0, %stack.1.object, -8 :: (store 4 into %ir.object, align 8)
+    STNT1D_ZRI renamable $z0, renamable $p0, %stack.1.object, -8 :: (store 8 into %ir.object, align 8)
+    RET_ReallyLR implicit $z0
+...
+
+---
+name:            testcase_positive_offset_out_of_range
+tracksRegLiveness: true
+stack:
+  - { id: 0, name: dummy, type: default, offset: 0, size: 32, alignment: 16, stack-id: scalable-vector }
+  - { id: 1, name: object, type: default, offset: 0, size: 32, alignment: 16, stack-id: scalable-vector }
+body:             |
+  bb.0 (%ir-block.0):
+    liveins: $p0
+
+    ; CHECK-LABEL: name: testcase_positive_offset_out_of_range
+    ; CHECK: liveins: $p0
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: early-clobber $sp = frame-setup STRXpre killed $fp, $sp, -16 :: (store (s64) into %stack.2)
+    ; CHECK-NEXT: $sp = frame-setup ADDVL_XXI $sp, -4
+    ; CHECK-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x0c, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0x20, 0x92, 0x2e, 0x00, 0x1e, 0x22
+    ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $w29, -16
+    ; CHECK-NEXT: $x8 = ADDVL_XXI $sp, 1
+    ; CHECK-NEXT: renamable $z0 = LDNT1B_ZRI renamable $p0, killed $x8, 7 :: (load (s8) from %ir.object, align 2)
+    ; CHECK-NEXT: $x8 = ADDVL_XXI $sp, 1
+    ; CHECK-NEXT: renamable $z0 = LDNT1H_ZRI renamable $p0, killed $x8, 7 :: (load (s16) from %ir.object)
+    ; CHECK-NEXT: $x8 = ADDVL_XXI $sp, 1
+    ; CHECK-NEXT: renamable $z0 = LDNT1W_ZRI renamable $p0, killed $x8, 7 :: (load (s32) from %ir.object)
+    ; CHECK-NEXT: $x8 = ADDVL_XXI $sp, 1
+    ; CHECK-NEXT: renamable $z0 = LDNT1D_ZRI renamable $p0, killed $x8, 7 :: (load (s64) from %ir.object)
+    ; CHECK-NEXT: $x8 = ADDVL_XXI $sp, 1
+    ; CHECK-NEXT: STNT1B_ZRI renamable $z0, renamable $p0, killed $x8, 7 :: (store (s8) into %ir.object, align 8)
+    ; CHECK-NEXT: $x8 = ADDVL_XXI $sp, 1
+    ; CHECK-NEXT: STNT1H_ZRI renamable $z0, renamable $p0, killed $x8, 7 :: (store (s16) into %ir.object, align 8)
+    ; CHECK-NEXT: $x8 = ADDVL_XXI $sp, 1
+    ; CHECK-NEXT: STNT1W_ZRI renamable $z0, renamable $p0, killed $x8, 7 :: (store (s32) into %ir.object, align 8)
+    ; CHECK-NEXT: $x8 = ADDVL_XXI $sp, 1
+    ; CHECK-NEXT: STNT1D_ZRI renamable $z0, renamable $p0, killed $x8, 7 :: (store (s64) into %ir.object)
+    ; CHECK-NEXT: $sp = frame-destroy ADDVL_XXI $sp, 4
+    ; CHECK-NEXT: early-clobber $sp, $fp = frame-destroy LDRXpost $sp, 16 :: (load (s64) from %stack.2)
+    ; CHECK-NEXT: RET_ReallyLR implicit $z0
+    renamable $z0 = LDNT1B_ZRI renamable $p0, %stack.1.object, 8 :: (load 1 from %ir.object, align 2)
+    renamable $z0 = LDNT1H_ZRI renamable $p0, %stack.1.object, 8 :: (load 2 from %ir.object, align 2)
+    renamable $z0 = LDNT1W_ZRI renamable $p0, %stack.1.object, 8 :: (load 4 from %ir.object, align 4)
+    renamable $z0 = LDNT1D_ZRI renamable $p0, %stack.1.object, 8 :: (load 8 from %ir.object, align 8)
+    STNT1B_ZRI renamable $z0, renamable $p0, %stack.1.object, 8 :: (store 1 into %ir.object, align 8)
+    STNT1H_ZRI renamable $z0, renamable $p0, %stack.1.object, 8 :: (store 2 into %ir.object, align 8)
+    STNT1W_ZRI renamable $z0, renamable $p0, %stack.1.object, 8 :: (store 4 into %ir.object, align 8)
+    STNT1D_ZRI renamable $z0, renamable $p0, %stack.1.object, 8 :: (store 8 into %ir.object, align 8)
+    RET_ReallyLR implicit $z0
+...
+
+---
+name:            testcase_negative_offset_out_of_range
+tracksRegLiveness: true
+stack:
+  - { id: 0, name: dummy, type: default, offset: 0, size: 32, alignment: 16, stack-id: scalable-vector }
+  - { id: 1, name: object, type: default, offset: 0, size: 32, alignment: 16, stack-id: scalable-vector }
+body:             |
+  bb.0 (%ir-block.0):
+    liveins: $p0
+
+    ; CHECK-LABEL: name: testcase_negative_offset_out_of_range
+    ; CHECK: liveins: $p0
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: early-clobber $sp = frame-setup STRXpre killed $fp, $sp, -16 :: (store (s64) into %stack.2)
+    ; CHECK-NEXT: $sp = frame-setup ADDVL_XXI $sp, -4
+    ; CHECK-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x0c, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0x20, 0x92, 0x2e, 0x00, 0x1e, 0x22
+    ; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $w29, -16
+    ; CHECK-NEXT: $x8 = ADDVL_XXI $sp, -1
+    ; CHECK-NEXT: renamable $z0 = LDNT1B_ZRI renamable $p0, killed $x8, -8 :: (load (s8) from %ir.object, align 2)
+    ; CHECK-NEXT: $x8 = ADDVL_XXI $sp, -1
+    ; CHECK-NEXT: renamable $z0 = LDNT1H_ZRI renamable $p0, killed $x8, -8 :: (load (s16) from %ir.object)
+    ; CHECK-NEXT: $x8 = ADDVL_XXI $sp, -1
+    ; CHECK-NEXT: renamable $z0 = LDNT1W_ZRI renamable $p0, killed $x8, -8 :: (load (s32) from %ir.object)
+    ; CHECK-NEXT: $x8 = ADDVL_XXI $sp, -1
+    ; CHECK-NEXT: renamable $z0 = LDNT1D_ZRI renamable $p0, killed $x8, -8 :: (load (s64) from %ir.object)
+    ; CHECK-NEXT: $x8 = ADDVL_XXI $sp, -1
+    ; CHECK-NEXT: STNT1B_ZRI renamable $z0, renamable $p0, killed $x8, -8 :: (store (s8) into %ir.object, align 8)
+    ; CHECK-NEXT: $x8 = ADDVL_XXI $sp, -1
+    ; CHECK-NEXT: STNT1H_ZRI renamable $z0, renamable $p0, killed $x8, -8 :: (store (s16) into %ir.object, align 8)
+    ; CHECK-NEXT: $x8 = ADDVL_XXI $sp, -1
+    ; CHECK-NEXT: STNT1W_ZRI renamable $z0, renamable $p0, killed $x8, -8 :: (store (s32) into %ir.object, align 8)
+    ; CHECK-NEXT: $x8 = ADDVL_XXI $sp, -1
+    ; CHECK-NEXT: STNT1D_ZRI renamable $z0, renamable $p0, killed $x8, -8 :: (store (s64) into %ir.object)
+    ; CHECK-NEXT: $sp = frame-destroy ADDVL_XXI $sp, 4
+    ; CHECK-NEXT: early-clobber $sp, $fp = frame-destroy LDRXpost $sp, 16 :: (load (s64) from %stack.2)
+    ; CHECK-NEXT: RET_ReallyLR implicit $z0
+    renamable $z0 = LDNT1B_ZRI renamable $p0, %stack.1.object, -9 :: (load 1 from %ir.object, align 2)
+    renamable $z0 = LDNT1H_ZRI renamable $p0, %stack.1.object, -9 :: (load 2 from %ir.object, align 2)
+    renamable $z0 = LDNT1W_ZRI renamable $p0, %stack.1.object, -9 :: (load 4 from %ir.object, align 4)
+    renamable $z0 = LDNT1D_ZRI renamable $p0, %stack.1.object, -9 :: (load 8 from %ir.object, align 8)
+    STNT1B_ZRI renamable $z0, renamable $p0, %stack.1.object, -9 :: (store 1 into %ir.object, align 8)
+    STNT1H_ZRI renamable $z0, renamable $p0, %stack.1.object, -9 :: (store 2 into %ir.object, align 8)
+    STNT1W_ZRI renamable $z0, renamable $p0, %stack.1.object, -9 :: (store 4 into %ir.object, align 8)
+    STNT1D_ZRI renamable $z0, renamable $p0, %stack.1.object, -9 :: (store 8 into %ir.object, align 8)
+    RET_ReallyLR implicit $z0
+...

llvm/test/CodeGen/AArch64/sve-split-extract-elt.ll

 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    str x29, [sp, #-16]! // 8-byte Folded Spill
 ; CHECK-NEXT:    addvl sp, sp, #-2
 ; CHECK-NEXT:    .cfi_escape 0x0f, 0x0c, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 16 + 16 * VG
 ; CHECK-NEXT:    .cfi_offset w29, -16
 ; CHECK-NEXT:    mov x8, #-1
 ; CHECK-NEXT:    // kill: def $w0 killed $w0 def $x0
 ; CHECK-NEXT:    sxtw x9, w0
-; CHECK-NEXT:    mov x10, sp
 ; CHECK-NEXT:    ptrue p0.b
+; CHECK-NEXT:    st1b { z1.b }, p0, [sp, #1, mul vl]
+; CHECK-NEXT:    st1b { z0.b }, p0, [sp]
 ; CHECK-NEXT:    addvl x8, x8, #2
 ; CHECK-NEXT:    cmp x9, x8
-; CHECK-NEXT:    st1b { z1.b }, p0, [x10, #1, mul vl]
 ; CHECK-NEXT:    csel x8, x9, x8, lo
-; CHECK-NEXT:    st1b { z0.b }, p0, [sp]
-; CHECK-NEXT:    ldrb w0, [x10, x8]
+; CHECK-NEXT:    mov x9, sp
+; CHECK-NEXT:    ldrb w0, [x9, x8]
 ; CHECK-NEXT:    addvl sp, sp, #2
 ; CHECK-NEXT:    ldr x29, [sp], #16 // 8-byte Folded Reload
 ; CHECK-NEXT:    ret
   %ext = extractelement <vscale x 32 x i8> %a, i32 %idx
   ret i8 %ext
 }
 
 define i16 @split_extract_16i16_idx(<vscale x 16 x i16> %a, i32 %idx) {
 ; CHECK-LABEL: split_extract_16i16_idx:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    str x29, [sp, #-16]! // 8-byte Folded Spill
 ; CHECK-NEXT:    addvl sp, sp, #-2
 ; CHECK-NEXT:    .cfi_escape 0x0f, 0x0c, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 16 + 16 * VG
 ; CHECK-NEXT:    .cfi_offset w29, -16
 ; CHECK-NEXT:    mov x8, #-1
 ; CHECK-NEXT:    // kill: def $w0 killed $w0 def $x0
 ; CHECK-NEXT:    sxtw x9, w0
-; CHECK-NEXT:    mov x10, sp
 ; CHECK-NEXT:    ptrue p0.h
+; CHECK-NEXT:    st1h { z1.h }, p0, [sp, #1, mul vl]
+; CHECK-NEXT:    st1h { z0.h }, p0, [sp]
 ; CHECK-NEXT:    addvl x8, x8, #1
 ; CHECK-NEXT:    cmp x9, x8
-; CHECK-NEXT:    st1h { z1.h }, p0, [x10, #1, mul vl]
 ; CHECK-NEXT:    csel x8, x9, x8, lo
-; CHECK-NEXT:    st1h { z0.h }, p0, [sp]
-; CHECK-NEXT:    ldrh w0, [x10, x8, lsl #1]
+; CHECK-NEXT:    mov x9, sp
+; CHECK-NEXT:    ldrh w0, [x9, x8, lsl #1]
 ; CHECK-NEXT:    addvl sp, sp, #2
 ; CHECK-NEXT:    ldr x29, [sp], #16 // 8-byte Folded Reload
 ; CHECK-NEXT:    ret
   %ext = extractelement <vscale x 16 x i16> %a, i32 %idx
   ret i16 %ext
 }
 
 define i32 @split_extract_8i32_idx(<vscale x 8 x i32> %a, i32 %idx) {
 ; CHECK-LABEL: split_extract_8i32_idx:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    str x29, [sp, #-16]! // 8-byte Folded Spill
 ; CHECK-NEXT:    addvl sp, sp, #-2
 ; CHECK-NEXT:    .cfi_escape 0x0f, 0x0c, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 16 + 16 * VG
 ; CHECK-NEXT:    .cfi_offset w29, -16
 ; CHECK-NEXT:    cnth x8
 ; CHECK-NEXT:    // kill: def $w0 killed $w0 def $x0
 ; CHECK-NEXT:    sxtw x9, w0
 ; CHECK-NEXT:    sub x8, x8, #1
-; CHECK-NEXT:    mov x10, sp
-; CHECK-NEXT:    cmp x9, x8
 ; CHECK-NEXT:    ptrue p0.s
+; CHECK-NEXT:    cmp x9, x8
+; CHECK-NEXT:    st1w { z1.s }, p0, [sp, #1, mul vl]
 ; CHECK-NEXT:    csel x8, x9, x8, lo
-; CHECK-NEXT:    st1w { z1.s }, p0, [x10, #1, mul vl]
+; CHECK-NEXT:    mov x9, sp
 ; CHECK-NEXT:    st1w { z0.s }, p0, [sp]
-; CHECK-NEXT:    ldr w0, [x10, x8, lsl #2]
+; CHECK-NEXT:    ldr w0, [x9, x8, lsl #2]
 ; CHECK-NEXT:    addvl sp, sp, #2
 ; CHECK-NEXT:    ldr x29, [sp], #16 // 8-byte Folded Reload
 ; CHECK-NEXT:    ret
   %ext = extractelement <vscale x 8 x i32> %a, i32 %idx
   ret i32 %ext
 }
 
 define i64 @split_extract_8i64_idx(<vscale x 8 x i64> %a, i32 %idx) {
 ; CHECK-LABEL: split_extract_8i64_idx:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    str x29, [sp, #-16]! // 8-byte Folded Spill
 ; CHECK-NEXT:    addvl sp, sp, #-4
 ; CHECK-NEXT:    .cfi_escape 0x0f, 0x0c, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0x20, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 16 + 32 * VG
 ; CHECK-NEXT:    .cfi_offset w29, -16
-; CHECK-NEXT:    cnth x9
+; CHECK-NEXT:    cnth x8
 ; CHECK-NEXT:    // kill: def $w0 killed $w0 def $x0
-; CHECK-NEXT:    sxtw x10, w0
-; CHECK-NEXT:    sub x9, x9, #1
-; CHECK-NEXT:    mov x8, sp
-; CHECK-NEXT:    cmp x10, x9
+; CHECK-NEXT:    sxtw x9, w0
+; CHECK-NEXT:    sub x8, x8, #1
 ; CHECK-NEXT:    ptrue p0.d
-; CHECK-NEXT:    csel x9, x10, x9, lo
-; CHECK-NEXT:    st1d { z3.d }, p0, [x8, #3, mul vl]
-; CHECK-NEXT:    st1d { z2.d }, p0, [x8, #2, mul vl]
-; CHECK-NEXT:    st1d { z1.d }, p0, [x8, #1, mul vl]
+; CHECK-NEXT:    cmp x9, x8
+; CHECK-NEXT:    st1d { z3.d }, p0, [sp, #3, mul vl]
+; CHECK-NEXT:    csel x8, x9, x8, lo
+; CHECK-NEXT:    mov x9, sp
+; CHECK-NEXT:    st1d { z2.d }, p0, [sp, #2, mul vl]
+; CHECK-NEXT:    st1d { z1.d }, p0, [sp, #1, mul vl]
 ; CHECK-NEXT:    st1d { z0.d }, p0, [sp]
-; CHECK-NEXT:    ldr x0, [x8, x9, lsl #3]
+; CHECK-NEXT:    ldr x0, [x9, x8, lsl #3]
 ; CHECK-NEXT:    addvl sp, sp, #4
 ; CHECK-NEXT:    ldr x29, [sp], #16 // 8-byte Folded Reload
 ; CHECK-NEXT:    ret
   %ext = extractelement <vscale x 8 x i64> %a, i32 %idx
   ret i64 %ext
 }
 
 ; EXTRACT VECTOR ELT, CONSTANT IDX

 define i16 @split_extract_16i16(<vscale x 16 x i16> %a) {
 ; CHECK-LABEL: split_extract_16i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    str x29, [sp, #-16]! // 8-byte Folded Spill
 ; CHECK-NEXT:    addvl sp, sp, #-2
 ; CHECK-NEXT:    .cfi_escape 0x0f, 0x0c, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 16 + 16 * VG
 ; CHECK-NEXT:    .cfi_offset w29, -16
 ; CHECK-NEXT:    mov x8, #-1
-; CHECK-NEXT:    mov x9, sp
-; CHECK-NEXT:    mov w10, #128
+; CHECK-NEXT:    mov w9, #128
 ; CHECK-NEXT:    ptrue p0.h
+; CHECK-NEXT:    st1h { z1.h }, p0, [sp, #1, mul vl]
+; CHECK-NEXT:    st1h { z0.h }, p0, [sp]
 ; CHECK-NEXT:    addvl x8, x8, #1
-; CHECK-NEXT:    st1h { z1.h }, p0, [x9, #1, mul vl]
 ; CHECK-NEXT:    cmp x8, #128
-; CHECK-NEXT:    st1h { z0.h }, p0, [sp]
-; CHECK-NEXT:    csel x8, x8, x10, lo
+; CHECK-NEXT:    csel x8, x8, x9, lo
+; CHECK-NEXT:    mov x9, sp
 ; CHECK-NEXT:    ldrh w0, [x9, x8, lsl #1]
 ; CHECK-NEXT:    addvl sp, sp, #2
 ; CHECK-NEXT:    ldr x29, [sp], #16 // 8-byte Folded Reload
 ; CHECK-NEXT:    ret
   %ext = extractelement <vscale x 16 x i16> %a, i32 128
   ret i16 %ext
 }
 
 define i32 @split_extract_16i32(<vscale x 16 x i32> %a) {
 ; CHECK-LABEL: split_extract_16i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    str x29, [sp, #-16]! // 8-byte Folded Spill
 ; CHECK-NEXT:    addvl sp, sp, #-4
 ; CHECK-NEXT:    .cfi_escape 0x0f, 0x0c, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0x20, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 16 + 32 * VG
 ; CHECK-NEXT:    .cfi_offset w29, -16
 ; CHECK-NEXT:    mov x8, #-1
-; CHECK-NEXT:    mov w10, #34464
-; CHECK-NEXT:    movk w10, #1, lsl #16
-; CHECK-NEXT:    mov x9, sp
+; CHECK-NEXT:    mov w9, #34464
+; CHECK-NEXT:    movk w9, #1, lsl #16
 ; CHECK-NEXT:    ptrue p0.s
+; CHECK-NEXT:    st1w { z3.s }, p0, [sp, #3, mul vl]
+; CHECK-NEXT:    st1w { z2.s }, p0, [sp, #2, mul vl]
 ; CHECK-NEXT:    addvl x8, x8, #1
-; CHECK-NEXT:    cmp x8, x10
-; CHECK-NEXT:    st1w { z3.s }, p0, [x9, #3, mul vl]
-; CHECK-NEXT:    csel x8, x8, x10, lo
-; CHECK-NEXT:    st1w { z2.s }, p0, [x9, #2, mul vl]
-; CHECK-NEXT:    st1w { z1.s }, p0, [x9, #1, mul vl]
+; CHECK-NEXT:    st1w { z1.s }, p0, [sp, #1, mul vl]
+; CHECK-NEXT:    cmp x8, x9
 ; CHECK-NEXT:    st1w { z0.s }, p0, [sp]
+; CHECK-NEXT:    csel x8, x8, x9, lo
+; CHECK-NEXT:    mov x9, sp
 ; CHECK-NEXT:    ldr w0, [x9, x8, lsl #2]
 ; CHECK-NEXT:    addvl sp, sp, #4
 ; CHECK-NEXT:    ldr x29, [sp], #16 // 8-byte Folded Reload
 ; CHECK-NEXT:    ret
   %ext = extractelement <vscale x 16 x i32> %a, i32 100000
   ret i32 %ext
 }
 
 define i64 @split_extract_4i64(<vscale x 4 x i64> %a) {
 ; CHECK-LABEL: split_extract_4i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    str x29, [sp, #-16]! // 8-byte Folded Spill
 ; CHECK-NEXT:    addvl sp, sp, #-2
 ; CHECK-NEXT:    .cfi_escape 0x0f, 0x0c, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 16 + 16 * VG
 ; CHECK-NEXT:    .cfi_offset w29, -16
 ; CHECK-NEXT:    cntw x8
-; CHECK-NEXT:    mov x9, sp
+; CHECK-NEXT:    mov w9, #10
 ; CHECK-NEXT:    sub x8, x8, #1
-; CHECK-NEXT:    mov w10, #10
-; CHECK-NEXT:    cmp x8, #10
 ; CHECK-NEXT:    ptrue p0.d
-; CHECK-NEXT:    csel x8, x8, x10, lo
-; CHECK-NEXT:    st1d { z1.d }, p0, [x9, #1, mul vl]
+; CHECK-NEXT:    cmp x8, #10
+; CHECK-NEXT:    st1d { z1.d }, p0, [sp, #1, mul vl]
+; CHECK-NEXT:    csel x8, x8, x9, lo
+; CHECK-NEXT:    mov x9, sp
 ; CHECK-NEXT:    st1d { z0.d }, p0, [sp]
 ; CHECK-NEXT:    ldr x0, [x9, x8, lsl #3]
 ; CHECK-NEXT:    addvl sp, sp, #2
 ; CHECK-NEXT:    ldr x29, [sp], #16 // 8-byte Folded Reload
 ; CHECK-NEXT:    ret
   %ext = extractelement <vscale x 4 x i64> %a, i32 10
   ret i64 %ext
 }

llvm/test/CodeGen/AArch64/sve-split-insert-elt.ll

 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    str x29, [sp, #-16]! // 8-byte Folded Spill
 ; CHECK-NEXT:    addvl sp, sp, #-2
 ; CHECK-NEXT:    .cfi_escape 0x0f, 0x0c, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 16 + 16 * VG
 ; CHECK-NEXT:    .cfi_offset w29, -16
 ; CHECK-NEXT:    mov x8, #-1
 ; CHECK-NEXT:    mov x9, sp
 ; CHECK-NEXT:    ptrue p0.b
+; CHECK-NEXT:    st1b { z1.b }, p0, [sp, #1, mul vl]
+; CHECK-NEXT:    st1b { z0.b }, p0, [sp]
 ; CHECK-NEXT:    addvl x8, x8, #2
-; CHECK-NEXT:    st1b { z1.b }, p0, [x9, #1, mul vl]
 ; CHECK-NEXT:    cmp x1, x8
-; CHECK-NEXT:    st1b { z0.b }, p0, [sp]
 ; CHECK-NEXT:    csel x8, x1, x8, lo
 ; CHECK-NEXT:    strb w0, [x9, x8]
-; CHECK-NEXT:    ld1b { z1.b }, p0/z, [x9, #1, mul vl]
 ; CHECK-NEXT:    ld1b { z0.b }, p0/z, [sp]
+; CHECK-NEXT:    ld1b { z1.b }, p0/z, [sp, #1, mul vl]
 ; CHECK-NEXT:    addvl sp, sp, #2
 ; CHECK-NEXT:    ldr x29, [sp], #16 // 8-byte Folded Reload
 ; CHECK-NEXT:    ret
   %ins = insertelement <vscale x 32 x i8> %a, i8 %elt, i64 %idx
   ret <vscale x 32 x i8> %ins
 }
 
 define <vscale x 8 x float> @split_insert_8f32_idx(<vscale x 8 x float> %a, float %elt, i64 %idx) {
 ; CHECK-LABEL: split_insert_8f32_idx:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    str x29, [sp, #-16]! // 8-byte Folded Spill
 ; CHECK-NEXT:    addvl sp, sp, #-2
 ; CHECK-NEXT:    .cfi_escape 0x0f, 0x0c, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 16 + 16 * VG
 ; CHECK-NEXT:    .cfi_offset w29, -16
 ; CHECK-NEXT:    cnth x8
 ; CHECK-NEXT:    mov x9, sp
 ; CHECK-NEXT:    sub x8, x8, #1
 ; CHECK-NEXT:    ptrue p0.s
 ; CHECK-NEXT:    cmp x0, x8
+; CHECK-NEXT:    st1w { z1.s }, p0, [sp, #1, mul vl]
 ; CHECK-NEXT:    csel x8, x0, x8, lo
-; CHECK-NEXT:    st1w { z1.s }, p0, [x9, #1, mul vl]
 ; CHECK-NEXT:    st1w { z0.s }, p0, [sp]
 ; CHECK-NEXT:    str s2, [x9, x8, lsl #2]
-; CHECK-NEXT:    ld1w { z1.s }, p0/z, [x9, #1, mul vl]
 ; CHECK-NEXT:    ld1w { z0.s }, p0/z, [sp]
+; CHECK-NEXT:    ld1w { z1.s }, p0/z, [sp, #1, mul vl]
 ; CHECK-NEXT:    addvl sp, sp, #2
 ; CHECK-NEXT:    ldr x29, [sp], #16 // 8-byte Folded Reload
 ; CHECK-NEXT:    ret
   %ins = insertelement <vscale x 8 x float> %a, float %elt, i64 %idx
   ret <vscale x 8 x float> %ins
 }
 
 define <vscale x 8 x i64> @split_insert_8i64_idx(<vscale x 8 x i64> %a, i64 %elt, i64 %idx) {
 ; CHECK-LABEL: split_insert_8i64_idx:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    str x29, [sp, #-16]! // 8-byte Folded Spill
 ; CHECK-NEXT:    addvl sp, sp, #-4
 ; CHECK-NEXT:    .cfi_escape 0x0f, 0x0c, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0x20, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 16 + 32 * VG
 ; CHECK-NEXT:    .cfi_offset w29, -16
 ; CHECK-NEXT:    cnth x8
 ; CHECK-NEXT:    mov x9, sp
 ; CHECK-NEXT:    sub x8, x8, #1
 ; CHECK-NEXT:    ptrue p0.d
 ; CHECK-NEXT:    cmp x1, x8
+; CHECK-NEXT:    st1d { z3.d }, p0, [sp, #3, mul vl]
 ; CHECK-NEXT:    csel x8, x1, x8, lo
-; CHECK-NEXT:    st1d { z3.d }, p0, [x9, #3, mul vl]
-; CHECK-NEXT:    st1d { z2.d }, p0, [x9, #2, mul vl]
-; CHECK-NEXT:    st1d { z1.d }, p0, [x9, #1, mul vl]
+; CHECK-NEXT:    st1d { z2.d }, p0, [sp, #2, mul vl]
+; CHECK-NEXT:    st1d { z1.d }, p0, [sp, #1, mul vl]
 ; CHECK-NEXT:    st1d { z0.d }, p0, [sp]
 ; CHECK-NEXT:    str x0, [x9, x8, lsl #3]
-; CHECK-NEXT:    ld1d { z1.d }, p0/z, [x9, #1, mul vl]
-; CHECK-NEXT:    ld1d { z2.d }, p0/z, [x9, #2, mul vl]
-; CHECK-NEXT:    ld1d { z3.d }, p0/z, [x9, #3, mul vl]
 ; CHECK-NEXT:    ld1d { z0.d }, p0/z, [sp]
+; CHECK-NEXT:    ld1d { z1.d }, p0/z, [sp, #1, mul vl]
+; CHECK-NEXT:    ld1d { z2.d }, p0/z, [sp, #2, mul vl]
+; CHECK-NEXT:    ld1d { z3.d }, p0/z, [sp, #3, mul vl]
 ; CHECK-NEXT:    addvl sp, sp, #4
 ; CHECK-NEXT:    ldr x29, [sp], #16 // 8-byte Folded Reload
 ; CHECK-NEXT:    ret
   %ins = insertelement <vscale x 8 x i64> %a, i64 %elt, i64 %idx
   ret <vscale x 8 x i64> %ins
 }
 
 ; INSERT VECTOR ELT, CONSTANT IDX

 define <vscale x 32 x i16> @split_insert_32i16(<vscale x 32 x i16> %a, i16 %elt) {
 ; CHECK-LABEL: split_insert_32i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    str x29, [sp, #-16]! // 8-byte Folded Spill
 ; CHECK-NEXT:    addvl sp, sp, #-4
 ; CHECK-NEXT:    .cfi_escape 0x0f, 0x0c, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0x20, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 16 + 32 * VG
 ; CHECK-NEXT:    .cfi_offset w29, -16
 ; CHECK-NEXT:    mov x8, #-1
-; CHECK-NEXT:    mov w10, #128
-; CHECK-NEXT:    mov x9, sp
+; CHECK-NEXT:    mov w9, #128
 ; CHECK-NEXT:    ptrue p0.h
+; CHECK-NEXT:    st1h { z3.h }, p0, [sp, #3, mul vl]
+; CHECK-NEXT:    st1h { z2.h }, p0, [sp, #2, mul vl]
 ; CHECK-NEXT:    addvl x8, x8, #2
+; CHECK-NEXT:    st1h { z1.h }, p0, [sp, #1, mul vl]
 ; CHECK-NEXT:    cmp x8, #128
-; CHECK-NEXT:    st1h { z3.h }, p0, [x9, #3, mul vl]
-; CHECK-NEXT:    csel x8, x8, x10, lo
-; CHECK-NEXT:    st1h { z2.h }, p0, [x9, #2, mul vl]
-; CHECK-NEXT:    st1h { z1.h }, p0, [x9, #1, mul vl]
 ; CHECK-NEXT:    st1h { z0.h }, p0, [sp]
+; CHECK-NEXT:    csel x8, x8, x9, lo
+; CHECK-NEXT:    mov x9, sp
 ; CHECK-NEXT:    strh w0, [x9, x8, lsl #1]
-; CHECK-NEXT:    ld1h { z1.h }, p0/z, [x9, #1, mul vl]
-; CHECK-NEXT:    ld1h { z2.h }, p0/z, [x9, #2, mul vl]
-; CHECK-NEXT:    ld1h { z3.h }, p0/z, [x9, #3, mul vl]
 ; CHECK-NEXT:    ld1h { z0.h }, p0/z, [sp]
+; CHECK-NEXT:    ld1h { z1.h }, p0/z, [sp, #1, mul vl]
+; CHECK-NEXT:    ld1h { z2.h }, p0/z, [sp, #2, mul vl]
+; CHECK-NEXT:    ld1h { z3.h }, p0/z, [sp, #3, mul vl]
 ; CHECK-NEXT:    addvl sp, sp, #4
 ; CHECK-NEXT:    ldr x29, [sp], #16 // 8-byte Folded Reload
 ; CHECK-NEXT:    ret
   %ins = insertelement <vscale x 32 x i16> %a, i16 %elt, i64 128
   ret <vscale x 32 x i16> %ins
 }
 
 define <vscale x 8 x i32> @split_insert_8i32(<vscale x 8 x i32> %a, i32 %elt) {
 ; CHECK-LABEL: split_insert_8i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    str x29, [sp, #-16]! // 8-byte Folded Spill
 ; CHECK-NEXT:    addvl sp, sp, #-2
 ; CHECK-NEXT:    .cfi_escape 0x0f, 0x0c, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 16 + 16 * VG
 ; CHECK-NEXT:    .cfi_offset w29, -16
 ; CHECK-NEXT:    cnth x8
 ; CHECK-NEXT:    mov w9, #16960
 ; CHECK-NEXT:    movk w9, #15, lsl #16
 ; CHECK-NEXT:    sub x8, x8, #1
 ; CHECK-NEXT:    cmp x8, x9
-; CHECK-NEXT:    mov x10, sp
-; CHECK-NEXT:    csel x8, x8, x9, lo
 ; CHECK-NEXT:    ptrue p0.s
-; CHECK-NEXT:    st1w { z1.s }, p0, [x10, #1, mul vl]
+; CHECK-NEXT:    csel x8, x8, x9, lo
+; CHECK-NEXT:    mov x9, sp
+; CHECK-NEXT:    st1w { z1.s }, p0, [sp, #1, mul vl]
 ; CHECK-NEXT:    st1w { z0.s }, p0, [sp]
-; CHECK-NEXT:    str w0, [x10, x8, lsl #2]
-; CHECK-NEXT:    ld1w { z1.s }, p0/z, [x10, #1, mul vl]
+; CHECK-NEXT:    str w0, [x9, x8, lsl #2]
 ; CHECK-NEXT:    ld1w { z0.s }, p0/z, [sp]
+; CHECK-NEXT:    ld1w { z1.s }, p0/z, [sp, #1, mul vl]
 ; CHECK-NEXT:    addvl sp, sp, #2
 ; CHECK-NEXT:    ldr x29, [sp], #16 // 8-byte Folded Reload
 ; CHECK-NEXT:    ret
   %ins = insertelement <vscale x 8 x i32> %a, i32 %elt, i64 1000000
   ret <vscale x 8 x i32> %ins
 }