[clang][ARM] PACBTI-M assembly support

[stuij]

Summary

Introduce assembly support for Armv8.1-M PACBTI extension. This is an optional
extension in v8.1-M.

There are 10 new system registers and 5 new instructions, all predicated on the
feature.

The attribute for llvm-mc is called "pacbti". For armclang, an architecture
extension also called "pacbti" was created.

This patch is part of a series that adds support for the PACBTI-M extension of
the Armv8.1-M architecture, as detailed here:

https://community.arm.com/arm-community-blogs/b/architectures-and-processors-blog/posts/armv8-1-m-pointer-authentication-and-branch-target-identification-extension

The PACBTI-M specification can be found in the Armv8-M Architecture Reference
Manual:

https://developer.arm.com/documentation/ddi0553/latest

The following people contributed to this patch:

• Victor Campos
• Ties Stuij

[ostannard]

llvm/lib/Target/ARM/ARMInstrThumb2.td

4083

Why are these needed in addition to the PACBTIHintSpaceInst instructions below?

5678

I think all of the AUT instructions need hasSideEffects set, since they can raise exceptions.

5679

This needs isBranch set, and a test added to test/MC/ARM/implicit-it-generation.s.

llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp

6441

PACG, AUTG and BXAUT can be conditional, so shouldn't be in this list.

6589

Again, some of these are predicable.

12282

Unintentional formatting change.

llvm/test/MC/ARM/armv8.1m-pacbti-error.s

4

We should also test the cases where PACG/AUTG/BXAUT cannot use PC/SP.

[vhscampos]

llvm/lib/Target/ARM/ARMInstrThumb2.td

4083

Since these instructions are in the HINT space, without specifying inst aliases, they were printed in the HINT form when using llvm-mc instead of in their PACBTI form. Therefore I added these t2InstAlias instances.

[stuij]

addressed review comments:

• Added predicate operand to bxaut, autg. They will now also behave correctly in IT blocks.
• Adjusted operator constraints for a number of instructions so these confirm to the specs.
• Expanded tests to test above changes and permutation of allowed operators for instructions.
• Addressed minor review comments.

[stuij]

A slight amendment to the description of the just uploaded patch amendment: PACG has also been made conditional.

llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp

6441

Thanks. Besides removing these from this list and the one below, I've added a predicate operator to actually make them conditional. The description of the patch amend didn't mention PACG, but it too has been made conditional.

llvm/test/MC/ARM/armv8.1m-pacbti-error.s

4

Thanks. Adding extra testcases uncovered a number of cases where the changes didn't match the spec. This should now be resolved.

[labrinea]

Looks like you've addressed Oliver's comments. I don't have any new suggestions from my end. Just make sure you've removed the test xfail before merging.

clang/test/Driver/darwin-ld-lto.c

2

Seems accidental.

[stuij]

addressed review comment and clang-format suggestions

clang/test/Driver/armv8.1m.main.c

 // RUN: %clang -target arm-arm-none-eabi -march=armv8.1-m.main+dsp  -### %s 2> %t
 // RUN: FileCheck --check-prefix=CHECK-DSP < %t %s
 // CHECK-DSP: "-target-feature" "+dsp"
 
+// RUN: %clang -target arm-arm-none-eabi -march=armv8.1-m.main+pacbti -### %s 2> %t
+// RUN: FileCheck --check-prefix=CHECK-PACBTI < %t %s
+// CHECK-PACBTI: "-target-feature" "+pacbti"
+
 // RUN: %clang -target arm-arm-none-eabi -march=armv8.1-m.main+fp  -### %s 2> %t
 // RUN: FileCheck --check-prefix=CHECK-FP < %t %s
 // CHECK-FP-DAG: "-target-feature" "+fp-armv8d16sp"
 // CHECK-FP-NOT: "-target-feature" "+fp-armv8d16"
 // CHECK-FP-NOT: "-target-feature" "+fp-armv8sp"
 // CHECK-FP-NOT: "-target-feature" "+fp-armv8"
 // CHECK-FP-NOT: "-target-feature" "+fp64"
 // CHECK-FP-NOT: "-target-feature" "+d32"

clang/test/Driver/darwin-ld-lto.c

 // REQUIRES: system-darwin
-
+// XFAIL: *
 // Check that ld gets "-lto_library".
 
 // RUN: mkdir -p %t/bin
 // RUN: mkdir -p %t/lib
 // RUN: touch %t/lib/libLTO.dylib
 // RUN: %clang -fuse-ld= -target x86_64-apple-darwin10 -### %s \
 // RUN:   -ccc-install-dir %t/bin -mlinker-version=133 2> %t.log
 // RUN: FileCheck -check-prefix=LINK_LTOLIB_PATH %s -input-file %t.log

llvm/include/llvm/Support/ARMTargetParser.h

 //===-- ARMTargetParser - Parser for ARM target features --------*- C++ -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //

 
 class Triple;
 
 namespace ARM {
 
 // Arch extension modifiers for CPUs.
 // Note that this is not the same as the AArch64 list
 enum ArchExtKind : uint64_t {
   AEK_INVALID =     0,
   AEK_NONE =        1,
   AEK_CRC =         1 << 1,
   AEK_CRYPTO =      1 << 2,
   AEK_FP =          1 << 3,
   AEK_HWDIVTHUMB =  1 << 4,
   AEK_HWDIVARM =    1 << 5,
   AEK_MP =          1 << 6,
   AEK_SIMD =        1 << 7,
enum ArchExtKind : uint64_t {
   AEK_CDECP0 =      1 << 22,
   AEK_CDECP1 =      1 << 23,
   AEK_CDECP2 =      1 << 24,
   AEK_CDECP3 =      1 << 25,
   AEK_CDECP4 =      1 << 26,
   AEK_CDECP5 =      1 << 27,
   AEK_CDECP6 =      1 << 28,
   AEK_CDECP7 =      1 << 29,
-
+  AEK_PACBTI =      1 << 30,
   // Unsupported extensions.
   AEK_OS       =    1ULL << 59,
   AEK_IWMMXT   =    1ULL << 60,
   AEK_IWMMXT2  =    1ULL << 61,
   AEK_MAVERICK =    1ULL << 62,
   AEK_XSCALE   =    1ULL << 63,
 };
 
 // List of Arch Extension names.
 // FIXME: TableGen this.

llvm/include/llvm/Support/ARMTargetParser.def

 ARM_ARCH_EXT_NAME("cdecp0",   ARM::AEK_CDECP0,   "+cdecp0",  "-cdecp0")
 ARM_ARCH_EXT_NAME("cdecp1",   ARM::AEK_CDECP1,   "+cdecp1",  "-cdecp1")
 ARM_ARCH_EXT_NAME("cdecp2",   ARM::AEK_CDECP2,   "+cdecp2",  "-cdecp2")
 ARM_ARCH_EXT_NAME("cdecp3",   ARM::AEK_CDECP3,   "+cdecp3",  "-cdecp3")
 ARM_ARCH_EXT_NAME("cdecp4",   ARM::AEK_CDECP4,   "+cdecp4",  "-cdecp4")
 ARM_ARCH_EXT_NAME("cdecp5",   ARM::AEK_CDECP5,   "+cdecp5",  "-cdecp5")
 ARM_ARCH_EXT_NAME("cdecp6",   ARM::AEK_CDECP6,   "+cdecp6",  "-cdecp6")
 ARM_ARCH_EXT_NAME("cdecp7",   ARM::AEK_CDECP7,   "+cdecp7",  "-cdecp7")
+ARM_ARCH_EXT_NAME("pacbti",   ARM::AEK_PACBTI,   "+pacbti",  "-pacbti")
 #undef ARM_ARCH_EXT_NAME
 
 #ifndef ARM_HW_DIV_NAME
 #define ARM_HW_DIV_NAME(NAME, ID)
 #endif
 ARM_HW_DIV_NAME("invalid", ARM::AEK_INVALID)
 ARM_HW_DIV_NAME("none", ARM::AEK_NONE)
 ARM_HW_DIV_NAME("thumb", ARM::AEK_HWDIVTHUMB)

llvm/lib/Target/ARM/ARM.td

def FeatureLOB            : SubtargetFeature<"lob", "HasLOB", "true",
                                              "Enable Low Overhead Branch "
                                              "extensions">;
 
 def FeatureFixCMSE_CVE_2021_35465 : SubtargetFeature<"fix-cmse-cve-2021-35465",
                                         "FixCMSE_CVE_2021_35465", "true",
                                         "Mitigate against the cve-2021-35465 "
                                         "security vulnurability">;
 
+def FeaturePACBTI         : SubtargetFeature<"pacbti", "HasPACBTI", "true",
+                                             "Enable Pointer Authentication and Branch "
+                                             "Target Identification">;
+
 //===----------------------------------------------------------------------===//
 // ARM architecture class
 //
 
 // A-series ISA
 def FeatureAClass : SubtargetFeature<"aclass", "ARMProcClass", "AClass",
                                      "Is application profile ('A' series)">;
 

llvm/lib/Target/ARM/ARMInstrThumb2.td

 
 // A6.3.4 Branches and miscellaneous control
 // Table A6-14 Change Processor State, and hint instructions
 def t2HINT : T2I<(outs), (ins imm0_239:$imm), NoItinerary, "hint", ".w\t$imm",
                   [(int_arm_hint imm0_239:$imm)]> {
   bits<8> imm;
   let Inst{31-3} = 0b11110011101011111000000000000;
   let Inst{7-0} = imm;
+
+  let DecoderMethod = "DecodeT2HintSpaceInstruction";
 }
 
 def : t2InstAlias<"hint$p $imm", (t2HINT imm0_239:$imm, pred:$p), 0>;
 def : t2InstAlias<"nop$p.w", (t2HINT 0, pred:$p), 1>;
 def : t2InstAlias<"yield$p.w", (t2HINT 1, pred:$p), 1>;
 def : t2InstAlias<"wfe$p.w", (t2HINT 2, pred:$p), 1>;
 def : t2InstAlias<"wfi$p.w", (t2HINT 3, pred:$p), 1>;
 def : t2InstAlias<"sev$p.w", (t2HINT 4, pred:$p), 1>;
 def : t2InstAlias<"sevl$p.w", (t2HINT 5, pred:$p), 1> {
   let Predicates = [IsThumb2, HasV8];
 }
 def : t2InstAlias<"esb$p.w", (t2HINT 16, pred:$p), 1> {
   let Predicates = [IsThumb2, HasRAS];
 }
 def : t2InstAlias<"esb$p", (t2HINT 16, pred:$p), 0> {
   let Predicates = [IsThumb2, HasRAS];
 }
 def : t2InstAlias<"csdb$p.w", (t2HINT 20, pred:$p), 0>;
 def : t2InstAlias<"csdb$p",   (t2HINT 20, pred:$p), 1>;
 
+def : t2InstAlias<"pacbti$p r12,lr,sp", (t2HINT 13, pred:$p), 1>;
+def : t2InstAlias<"bti$p", (t2HINT 15, pred:$p), 1>;
+def : t2InstAlias<"pac$p r12,lr,sp", (t2HINT 29, pred:$p), 1>;
+def : t2InstAlias<"aut$p r12,lr,sp", (t2HINT 45, pred:$p), 1>;
+
 def t2DBG : T2I<(outs), (ins imm0_15:$opt), NoItinerary, "dbg", "\t$opt",
                 [(int_arm_dbg imm0_15:$opt)]> {
   bits<4> opt;
   let Inst{31-20} = 0b111100111010;
   let Inst{19-16} = 0b1111;
   let Inst{15-8} = 0b10000000;
   let Inst{7-4} = 0b1111;
   let Inst{3-0} = opt;
def : InstAlias<"cinc\t$Rd, $Rn, $fcond",
                  (t2CSINC rGPR:$Rd, GPRwithZRnosp:$Rn, GPRwithZRnosp:$Rn, pred_noal_inv:$fcond)>;
 
   def : InstAlias<"cinv\t$Rd, $Rn, $fcond",
                  (t2CSINV rGPR:$Rd, GPRwithZRnosp:$Rn, GPRwithZRnosp:$Rn, pred_noal_inv:$fcond)>;
 
   def : InstAlias<"cneg\t$Rd, $Rn, $fcond",
                  (t2CSNEG rGPR:$Rd, GPRwithZRnosp:$Rn, GPRwithZRnosp:$Rn, pred_noal_inv:$fcond)>;
 }
+
+
+// PACBTI
+let Predicates = [IsThumb2, HasV8_1MMainline, HasPACBTI] in {
+def t2PACG : V8_1MI<(outs rGPR:$Rd),
+                    (ins pred:$p, GPRnopc:$Rn, GPRnopc:$Rm),
+                    AddrModeNone, NoItinerary, "pacg${p}", "$Rd, $Rn, $Rm", "", []> {
+  bits<4> Rd;
+  bits<4> Rn;
+  bits<4> Rm;
+  let Inst{31-20} = 0b111110110110;
+  let Inst{19-16} = Rn;
+  let Inst{15-12} = 0b1111;
+  let Inst{11-8}  = Rd;
+  let Inst{7-4}   = 0b0000;
+  let Inst{3-0}   = Rm;
+}
+
+let hasSideEffects = 1 in {
+class PACBTIAut<dag iops, string asm, bit b>
+  : V8_1MI<(outs), iops,
+           AddrModeNone, NoItinerary, asm, "$Ra, $Rn, $Rm", "", []> {
+  bits<4> Ra;
+  bits<4> Rn;
+  bits<4> Rm;
+  let Inst{31-20} = 0b111110110101;
+  let Inst{19-16} = Rn;
+  let Inst{15-12} = Ra;
+  let Inst{11-5}  = 0b1111000;
+  let Inst{4}     = b;
+  let Inst{3-0}   = Rm;
+}
+}
+
+def t2AUTG  : PACBTIAut<(ins pred:$p, GPRnosp:$Ra, GPRnopc:$Rn, GPRnopc:$Rm),
+                        "autg${p}", 0>;
+
+let isBranch = 1, isTerminator = 1, isIndirectBranch = 1 in {
+  def t2BXAUT : PACBTIAut<(ins pred:$p, GPRnosp:$Ra, rGPR:$Rn, GPRnopc:$Rm),
+                          "bxaut${p}", 1>;
+}
+}
+
+
+class PACBTIHintSpaceInst<string asm, string ops, bits<8> imm>
+  : V8_1MI<(outs), (ins), AddrModeNone, NoItinerary, asm, ops, "", []> {
+  let Inst{31-8} = 0b111100111010111110000000;
+  let Inst{7-0}  = imm;
+
+  let Unpredictable{19-16} = 0b1111;
+  let Unpredictable{13-11} = 0b101;
+
+  let DecoderMethod = "DecodeT2HintSpaceInstruction";
+}
+
+class PACBTIHintSpaceNoOpsInst<string asm, bits<8> imm>
+  : PACBTIHintSpaceInst<asm, "", imm>;
+
+class PACBTIHintSpaceDefInst<string asm, bits<8> imm>
+  : PACBTIHintSpaceInst<asm, "r12, lr, sp", imm> {
+  let Defs = [R12];
+  let Uses = [LR, SP];
+}
+
+class PACBTIHintSpaceUseInst<string asm, bits<8> imm>
+  : PACBTIHintSpaceInst<asm, "r12, lr, sp", imm> {
+  let Uses = [R12, LR, SP];
+}
+
+def t2PAC    : PACBTIHintSpaceDefInst<"pac", 0b00011101>;
+def t2PACBTI : PACBTIHintSpaceDefInst<"pacbti", 0b00001101>;
+def t2BTI    : PACBTIHintSpaceNoOpsInst<"bti", 0b00001111>;
+def t2AUT    : PACBTIHintSpaceUseInst<"aut", 0b00101101> {
+  let hasSideEffects = 1;
+}

llvm/lib/Target/ARM/ARMPredicates.td

 def HasDotProd       : Predicate<"Subtarget->hasDotProd()">,
                                  AssemblerPredicate<(all_of FeatureDotProd), "dotprod">;
 def HasCRC           : Predicate<"Subtarget->hasCRC()">,
                                  AssemblerPredicate<(all_of FeatureCRC), "crc">;
 def HasRAS           : Predicate<"Subtarget->hasRAS()">,
                                  AssemblerPredicate<(all_of FeatureRAS), "ras">;
 def HasLOB           : Predicate<"Subtarget->hasLOB()">,
                                  AssemblerPredicate<(all_of FeatureLOB), "lob">;
+def HasPACBTI        : Predicate<"Subtarget->hasPACBTI()">,
+                                 AssemblerPredicate<(all_of FeaturePACBTI), "pacbti">;
 def HasFP16          : Predicate<"Subtarget->hasFP16()">,
                                  AssemblerPredicate<(all_of FeatureFP16),"half-float conversions">;
 def HasFullFP16      : Predicate<"Subtarget->hasFullFP16()">,
                                  AssemblerPredicate<(all_of FeatureFullFP16),"full half-float">;
 def HasFP16FML       : Predicate<"Subtarget->hasFP16FML()">,
                                  AssemblerPredicate<(all_of FeatureFP16FML),"full half-float fml">;
 def HasBF16          : Predicate<"Subtarget->hasBF16()">,
                                  AssemblerPredicate<(all_of FeatureBF16),"BFloat16 floating point extension">;

llvm/lib/Target/ARM/ARMRegisterInfo.td

 def GPRwithAPSR : RegisterClass<"ARM", [i32], 32, (add (sub GPR, PC), APSR_NZCV)> {
   let AltOrders = [(add LR, GPRnopc), (trunc GPRnopc, 8)];
   let AltOrderSelect = [{
       return 1 + MF.getSubtarget<ARMSubtarget>().isThumb1Only();
   }];
   let DiagnosticString = "operand must be a register in range [r0, r14] or apsr_nzcv";
 }
 
+// GPRs without the SP register. Used for BXAUT and AUTG
+def GPRnosp : RegisterClass<"ARM", [i32], 32, (add (sequence "R%u", 0, 12), LR, PC)> {
+  let AltOrders = [(add LR, GPRnosp), (trunc GPRnosp, 8),
+                   (add (trunc GPRnosp, 8), R12, LR, (shl GPRnosp, 8))];
+  let AltOrderSelect = [{
+      return MF.getSubtarget<ARMSubtarget>().getGPRAllocationOrder(MF);
+  }];
+  let DiagnosticString = "operand must be a register in range [r0, r12] or LR or PC";
+}
+
 // GPRs without the PC and SP registers but with APSR. Used by CLRM instruction.
 def GPRwithAPSRnosp : RegisterClass<"ARM", [i32], 32, (add (sequence "R%u", 0, 12), LR, APSR)> {
   let isAllocatable = 0;
 }
 
 def GPRwithZR : RegisterClass<"ARM", [i32], 32, (add (sub GPR, PC), ZR)> {
   let AltOrders = [(add LR, GPRwithZR), (trunc GPRwithZR, 8)];
   let AltOrderSelect = [{

llvm/lib/Target/ARM/ARMSubtarget.h

 //===-- ARMSubtarget.h - Define Subtarget for the ARM ----------*- C++ -*--===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
protected:
   bool HasCRC = false;
 
   /// HasRAS - if true, the processor supports RAS extensions
   bool HasRAS = false;
 
   /// HasLOB - if true, the processor supports the Low Overhead Branch extension
   bool HasLOB = false;
 
+  bool HasPACBTI = false;
+
   /// If true, the instructions "vmov.i32 d0, #0" and "vmov.i32 q0, #0" are
   /// particularly effective at zeroing a VFP register.
   bool HasZeroCycleZeroing = false;
 
   /// HasFPAO - if true, processor  does positive address offset computation faster
   bool HasFPAO = false;
 
   /// HasFuseAES - if true, processor executes back to back AES instruction
public:
   bool hasNEON() const { return HasNEON;  }
   bool hasSHA2() const { return HasSHA2; }
   bool hasAES() const { return HasAES; }
   bool hasCrypto() const { return HasCrypto; }
   bool hasDotProd() const { return HasDotProd; }
   bool hasCRC() const { return HasCRC; }
   bool hasRAS() const { return HasRAS; }
   bool hasLOB() const { return HasLOB; }
+  bool hasPACBTI() const { return HasPACBTI; }
   bool hasVirtualization() const { return HasVirtualization; }
 
   bool useNEONForSinglePrecisionFP() const {
     return hasNEON() && UseNEONForSinglePrecisionFP;
   }
 
   bool hasDivideInThumbMode() const { return HasHardwareDivideInThumb; }
   bool hasDivideInARMMode() const { return HasHardwareDivideInARM; }

llvm/lib/Target/ARM/ARMSystemRegister.td

 def : MClassSysReg<0,    0,    1,    0x893, "faultmask_ns">;
 }
 
 let Requires = [{ {ARM::Feature8MSecExt} }] in {
 def : MClassSysReg<0,    0,    1,    0x894, "control_ns">;
 def : MClassSysReg<0,    0,    1,    0x898, "sp_ns">;
 }
 
+let Requires = [{ {ARM::FeaturePACBTI} }] in {
+def : MClassSysReg<0,    0,    1,    0x820, "pac_key_p_0">;
+def : MClassSysReg<0,    0,    1,    0x821, "pac_key_p_1">;
+def : MClassSysReg<0,    0,    1,    0x822, "pac_key_p_2">;
+def : MClassSysReg<0,    0,    1,    0x823, "pac_key_p_3">;
+def : MClassSysReg<0,    0,    1,    0x824, "pac_key_u_0">;
+def : MClassSysReg<0,    0,    1,    0x825, "pac_key_u_1">;
+def : MClassSysReg<0,    0,    1,    0x826, "pac_key_u_2">;
+def : MClassSysReg<0,    0,    1,    0x827, "pac_key_u_3">;
+def : MClassSysReg<0,    0,    1,    0x8a0, "pac_key_p_0_ns">;
+def : MClassSysReg<0,    0,    1,    0x8a1, "pac_key_p_1_ns">;
+def : MClassSysReg<0,    0,    1,    0x8a2, "pac_key_p_2_ns">;
+def : MClassSysReg<0,    0,    1,    0x8a3, "pac_key_p_3_ns">;
+def : MClassSysReg<0,    0,    1,    0x8a4, "pac_key_u_0_ns">;
+def : MClassSysReg<0,    0,    1,    0x8a5, "pac_key_u_1_ns">;
+def : MClassSysReg<0,    0,    1,    0x8a6, "pac_key_u_2_ns">;
+def : MClassSysReg<0,    0,    1,    0x8a7, "pac_key_u_3_ns">;
+}
 
 // Banked Registers
 //
 class BankedReg<string name,  bits<8> enc>
                : SearchableTable {
   string Name;
   bits<8> Encoding;
   let Name = name;

llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp

 //===- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions -------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
StringRef ARMAsmParser::splitMnemonic(StringRef Mnemonic,
   PredicationCode = ARMCC::AL;
   VPTPredicationCode = ARMVCC::None;
   CarrySetting = false;
   ProcessorIMod = 0;
 
   // Ignore some mnemonics we know aren't predicated forms.
   //
   // FIXME: Would be nice to autogen this.
   if ((Mnemonic == "movs" && isThumb()) ||
       Mnemonic == "teq"   || Mnemonic == "vceq"   || Mnemonic == "svc"   ||
       Mnemonic == "mls"   || Mnemonic == "smmls"  || Mnemonic == "vcls"  ||
       Mnemonic == "vmls"  || Mnemonic == "vnmls"  || Mnemonic == "vacge" ||
       Mnemonic == "vcge"  || Mnemonic == "vclt"   || Mnemonic == "vacgt" ||
       Mnemonic == "vaclt" || Mnemonic == "vacle"  || Mnemonic == "hlt" ||
       Mnemonic == "vcgt"  || Mnemonic == "vcle"   || Mnemonic == "smlal" ||
       Mnemonic == "umaal" || Mnemonic == "umlal"  || Mnemonic == "vabal" ||
       Mnemonic == "vmlal" || Mnemonic == "vpadal" || Mnemonic == "vqdmlal" ||
       Mnemonic == "fmuls" || Mnemonic == "vmaxnm" || Mnemonic == "vminnm" ||
       Mnemonic == "vcvta" || Mnemonic == "vcvtn"  || Mnemonic == "vcvtp" ||
       Mnemonic == "vcvtm" || Mnemonic == "vrinta" || Mnemonic == "vrintn" ||
       Mnemonic == "vrintp" || Mnemonic == "vrintm" || Mnemonic == "hvc" ||
       Mnemonic.startswith("vsel") || Mnemonic == "vins" || Mnemonic == "vmovx" ||
       Mnemonic == "bxns"  || Mnemonic == "blxns" ||
-      Mnemonic == "vdot"  || Mnemonic == "vmmla"  ||
+      Mnemonic == "vdot"  || Mnemonic == "vmmla" ||
       Mnemonic == "vudot" || Mnemonic == "vsdot" ||
       Mnemonic == "vcmla" || Mnemonic == "vcadd" ||
       Mnemonic == "vfmal" || Mnemonic == "vfmsl" ||
-      Mnemonic == "wls" || Mnemonic == "le" || Mnemonic == "dls" ||
-      Mnemonic == "csel" || Mnemonic == "csinc" ||
+      Mnemonic == "wls"   || Mnemonic == "le"    || Mnemonic == "dls" ||
+      Mnemonic == "csel"  || Mnemonic == "csinc" ||
       Mnemonic == "csinv" || Mnemonic == "csneg" || Mnemonic == "cinc" ||
-      Mnemonic == "cinv" || Mnemonic == "cneg" || Mnemonic == "cset" ||
-      Mnemonic == "csetm")
+      Mnemonic == "cinv"  || Mnemonic == "cneg"  || Mnemonic == "cset" ||
+      Mnemonic == "csetm" ||
+      Mnemonic == "aut"   || Mnemonic == "pac" || Mnemonic == "pacbti" ||
+      Mnemonic == "bti")
     return Mnemonic;
 
   // First, split out any predication code. Ignore mnemonics we know aren't
   // predicated but do have a carry-set and so weren't caught above.
   if (Mnemonic != "adcs" && Mnemonic != "bics" && Mnemonic != "movs" &&
       Mnemonic != "muls" && Mnemonic != "smlals" && Mnemonic != "smulls" &&
       Mnemonic != "umlals" && Mnemonic != "umulls" && Mnemonic != "lsls" &&
       Mnemonic != "sbcs" && Mnemonic != "rscs" &&
if (Mnemonic == "bkpt" || Mnemonic == "cbnz" || Mnemonic == "setend" ||
       Mnemonic.startswith("crc32") || Mnemonic.startswith("cps") ||
       Mnemonic.startswith("vsel") || Mnemonic == "vmaxnm" ||
       Mnemonic == "vminnm" || Mnemonic == "vcvta" || Mnemonic == "vcvtn" ||
       Mnemonic == "vcvtp" || Mnemonic == "vcvtm" || Mnemonic == "vrinta" ||
       Mnemonic == "vrintn" || Mnemonic == "vrintp" || Mnemonic == "vrintm" ||
       Mnemonic.startswith("aes") || Mnemonic == "hvc" || Mnemonic == "setpan" ||
       Mnemonic.startswith("sha1") || Mnemonic.startswith("sha256") ||
       (FullInst.startswith("vmull") && FullInst.endswith(".p64")) ||
       Mnemonic == "vmovx" || Mnemonic == "vins" ||
       Mnemonic == "vudot" || Mnemonic == "vsdot" ||
       Mnemonic == "vcmla" || Mnemonic == "vcadd" ||
       Mnemonic == "vfmal" || Mnemonic == "vfmsl" ||
       Mnemonic == "vfmat" || Mnemonic == "vfmab" ||
       Mnemonic == "vdot"  || Mnemonic == "vmmla" ||
       Mnemonic == "sb"    || Mnemonic == "ssbb"  ||
       Mnemonic == "pssbb" || Mnemonic == "vsmmla" ||
       Mnemonic == "vummla" || Mnemonic == "vusmmla" ||
       Mnemonic == "vusdot" || Mnemonic == "vsudot" ||
       Mnemonic == "bfcsel" || Mnemonic == "wls" ||
       Mnemonic == "dls" || Mnemonic == "le" || Mnemonic == "csel" ||
       Mnemonic == "csinc" || Mnemonic == "csinv" || Mnemonic == "csneg" ||
       Mnemonic == "cinc" || Mnemonic == "cinv" || Mnemonic == "cneg" ||
       Mnemonic == "cset" || Mnemonic == "csetm" ||
-      Mnemonic.startswith("vpt") || Mnemonic.startswith("vpst") ||
       (hasCDE() && MS.isCDEInstr(Mnemonic) &&
        !MS.isITPredicableCDEInstr(Mnemonic)) ||
+      Mnemonic.startswith("vpt") || Mnemonic.startswith("vpst") ||
+      Mnemonic == "pac" || Mnemonic == "pacbti" ||
+      Mnemonic == "aut" ||
+      Mnemonic == "bti" ||
       (hasMVE() &&
        (Mnemonic.startswith("vst2") || Mnemonic.startswith("vld2") ||
         Mnemonic.startswith("vst4") || Mnemonic.startswith("vld4") ||
         Mnemonic.startswith("wlstp") || Mnemonic.startswith("dlstp") ||
         Mnemonic.startswith("letp")))) {
     // These mnemonics are never predicable
     CanAcceptPredicationCode = false;
   } else if (!isThumb()) {
const FeatureBitset Features;
       {ARM::AEK_SEC, {Feature_HasV6KBit}, {ARM::FeatureTrustZone}},
       // FIXME: Only available in A-class, isel not predicated
       {ARM::AEK_VIRT, {Feature_HasV7Bit}, {ARM::FeatureVirtualization}},
       {ARM::AEK_FP16,
        {Feature_HasV8_2aBit},
        {ARM::FeatureFPARMv8, ARM::FeatureFullFP16}},
       {ARM::AEK_RAS, {Feature_HasV8Bit}, {ARM::FeatureRAS}},
       {ARM::AEK_LOB, {Feature_HasV8_1MMainlineBit}, {ARM::FeatureLOB}},
+      { ARM::AEK_PACBTI, {Feature_HasV8_1MMainlineBit}, {ARM::FeaturePACBTI} },
       // FIXME: Unsupported extensions.
       {ARM::AEK_OS, {}, {}},
       {ARM::AEK_IWMMXT, {}, {}},
       {ARM::AEK_IWMMXT2, {}, {}},
       {ARM::AEK_MAVERICK, {}, {}},
       {ARM::AEK_XSCALE, {}, {}},
   };
   bool EnableFeature = true;
   if (Name.startswith_insensitive("no")) {
     EnableFeature = false;

llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp

 //===- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA ---------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 

 static DecodeStatus DecodetGPREvenRegisterClass(MCInst &Inst, unsigned RegNo,
                                    uint64_t Address, const void *Decoder);
 static DecodeStatus
 DecodeGPRwithAPSR_NZCVnospRegisterClass(MCInst &Inst, unsigned RegNo,
                                         uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst,
                                                unsigned RegNo, uint64_t Address,
                                                const void *Decoder);
+static DecodeStatus DecodeGPRnospRegisterClass(MCInst &Inst,
+                                               unsigned RegNo, uint64_t Address,
+                                               const void *Decoder);
 static DecodeStatus DecodeGPRwithAPSRRegisterClass(MCInst &Inst,
                                                unsigned RegNo, uint64_t Address,
                                                const void *Decoder);
 static DecodeStatus DecodeGPRwithZRRegisterClass(MCInst &Inst,
                                                unsigned RegNo, uint64_t Address,
                                                const void *Decoder);
 static DecodeStatus DecodeGPRwithZRnospRegisterClass(
     MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder);

 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn,
                                uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeTSTInstruction(MCInst &Inst, unsigned Insn,
                                uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeSETPANInstruction(MCInst &Inst, unsigned Insn,
                                uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn,
                                uint64_t Address, const void *Decoder);
+static DecodeStatus DecodeT2HintSpaceInstruction(MCInst &Inst, unsigned Insn,
+                                                 uint64_t Address,
+                                                 const void *Decoder);
 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val,
                                uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val,
                                uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeAddrMode5FP16Operand(MCInst &Inst, unsigned Val,
                                uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val,
                                uint64_t Address, const void *Decoder);
DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo,
   if (RegNo == 15)
     S = MCDisassembler::SoftFail;
 
   Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
 
   return S;
 }
 
 static DecodeStatus
+DecodeGPRnospRegisterClass(MCInst &Inst, unsigned RegNo,
+                           uint64_t Address, const void *Decoder) {
+  DecodeStatus S = MCDisassembler::Success;
+
+  if (RegNo == 13)
+    S = MCDisassembler::SoftFail;
+
+  Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
+
+  return S;
+}
+
+static DecodeStatus
 DecodeGPRwithAPSRRegisterClass(MCInst &Inst, unsigned RegNo,
                                uint64_t Address, const void *Decoder) {
   DecodeStatus S = MCDisassembler::Success;
 
   if (RegNo == 15)
   {
     Inst.addOperand(MCOperand::createReg(ARM::APSR_NZCV));
     return MCDisassembler::Success;
if (imod && M) {
     if(imm > 4) return MCDisassembler::Fail;
     Inst.setOpcode(ARM::t2HINT);
     Inst.addOperand(MCOperand::createImm(imm));
   }
 
   return S;
 }
 
+static DecodeStatus DecodeT2HintSpaceInstruction(MCInst &Inst, unsigned Insn,
+                                                 uint64_t Address,
+                                                 const void *Decoder) {
+  unsigned imm = fieldFromInstruction(Insn, 0, 8);
+
+  unsigned Opcode = ARM::t2HINT;
+
+  if (imm == 0x0D) {
+    Opcode = ARM::t2PACBTI;
+  } else if (imm == 0x1D) {
+    Opcode = ARM::t2PAC;
+  } else if (imm == 0x2D) {
+    Opcode = ARM::t2AUT;
+  } else if (imm == 0x0F) {
+    Opcode = ARM::t2BTI;
+  }
+
+  Inst.setOpcode(Opcode);
+  if (Opcode == ARM::t2HINT) {
+    Inst.addOperand(MCOperand::createImm(imm));
+  }
+
+  return MCDisassembler::Success;
+}
+
 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn,
                                  uint64_t Address, const void *Decoder) {
   DecodeStatus S = MCDisassembler::Success;
 
   unsigned Rd = fieldFromInstruction(Insn, 8, 4);
   unsigned imm = 0;
 
   imm |= (fieldFromInstruction(Insn, 0, 8) << 0);
if (FeatureBits[ARM::FeatureMClass]) {
     case 0x88: // msp_ns
     case 0x89: // psp_ns
     case 0x90: // primask_ns
     case 0x94: // control_ns
     case 0x98: // sp_ns
       if (!(FeatureBits[ARM::Feature8MSecExt]))
         return MCDisassembler::Fail;
       break;
+    case 0x20: // pac_key_p_0
+    case 0x21: // pac_key_p_1
+    case 0x22: // pac_key_p_2
+    case 0x23: // pac_key_p_3
+    case 0x24: // pac_key_u_0
+    case 0x25: // pac_key_u_1
+    case 0x26: // pac_key_u_2
+    case 0x27: // pac_key_u_3
+    case 0xa0: // pac_key_p_0_ns
+    case 0xa1: // pac_key_p_1_ns
+    case 0xa2: // pac_key_p_2_ns
+    case 0xa3: // pac_key_p_3_ns
+    case 0xa4: // pac_key_u_0_ns
+    case 0xa5: // pac_key_u_1_ns
+    case 0xa6: // pac_key_u_2_ns
+    case 0xa7: // pac_key_u_3_ns
+      if (!(FeatureBits[ARM::FeaturePACBTI]))
+        return MCDisassembler::Fail;
+      break;
     default:
       // Architecturally defined as unpredictable
       S = MCDisassembler::SoftFail;
       break;
     }
 
     if (Inst.getOpcode() == ARM::t2MSR_M) {
       unsigned Mask = fieldFromInstruction(Val, 10, 2);

llvm/test/CodeGen/Thumb/high-reg-clobber.mir

bb.0.entry:
     liveins: $r0
 
     ; CHECK-LABEL: name: constraint_h
     ; CHECK: liveins: $r0
     ; CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r0
     ; CHECK: tSTRspi [[COPY]], %stack.0, 0, 14 /* CC::al */, $noreg
     ; CHECK: [[tLDRspi:%[0-9]+]]:tgpr = tLDRspi %stack.0, 0, 14 /* CC::al */, $noreg
     ; CHECK: [[COPY1:%[0-9]+]]:hgpr = COPY [[tLDRspi]]
-    ; CHECK: INLINEASM &"mov r12, $0", 1 /* sideeffect attdialect */, 1048585 /* reguse:GPRnoip_and_GPRwithAPSR_NZCVnosp */, [[COPY1]], 12 /* clobber */, implicit-def early-clobber $r12
+    ; CHECK: INLINEASM &"mov r12, $0", 1 /* sideeffect attdialect */, 1048585 /* reguse:GPRnoip_and_GPRnopc */, %1, 12 /* clobber */, implicit-def early-clobber $r12
     ; CHECK: tBX_RET 14 /* CC::al */, $noreg
     ; FAST-LABEL: name: constraint_h
     ; FAST: liveins: $r0
     ; FAST: tSTRspi killed renamable $r0, %stack.0, 0, 14 /* CC::al */, $noreg
     ; FAST: renamable $r0 = tLDRspi %stack.0, 0, 14 /* CC::al */, $noreg
     ; FAST: renamable $r8 = COPY killed renamable $r0
-    ; FAST: INLINEASM &"mov r12, $0", 1 /* sideeffect attdialect */, 1048585 /* reguse:GPRnoip_and_GPRwithAPSR_NZCVnosp */, killed renamable $r8, 12 /* clobber */, implicit-def dead early-clobber $r12
+    ; FAST: INLINEASM &"mov r12, $0", 1 /* sideeffect attdialect */, 1048585 /* reguse:GPRnoip_and_GPRnopc */, killed renamable $r8, 12 /* clobber */, implicit-def dead early-clobber $r12
     ; FAST: tBX_RET 14 /* CC::al */, $noreg
     %0:tgpr = COPY $r0
     tSTRspi %0, %stack.0, 0, 14 /* CC::al */, $noreg
     %2:tgpr = tLDRspi %stack.0, 0, 14 /* CC::al */, $noreg
     %1:hgpr = COPY %2
     INLINEASM &"mov r12, $0", 1 /* sideeffect attdialect */, 1048585 /* reguse:hGPR */, %1, 12 /* clobber */, implicit-def early-clobber $r12
     tBX_RET 14 /* CC::al */, $noreg
 
 ...

llvm/test/MC/ARM/armv8.1m-pacbti-error.s

+// RUN: not llvm-mc -triple thumbv8.1m.main-arm-none-eabi -mattr=+pacbti %s -show-encoding -o - 2>&1 | FileCheck %s
+
+// CHECK: error: invalid operand for instruction
+pac r0, lr, sp
+// CHECK: error: invalid operand for instruction
+pac r12, r1, sp
+// CHECK: error: operand must be a register sp
+pac r12, lr, r2
+
+// CHECK: error: invalid operand for instruction
+aut r0, lr, sp
+// CHECK: error: invalid operand for instruction
+aut r12, r1, sp
+// CHECK: error: operand must be a register sp
+aut r12, lr, r2
+
+// CHECK: operand must be a register in range [r0, r12] or LR or PC
+autg sp, r1, r2
+// CHECK: operand must be a register in range [r0, r14]
+autg r0, pc, r2
+// CHECK: operand must be a register in range [r0, r14]
+autg r0, r1, pc
+
+// CHECK: operand must be a register in range [r0, r12] or r14
+pacg sp, r1, r2
+// CHECK: operand must be a register in range [r0, r12] or r14
+pacg pc, r1, r2
+// CHECK: operand must be a register in range [r0, r14]
+pacg r0, pc, r2
+// CHECK: operand must be a register in range [r0, r14]
+pacg r0, r1, pc
+
+// CHECK: operand must be a register in range [r0, r12] or LR or PC
+bxaut sp, r1, r2
+// CHECK: operand must be a register in range [r0, r12] or r14
+bxaut r0, sp, r2
+// CHECK: operand must be a register in range [r0, r12] or r14
+bxaut r0, pc, r2
+// CHECK: operand must be a register in range [r0, r14]
+bxaut r0, r1, pc

llvm/test/MC/ARM/armv8.1m-pacbti.s

+// RUN: llvm-mc -triple thumbv8.1m.main-arm-none-eabi -mattr=+pacbti %s -show-encoding -o - | FileCheck %s
+// RUN: not llvm-mc -triple thumbv8.1m.main-arm-none-eabi -mattr=-pacbti %s -show-encoding -o - 2>&1 | FileCheck %s --check-prefix=CHECK-NOPACBTI
+
+// CHECK: autg  r0, r1, r2              @ encoding: [0x51,0xfb,0x02,0x0f]
+// CHECK-NOPACBTI: error: instruction requires: pacbti
+autg r0, r1, r2
+// CHECK: autg  r12, lr, sp             @ encoding: [0x5e,0xfb,0x0d,0xcf]
+// CHECK-NOPACBTI: error: instruction requires: pacbti
+autg ip, lr, sp
+// CHECK: aut r12, lr, sp               @ encoding: [0xaf,0xf3,0x2d,0x80]
+aut ip, lr, sp
+// CHECK: aut r12,lr,sp               @ encoding: [0xaf,0xf3,0x2d,0x80]
+hint.w #45
+// CHECK: bxaut r0, r1, r2              @ encoding: [0x51,0xfb,0x12,0x0f]
+// CHECK-NOPACBTI: error: instruction requires: pacbti
+bxaut r0, r1, r2
+
+// CHECK: bti                           @ encoding: [0xaf,0xf3,0x0f,0x80]
+bti
+// CHECK: bti                           @ encoding: [0xaf,0xf3,0x0f,0x80]
+hint.w #15
+
+// CHECK: pacg r0, r1, r2               @ encoding: [0x61,0xfb,0x02,0xf0]
+// CHECK-NOPACBTI: error: instruction requires: pacbti
+pacg r0, r1, r2
+// CHECK: pacg r12, lr, sp              @ encoding: [0x6e,0xfb,0x0d,0xfc]
+// CHECK-NOPACBTI: error: instruction requires: pacbti
+pacg ip, lr, sp
+// CHECK: pac r12, lr, sp               @ encoding: [0xaf,0xf3,0x1d,0x80]
+pac ip, lr, sp
+// CHECK: pac r12,lr,sp               @ encoding: [0xaf,0xf3,0x1d,0x80]
+hint.w #29
+// CHECK: pacbti r12, lr, sp            @ encoding: [0xaf,0xf3,0x0d,0x80]
+pacbti ip, lr, sp
+// CHECK: pacbti r12,lr,sp            @ encoding: [0xaf,0xf3,0x0d,0x80]
+hint.w #13
+
+// CHECK: msr pac_key_p_0, r0           @ encoding: [0x80,0xf3,0x20,0x88]
+// CHECK-NOPACBTI: error: invalid operand for instruction
+msr pac_key_p_0, r0
+// CHECK: msr pac_key_p_1, r0           @ encoding: [0x80,0xf3,0x21,0x88]
+// CHECK-NOPACBTI: error: invalid operand for instruction
+msr pac_key_p_1, r0
+// CHECK: msr pac_key_p_2, r0           @ encoding: [0x80,0xf3,0x22,0x88]
+// CHECK-NOPACBTI: error: invalid operand for instruction
+msr pac_key_p_2, r0
+// CHECK: msr pac_key_p_3, r0           @ encoding: [0x80,0xf3,0x23,0x88]
+// CHECK-NOPACBTI: error: invalid operand for instruction
+msr pac_key_p_3, r0
+// CHECK: msr pac_key_u_0, r0           @ encoding: [0x80,0xf3,0x24,0x88]
+// CHECK-NOPACBTI: error: invalid operand for instruction
+msr pac_key_u_0, r0
+// CHECK: msr pac_key_u_1, r0           @ encoding: [0x80,0xf3,0x25,0x88]
+// CHECK-NOPACBTI: error: invalid operand for instruction
+msr pac_key_u_1, r0
+// CHECK: msr pac_key_u_2, r0           @ encoding: [0x80,0xf3,0x26,0x88]
+// CHECK-NOPACBTI: error: invalid operand for instruction
+msr pac_key_u_2, r0
+// CHECK: msr pac_key_u_3, r0           @ encoding: [0x80,0xf3,0x27,0x88]
+// CHECK-NOPACBTI: error: invalid operand for instruction
+msr pac_key_u_3, r0
+// CHECK: msr pac_key_p_0_ns, r0        @ encoding: [0x80,0xf3,0xa0,0x88]
+// CHECK-NOPACBTI: error: invalid operand for instruction
+msr pac_key_p_0_ns, r0
+// CHECK: msr pac_key_p_1_ns, r0        @ encoding: [0x80,0xf3,0xa1,0x88]
+// CHECK-NOPACBTI: error: invalid operand for instruction
+msr pac_key_p_1_ns, r0
+// CHECK: msr pac_key_p_2_ns, r0        @ encoding: [0x80,0xf3,0xa2,0x88]
+// CHECK-NOPACBTI: error: invalid operand for instruction
+msr pac_key_p_2_ns, r0
+// CHECK: msr pac_key_p_3_ns, r0        @ encoding: [0x80,0xf3,0xa3,0x88]
+// CHECK-NOPACBTI: error: invalid operand for instruction
+msr pac_key_p_3_ns, r0
+// CHECK: msr pac_key_u_0_ns, r0        @ encoding: [0x80,0xf3,0xa4,0x88]
+// CHECK-NOPACBTI: error: invalid operand for instruction
+msr pac_key_u_0_ns, r0
+// CHECK: msr pac_key_u_1_ns, r0        @ encoding: [0x80,0xf3,0xa5,0x88]
+// CHECK-NOPACBTI: error: invalid operand for instruction
+msr pac_key_u_1_ns, r0
+// CHECK: msr pac_key_u_2_ns, r0        @ encoding: [0x80,0xf3,0xa6,0x88]
+// CHECK-NOPACBTI: error: invalid operand for instruction
+msr pac_key_u_2_ns, r0
+// CHECK: msr pac_key_u_3_ns, r0        @ encoding: [0x80,0xf3,0xa7,0x88]
+// CHECK-NOPACBTI: error: invalid operand for instruction
+msr pac_key_u_3_ns, r0
+
+// CHECK: mrs r0, pac_key_p_0           @ encoding: [0xef,0xf3,0x20,0x80]
+// CHECK-NOPACBTI: error: invalid operand for instruction
+mrs r0, pac_key_p_0
+// CHECK: mrs r0, pac_key_p_1           @ encoding: [0xef,0xf3,0x21,0x80]
+// CHECK-NOPACBTI: error: invalid operand for instruction
+mrs r0, pac_key_p_1
+// CHECK: mrs r0, pac_key_p_2           @ encoding: [0xef,0xf3,0x22,0x80]
+// CHECK-NOPACBTI: error: invalid operand for instruction
+mrs r0, pac_key_p_2
+// CHECK: mrs r0, pac_key_p_3           @ encoding: [0xef,0xf3,0x23,0x80]
+// CHECK-NOPACBTI: error: invalid operand for instruction
+mrs r0, pac_key_p_3
+// CHECK: mrs r0, pac_key_u_0           @ encoding: [0xef,0xf3,0x24,0x80]
+// CHECK-NOPACBTI: error: invalid operand for instruction
+mrs r0, pac_key_u_0
+// CHECK: mrs r0, pac_key_u_1           @ encoding: [0xef,0xf3,0x25,0x80]
+// CHECK-NOPACBTI: error: invalid operand for instruction
+mrs r0, pac_key_u_1
+// CHECK: mrs r0, pac_key_u_2           @ encoding: [0xef,0xf3,0x26,0x80]
+// CHECK-NOPACBTI: error: invalid operand for instruction
+mrs r0, pac_key_u_2
+// CHECK: mrs r0, pac_key_u_3           @ encoding: [0xef,0xf3,0x27,0x80]
+// CHECK-NOPACBTI: error: invalid operand for instruction
+mrs r0, pac_key_u_3
+// CHECK: mrs r0, pac_key_p_0_ns        @ encoding: [0xef,0xf3,0xa0,0x80]
+// CHECK-NOPACBTI: error: invalid operand for instruction
+mrs r0, pac_key_p_0_ns
+// CHECK: mrs r0, pac_key_p_1_ns        @ encoding: [0xef,0xf3,0xa1,0x80]
+// CHECK-NOPACBTI: error: invalid operand for instruction
+mrs r0, pac_key_p_1_ns
+// CHECK: mrs r0, pac_key_p_2_ns        @ encoding: [0xef,0xf3,0xa2,0x80]
+// CHECK-NOPACBTI: error: invalid operand for instruction
+mrs r0, pac_key_p_2_ns
+// CHECK: mrs r0, pac_key_p_3_ns        @ encoding: [0xef,0xf3,0xa3,0x80]
+// CHECK-NOPACBTI: error: invalid operand for instruction
+mrs r0, pac_key_p_3_ns
+// CHECK: mrs r0, pac_key_u_0_ns        @ encoding: [0xef,0xf3,0xa4,0x80]
+// CHECK-NOPACBTI: error: invalid operand for instruction
+mrs r0, pac_key_u_0_ns
+// CHECK: mrs r0, pac_key_u_1_ns        @ encoding: [0xef,0xf3,0xa5,0x80]
+// CHECK-NOPACBTI: error: invalid operand for instruction
+mrs r0, pac_key_u_1_ns
+// CHECK: mrs r0, pac_key_u_2_ns        @ encoding: [0xef,0xf3,0xa6,0x80]
+// CHECK-NOPACBTI: error: invalid operand for instruction
+mrs r0, pac_key_u_2_ns
+// CHECK: mrs r0, pac_key_u_3_ns        @ encoding: [0xef,0xf3,0xa7,0x80]
+// CHECK-NOPACBTI: error: invalid operand for instruction
+mrs r0, pac_key_u_3_ns

llvm/test/MC/ARM/implicit-it-generation-v8.s

+@ RUN: llvm-mc -triple thumbv8.1m.main-arm-none-eabi -arm-implicit-it=always -mattr=+pacbti < %s -show-encoding | FileCheck %s
+
+autgeq r0, r1, r2
+pacgeq r0, r1, r2
+bxauteq r0, r1, r2
+@ CHECK: ittt eq
+@ CHECK: autgeq r0, r1, r2
+@ CHECK: pacgeq r0, r1, r2
+@ CHECK: bxauteq r0, r1, r2

llvm/test/MC/Disassembler/ARM/armv8.1m-pacbti.txt

+# RUN: llvm-mc -triple thumbv8.1m.main-arm-none-eabi -mattr=+pacbti -disassemble %s 2> /dev/null | FileCheck %s
+
+0x51,0xfb,0x02,0x0f
+0x5e,0xfb,0x0d,0xcf
+0xaf,0xf3,0x2d,0x80
+0x51,0xfb,0x12,0x0f
+0xaf,0xf3,0x0f,0x80
+0x61,0xfb,0x02,0xf0
+0x6e,0xfb,0x0d,0xfc
+0xaf,0xf3,0x1d,0x80
+0xaf,0xf3,0x0d,0x80
+0x80,0xf3,0x20,0x88
+0x80,0xf3,0x21,0x88
+0x80,0xf3,0x22,0x88
+0x80,0xf3,0x23,0x88
+0x80,0xf3,0x24,0x88
+0x80,0xf3,0x25,0x88
+0x80,0xf3,0x26,0x88
+0x80,0xf3,0x27,0x88
+0x80,0xf3,0xa0,0x88
+0x80,0xf3,0xa1,0x88
+0x80,0xf3,0xa2,0x88
+0x80,0xf3,0xa3,0x88
+0x80,0xf3,0xa4,0x88
+0x80,0xf3,0xa5,0x88
+0x80,0xf3,0xa6,0x88
+0x80,0xf3,0xa7,0x88
+0xef,0xf3,0x20,0x80
+0xef,0xf3,0x21,0x80
+0xef,0xf3,0x22,0x80
+0xef,0xf3,0x23,0x80
+0xef,0xf3,0x24,0x80
+0xef,0xf3,0x25,0x80
+0xef,0xf3,0x26,0x80
+0xef,0xf3,0x27,0x80
+0xef,0xf3,0xa0,0x80
+0xef,0xf3,0xa1,0x80
+0xef,0xf3,0xa2,0x80
+0xef,0xf3,0xa3,0x80
+0xef,0xf3,0xa4,0x80
+0xef,0xf3,0xa5,0x80
+0xef,0xf3,0xa6,0x80
+0xef,0xf3,0xa7,0x80
+
+# Test softfail encodings
+0xa7,0xf3,0x1d,0x80
+0xab,0xf3,0x1d,0x80
+0xad,0xf3,0x1d,0x80
+0xae,0xf3,0x1d,0x80
+0xaf,0xf3,0x1d,0x88
+0xaf,0xf3,0x1d,0xa0
+0xaf,0xf3,0x2d,0x80
+0xab,0xf3,0x2d,0x80
+0xad,0xf3,0x2d,0x80
+0xae,0xf3,0x2d,0x80
+0xaf,0xf3,0x2d,0x88
+0xaf,0xf3,0x2d,0xa0
+0xa7,0xf3,0x0f,0x80
+0xab,0xf3,0x0f,0x80
+0xad,0xf3,0x0f,0x80
+0xae,0xf3,0x0f,0x80
+0xaf,0xf3,0x0f,0x88
+0xaf,0xf3,0x0f,0xa0
+0xa7,0xf3,0x0d,0x80
+0xab,0xf3,0x0d,0x80
+0xad,0xf3,0x0d,0x80
+0xae,0xf3,0x0d,0x80
+0xaf,0xf3,0x0d,0x88
+0xaf,0xf3,0x0d,0xa0
+
+# CHECK: autg     r0, r1, r2
+# CHECK: autg     r12, lr, sp
+# CHECK: aut      r12, lr, sp
+# CHECK: bxaut    r0, r1, r2
+# CHECK: bti
+# CHECK: pacg     r0, r1, r2
+# CHECK: pacg     r12, lr, sp
+# CHECK: pac      r12, lr, sp
+# CHECK: pacbti   r12, lr, sp
+# CHECK: msr  pac_key_p_0, r0
+# CHECK: msr  pac_key_p_1, r0
+# CHECK: msr  pac_key_p_2, r0
+# CHECK: msr  pac_key_p_3, r0
+# CHECK: msr  pac_key_u_0, r0
+# CHECK: msr  pac_key_u_1, r0
+# CHECK: msr  pac_key_u_2, r0
+# CHECK: msr  pac_key_u_3, r0
+# CHECK: msr  pac_key_p_0_ns, r0
+# CHECK: msr  pac_key_p_1_ns, r0
+# CHECK: msr  pac_key_p_2_ns, r0
+# CHECK: msr  pac_key_p_3_ns, r0
+# CHECK: msr  pac_key_u_0_ns, r0
+# CHECK: msr  pac_key_u_1_ns, r0
+# CHECK: msr  pac_key_u_2_ns, r0
+# CHECK: msr  pac_key_u_3_ns, r0
+# CHECK: mrs  r0, pac_key_p_0
+# CHECK: mrs  r0, pac_key_p_1
+# CHECK: mrs  r0, pac_key_p_2
+# CHECK: mrs  r0, pac_key_p_3
+# CHECK: mrs  r0, pac_key_u_0
+# CHECK: mrs  r0, pac_key_u_1
+# CHECK: mrs  r0, pac_key_u_2
+# CHECK: mrs  r0, pac_key_u_3
+# CHECK: mrs  r0, pac_key_p_0_ns
+# CHECK: mrs  r0, pac_key_p_1_ns
+# CHECK: mrs  r0, pac_key_p_2_ns
+# CHECK: mrs  r0, pac_key_p_3_ns
+# CHECK: mrs  r0, pac_key_u_0_ns
+# CHECK: mrs  r0, pac_key_u_1_ns
+# CHECK: mrs  r0, pac_key_u_2_ns
+# CHECK: mrs  r0, pac_key_u_3_ns
+
+# Softfail encodings
+# CHECK: pac      r12, lr, sp
+# CHECK: pac      r12, lr, sp
+# CHECK: pac      r12, lr, sp
+# CHECK: pac      r12, lr, sp
+# CHECK: pac      r12, lr, sp
+# CHECK: pac      r12, lr, sp
+# CHECK: aut      r12, lr, sp
+# CHECK: aut      r12, lr, sp
+# CHECK: aut      r12, lr, sp
+# CHECK: aut      r12, lr, sp
+# CHECK: aut      r12, lr, sp
+# CHECK: aut      r12, lr, sp
+# CHECK: bti
+# CHECK: bti
+# CHECK: bti
+# CHECK: bti
+# CHECK: bti
+# CHECK: bti
+# CHECK: pacbti   r12, lr, sp
+# CHECK: pacbti   r12, lr, sp
+# CHECK: pacbti   r12, lr, sp
+# CHECK: pacbti   r12, lr, sp
+# CHECK: pacbti   r12, lr, sp
+# CHECK: pacbti   r12, lr, sp