[PowerPC] Add intrinsic to convert between ppc_fp128 and fp128

[qiucf]

Summary

ppc_fp128 and fp128 are both 128-bit floating point types. However, we can't do conversion between them now. (trunc/ext are not allowed for same-size fp types)

This patch adds two new intrinsics: llvm.ppc.convert.f128.to.ppcf128 and llvm.convert.ppcf128.to.f128, to support such conversion.

[efriedma]

This could be a powerpc-specific intrinsic, maybe? I guess that basically just shoving around the code a bit, but maybe clearer to readers. The name is also a little ambiguous: it's not clear from the name that the target type must be fp128.

Long-term, we might want to consider replacing fpext/fptrunc instructions with something like fpconv. We now have two pairs of floating-point types that have the same size, and if we ever add more floating-point types, the problems will just get more complicated.

llvm/lib/IR/Function.cpp

1031 ↗

(On Diff #371269)

Please define a new IITDescriptorKind for this.

[qiucf]

Make it a PowerPC intrinsic.

[shchenz]

Thanks for doing this. Looks reasonable to me. Some code format comments.

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

10390

Lint warnings.

Do we need a local variable for LC?

11031

Can we put this also in LowerINTRINSIC_WO_CHAIN? and call LowerINTRINSIC_WO_CHAIN here? So we can have a concentrated place for the ppc128/f128 conversion?

11039

no need for local Op?

[shchenz]

LGTM. Thanks.

Better to wait for several days in case other reviewers have comments.

[qiucf]

Rebase and fix typo

llvm/include/llvm/IR/IntrinsicsPowerPC.td

def int_ppc_compare_exp_eq : GCCBuiltin<"__builtin_ppc_compare_exp_eq">,
                                          [llvm_double_ty, llvm_double_ty], 
                                          [IntrNoMem]>;
   def int_ppc_test_data_class_d : Intrinsic<[llvm_i32_ty],
                                             [llvm_double_ty, llvm_i32_ty],
                                             [IntrNoMem, ImmArg<ArgIndex<1>>]>;
   def int_ppc_test_data_class_f : Intrinsic<[llvm_i32_ty],
                                             [llvm_float_ty, llvm_i32_ty],
                                             [IntrNoMem, ImmArg<ArgIndex<1>>]>;
+
+  def int_ppc_convert_f128_to_ppcf128
+      : Intrinsic<[llvm_ppcf128_ty], [llvm_f128_ty], [IntrNoMem]>;
+  def int_ppc_convert_ppcf128_to_f128
+      : Intrinsic<[llvm_f128_ty], [llvm_ppcf128_ty], [IntrNoMem]>;
 }
 
 //===----------------------------------------------------------------------===//
 // PowerPC Atomic Intrinsic Definitions.
 let TargetPrefix = "ppc" in {
   class AtomicRMW128Intrinsic
     : Intrinsic<[llvm_i64_ty, llvm_i64_ty],
                 [llvm_ptr_ty, llvm_i64_ty, llvm_i64_ty],

llvm/include/llvm/IR/RuntimeLibcalls.def

 HANDLE_LIBCALL(UINTTOFP_I64_F128, "__floatunditf")
 HANDLE_LIBCALL(UINTTOFP_I64_PPCF128, "__floatunditf")
 HANDLE_LIBCALL(UINTTOFP_I128_F16, "__floatuntihf")
 HANDLE_LIBCALL(UINTTOFP_I128_F32, "__floatuntisf")
 HANDLE_LIBCALL(UINTTOFP_I128_F64, "__floatuntidf")
 HANDLE_LIBCALL(UINTTOFP_I128_F80, "__floatuntixf")
 HANDLE_LIBCALL(UINTTOFP_I128_F128, "__floatuntitf")
 HANDLE_LIBCALL(UINTTOFP_I128_PPCF128, "__floatuntitf")
+HANDLE_LIBCALL(CONVERT_F128_PPCF128, "__extendkftf2")
+HANDLE_LIBCALL(CONVERT_PPCF128_F128, "__trunctfkf2")
 
 // Comparison
 HANDLE_LIBCALL(OEQ_F32, "__eqsf2")
 HANDLE_LIBCALL(OEQ_F64, "__eqdf2")
 HANDLE_LIBCALL(OEQ_F128, "__eqtf2")
 HANDLE_LIBCALL(OEQ_PPCF128, "__gcc_qeq")
 HANDLE_LIBCALL(UNE_F32, "__nesf2")
 HANDLE_LIBCALL(UNE_F64, "__nedf2")

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

case Intrinsic::ppc_altivec_vcmpgtuq_p:
     case Intrinsic::ppc_altivec_vcmpequq_p:
       CompareOpc = 455;
       break;
     case Intrinsic::ppc_altivec_vcmpgtsq_p:
       CompareOpc = 903;
       break;
     case Intrinsic::ppc_altivec_vcmpgtuq_p:
       CompareOpc = 647;
       break;
     }
     isDot = true;
     break;
   }
   return true;
 }
 
 /// LowerINTRINSIC_WO_CHAIN - If this is an intrinsic that we want to custom
return SDValue(
             PPC::SELECT_CC_I4, dl, MVT::i32,
             {SDValue(DAG.getMachineNode(CmprOpc, dl, MVT::i32, Op.getOperand(2),
                                         Op.getOperand(1)),
                      0),
              DAG.getConstant(1, dl, MVT::i32), DAG.getConstant(0, dl, MVT::i32),
              DAG.getTargetConstant(PPC::PRED_EQ, dl, MVT::i32)}),
         0);
   }
+  case Intrinsic::ppc_convert_f128_to_ppcf128:
+  case Intrinsic::ppc_convert_ppcf128_to_f128: {
+    RTLIB::Libcall LC = IntrinsicID == Intrinsic::ppc_convert_ppcf128_to_f128
+                            ? RTLIB::CONVERT_PPCF128_F128
+                            : RTLIB::CONVERT_F128_PPCF128;
+    MakeLibCallOptions CallOptions;
+    std::pair<SDValue, SDValue> Result =
+        makeLibCall(DAG, LC, Op.getValueType(), Op.getOperand(1), CallOptions,
+                    dl, SDValue());
+    return Result.first;
+  }
   }
 
   // If this is a lowered altivec predicate compare, CompareOpc is set to the
   // opcode number of the comparison.
   int CompareOpc;
   bool isDot;
   if (!getVectorCompareInfo(Op, CompareOpc, isDot, Subtarget))
     return SDValue();    // Don't custom lower most intrinsics.
SDValue PPCTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
 
   case ISD::INLINEASM:
   case ISD::INLINEASM_BR:       return LowerINLINEASM(Op, DAG);
   // Variable argument lowering.
   case ISD::VASTART:            return LowerVASTART(Op, DAG);
   case ISD::VAARG:              return LowerVAARG(Op, DAG);
   case ISD::VACOPY:             return LowerVACOPY(Op, DAG);
 
   case ISD::STACKRESTORE:       return LowerSTACKRESTORE(Op, DAG);
   case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
   case ISD::GET_DYNAMIC_AREA_OFFSET:
     return LowerGET_DYNAMIC_AREA_OFFSET(Op, DAG);
 
   // Exception handling lowering.
   case ISD::EH_DWARF_CFA:       return LowerEH_DWARF_CFA(Op, DAG);
   case ISD::EH_SJLJ_SETJMP:     return lowerEH_SJLJ_SETJMP(Op, DAG);
   case ISD::EH_SJLJ_LONGJMP:    return lowerEH_SJLJ_LONGJMP(Op, DAG);
 
   case ISD::LOAD:               return LowerLOAD(Op, DAG);
   case ISD::STORE:              return LowerSTORE(Op, DAG);
   case ISD::TRUNCATE:           return LowerTRUNCATE(Op, DAG);
   case ISD::SELECT_CC:          return LowerSELECT_CC(Op, DAG);
   case ISD::STRICT_FP_TO_UINT:
   case ISD::STRICT_FP_TO_SINT:
   case ISD::FP_TO_UINT:
case ISD::INTRINSIC_W_CHAIN: {
     SDValue NewInt = DAG.getNode(N->getOpcode(), dl, VTs, N->getOperand(0),
                                  N->getOperand(1));
 
     Results.push_back(DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, NewInt));
     Results.push_back(NewInt.getValue(1));
     break;
   }
   case ISD::INTRINSIC_WO_CHAIN: {
-    unsigned IntrinsicID =
-        cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
-
-    if (IntrinsicID == Intrinsic::ppc_pack_longdouble)
+    switch (cast<ConstantSDNode>(N->getOperand(0))->getZExtValue()) {
+    case Intrinsic::ppc_pack_longdouble:
       Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::ppcf128,
                                     N->getOperand(2), N->getOperand(1)));
       break;
+    case Intrinsic::ppc_convert_f128_to_ppcf128:
+      Results.push_back(LowerINTRINSIC_WO_CHAIN(SDValue(N, 0), DAG));
+      break;
+    }
+    break;
   }
   case ISD::VAARG: {
     if (!Subtarget.isSVR4ABI() || Subtarget.isPPC64())
       return;
 
     EVT VT = N->getValueType(0);
 
     if (VT == MVT::i64) {

llvm/test/CodeGen/PowerPC/f128-truncateNconv.ll

 entry:
   %0 = load fp128, fp128* %a, align 16
   %1 = load fp128, fp128* %b, align 16
   %add = fadd fp128 %0, %1
   %conv = fptoui fp128 %add to i8
   store i8 %conv, i8* %res, align 1
   ret void
 }
+
+define void @qpConvppcf128(fp128 %src, ppc_fp128* %dst) {
+; CHECK-LABEL: qpConvppcf128:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    mflr r0
+; CHECK-NEXT:    .cfi_def_cfa_offset 48
+; CHECK-NEXT:    .cfi_offset lr, 16
+; CHECK-NEXT:    .cfi_offset r30, -16
+; CHECK-NEXT:    std r30, -16(r1) # 8-byte Folded Spill
+; CHECK-NEXT:    std r0, 16(r1)
+; CHECK-NEXT:    stdu r1, -48(r1)
+; CHECK-NEXT:    mr r30, r5
+; CHECK-NEXT:    bl __extendkftf2
+; CHECK-NEXT:    nop
+; CHECK-NEXT:    stfd f2, 8(r30)
+; CHECK-NEXT:    stfd f1, 0(r30)
+; CHECK-NEXT:    addi r1, r1, 48
+; CHECK-NEXT:    ld r0, 16(r1)
+; CHECK-NEXT:    ld r30, -16(r1) # 8-byte Folded Reload
+; CHECK-NEXT:    mtlr r0
+; CHECK-NEXT:    blr
+;
+; CHECK-P8-LABEL: qpConvppcf128:
+; CHECK-P8:       # %bb.0: # %entry
+; CHECK-P8-NEXT:    mflr r0
+; CHECK-P8-NEXT:    .cfi_def_cfa_offset 48
+; CHECK-P8-NEXT:    .cfi_offset lr, 16
+; CHECK-P8-NEXT:    .cfi_offset r30, -16
+; CHECK-P8-NEXT:    std r30, -16(r1) # 8-byte Folded Spill
+; CHECK-P8-NEXT:    std r0, 16(r1)
+; CHECK-P8-NEXT:    stdu r1, -48(r1)
+; CHECK-P8-NEXT:    mr r30, r5
+; CHECK-P8-NEXT:    bl __extendkftf2
+; CHECK-P8-NEXT:    nop
+; CHECK-P8-NEXT:    stfd f2, 8(r30)
+; CHECK-P8-NEXT:    stfd f1, 0(r30)
+; CHECK-P8-NEXT:    addi r1, r1, 48
+; CHECK-P8-NEXT:    ld r0, 16(r1)
+; CHECK-P8-NEXT:    ld r30, -16(r1) # 8-byte Folded Reload
+; CHECK-P8-NEXT:    mtlr r0
+; CHECK-P8-NEXT:    blr
+entry:
+  %res = call ppc_fp128 @llvm.ppc.convert.f128.to.ppcf128(fp128 %src)
+  store ppc_fp128 %res, ppc_fp128* %dst, align 16
+  ret void
+}
+
+define void @ppcf128Convqp(ppc_fp128 %src, fp128* %dst) {
+; CHECK-LABEL: ppcf128Convqp:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    mflr r0
+; CHECK-NEXT:    .cfi_def_cfa_offset 48
+; CHECK-NEXT:    .cfi_offset lr, 16
+; CHECK-NEXT:    .cfi_offset r30, -16
+; CHECK-NEXT:    std r30, -16(r1) # 8-byte Folded Spill
+; CHECK-NEXT:    std r0, 16(r1)
+; CHECK-NEXT:    stdu r1, -48(r1)
+; CHECK-NEXT:    mr r30, r5
+; CHECK-NEXT:    bl __trunctfkf2
+; CHECK-NEXT:    nop
+; CHECK-NEXT:    stxv v2, 0(r30)
+; CHECK-NEXT:    addi r1, r1, 48
+; CHECK-NEXT:    ld r0, 16(r1)
+; CHECK-NEXT:    ld r30, -16(r1) # 8-byte Folded Reload
+; CHECK-NEXT:    mtlr r0
+; CHECK-NEXT:    blr
+;
+; CHECK-P8-LABEL: ppcf128Convqp:
+; CHECK-P8:       # %bb.0: # %entry
+; CHECK-P8-NEXT:    mflr r0
+; CHECK-P8-NEXT:    .cfi_def_cfa_offset 48
+; CHECK-P8-NEXT:    .cfi_offset lr, 16
+; CHECK-P8-NEXT:    .cfi_offset r30, -16
+; CHECK-P8-NEXT:    std r30, -16(r1) # 8-byte Folded Spill
+; CHECK-P8-NEXT:    std r0, 16(r1)
+; CHECK-P8-NEXT:    stdu r1, -48(r1)
+; CHECK-P8-NEXT:    mr r30, r5
+; CHECK-P8-NEXT:    bl __trunctfkf2
+; CHECK-P8-NEXT:    nop
+; CHECK-P8-NEXT:    stvx v2, 0, r30
+; CHECK-P8-NEXT:    addi r1, r1, 48
+; CHECK-P8-NEXT:    ld r0, 16(r1)
+; CHECK-P8-NEXT:    ld r30, -16(r1) # 8-byte Folded Reload
+; CHECK-P8-NEXT:    mtlr r0
+; CHECK-P8-NEXT:    blr
+entry:
+  %res = call fp128 @llvm.ppc.convert.ppcf128.to.f128(ppc_fp128 %src)
+  store fp128 %res, fp128* %dst, align 16
+  ret void
+}
+
+declare ppc_fp128 @llvm.ppc.convert.f128.to.ppcf128(fp128)
+declare fp128 @llvm.ppc.convert.ppcf128.to.f128(ppc_fp128)