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[RISCV][Clang] Add more RVV Floating-Point intrinsic functions.

Authored by khchen on Mar 31 2021, 9:45 AM.



Support below instructions.

  1. Vector Widening Floating-Point Add/Subtract Instructions
  2. Vector Widening Floating-Point Multiply
  3. Vector Single-Width Floating-Point Fused Multiply-Add Instructions
  4. Vector Widening Floating-Point Fused Multiply-Add Instructions
  5. Vector Floating-Point Compare Instructions

Diff Detail

Event Timeline

khchen created this revision.Mar 31 2021, 9:45 AM
khchen requested review of this revision.Mar 31 2021, 9:45 AM
Herald added a project: Restricted Project. · View Herald TranscriptMar 31 2021, 9:45 AM
khchen updated this revision to Diff 334659.Apr 1 2021, 5:40 AM

rebase and refine multiclass.

HsiangKai added inline comments.Apr 6 2021, 12:21 AM

why is there not -3 in Log2LMUL?



khchen marked 2 inline comments as done.Apr 6 2021, 6:43 AM
khchen added inline comments.

Because there is no vector floating type with mf8.
The minimum faction LMUL for floating is mf2 and half float is mf4.
In fact, we can give all LMUL combinations because the clang generator will make sure the type is legal.

craig.topper added inline comments.Apr 6 2021, 10:15 AM

Since we're not generating "h" here it should either be all LMULs or remove -2 as well.


Can we line up the colons here so that RVVFloatingTerBuiltinSet is in the same place in every line?


Are we going to fix the inconsistency with vfwadd_vf?

khchen updated this revision to Diff 335846.Apr 7 2021, 9:37 AM
khchen marked 4 inline comments as done.

address Craig's comments.

This revision is now accepted and ready to land.Apr 7 2021, 10:06 AM
khchen updated this revision to Diff 336117.Apr 8 2021, 8:17 AM


I don't know why let cannot overide field when we change instantiate single multiclasses to inheritance.

This revision was landed with ongoing or failed builds.Sun, Apr 11, 7:30 PM
This revision was automatically updated to reflect the committed changes.