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[RISCV][Clang] Add some RVV Integer intrinsic functions.

Authored by khchen on Mar 29 2021, 11:40 AM.


  1. Rename RVVBinBuiltin to RVVOutputOp1Builtin because it is not related

to the number of operand.

  1. Add RVV Integer instuctions which use RVVOutputOp1Builtin.

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khchen created this revision.Mar 29 2021, 11:40 AM
khchen requested review of this revision.Mar 29 2021, 11:40 AM
Herald added a project: Restricted Project. · View Herald TranscriptMar 29 2021, 11:40 AM

So sorry.. those huge tests make the browser so slowly, should I split them in the different patch?

craig.topper added inline comments.Mar 29 2021, 2:04 PM

Should we have a common class for vadd/vsub/vand/vxor/vor. They all have the same argments except for the name.

Or maybe a common class for signed binary ops and unsigned binary ops. And some can just instantiate both classes? That would allow us to pick up min/max and shifts as well.

khchen updated this revision to Diff 334164.Mar 30 2021, 7:34 AM
  1. Address Craig's comments.
  2. I didn't add common class for shift instruction. I will add it when we add

other shift instruction which have the same argments. Does it make sense?

This revision is now accepted and ready to land.Mar 30 2021, 11:32 AM
This revision was automatically updated to reflect the committed changes.