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[RISCV] Add legality check for vectoring reduction
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Authored by luke957 on Mar 29 2021, 8:15 AM.

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Summary

Check if it is legal to vectorize reduction.

Diff Detail

Event Timeline

luke957 created this revision.Mar 29 2021, 8:15 AM
luke957 requested review of this revision.Mar 29 2021, 8:15 AM
Herald added a project: Restricted Project. · View Herald TranscriptMar 29 2021, 8:15 AM
frasercrmck added inline comments.Mar 29 2021, 8:20 AM
llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
132

We support the fixed-length vector reductions. Can we add support for that too?

151

We don't support the fmin/fmax reductions yet. I suspect this would crash in the backend?

craig.topper added inline comments.Mar 29 2021, 11:05 AM
llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
133

This is returning true for not scalable. Is that saying that any fixed length reduction is supported?

craig.topper retitled this revision from [RISCV] Add legality check for vectoring redunction to [RISCV] Add legality check for vectoring reduction.Mar 29 2021, 1:52 PM
luke957 added inline comments.Apr 5 2021, 9:22 AM
llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
132

Can we just retrun true when VF is not scalable to support fixed-length vector reductions?

133

I understand returning true for not scalable is just to make canVectorizeReductions() in LoopVectorizer.cpp return right value. There will be other checks after canVectorizeReductions() returns.

luke957 added inline comments.Apr 5 2021, 9:32 AM
llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
151

The added test case contains a fmin case. For opt -loop-vectorize, it seems no crash.

craig.topper added inline comments.Apr 5 2021, 10:16 AM
llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
151

The crash would be in llc in SelectionDAG, not opt.

craig.topper added inline comments.Apr 5 2021, 10:20 AM
llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
133

Let me rephrase a little. You're returning true for fixed vectors, but not checking element type or opcode or hasStdExtV. Does the the mean the vectorizer will start generating reductions for vectors of i128. Or reductions of floats when the F extension isn't enabled?

dmgreen added inline comments.
llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
133

I believe the "legal" in this function really means "are you going to crash if there is a reduction of this type". Normal non-scalable reductions can always be legalized to something, even if that mean expanding or scalarizing or converting to soft float.

The standard costmodelling then kicks in to say whether it is actually a good idea. i.e work the same as X86/Arm/etc. (But, because they are outside the loop, the vectorizer doesn't account for them directly, only the arithmetic instructions that will be in the loop. The assumption is what is in the loop will dominate performance).

luke957 updated this revision to Diff 335822.Wed, Apr 7, 8:34 AM
luke957 added inline comments.Wed, Apr 7, 8:38 AM
llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
133

I think so. But as StdExtV is optional for riscv, hasStdExtV() check might still be needed.

151

Silly of me. Add fixme for fmin/fmax.

craig.topper added inline comments.Wed, Apr 7, 11:28 AM
llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
153

Please wrap this to 80 columns.

llvm/test/Transforms/LoopVectorize/RISCV/scalable-reductions.ll
355

"end emit a warning" -> "and emit a warning"?

luke957 updated this revision to Diff 336029.Thu, Apr 8, 1:25 AM
luke957 added inline comments.Thu, Apr 8, 1:36 AM
llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
153

Fixed.

llvm/test/Transforms/LoopVectorize/RISCV/scalable-reductions.ll
355

Fix typo. Remove fmin and fmax test cases.

frasercrmck added inline comments.Thu, Apr 15, 3:20 AM
llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
135

I'm wondering if returning true for fixed-length vectors, even if correct (i.e. not crashing), is likely to produce worse code. Will it trick the cost modeling into producing code which we'll then expand during legalization, and increase register pressure and the likelihood of spilling?

craig.topper added inline comments.Thu, Apr 15, 9:09 AM
llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
130

There should be a blank line above this.

135

For most reductions the expansion should be log2(elements) SingleSrcPermute shuffles and binops to reduce elements by half each step. So it shouldn't increase the register pressure much since you just need 2 registers. This should match the default cost model for getArithmeticReductionCost/getMinMaxReductionCost.

That isn't what happens for ordered floating point reduction though, but it also doesn't look like this function is told that it is an ordered reduction. It doesn't look like getArithmeticReductionCost get's told either. Maybe we only vectorize to unordered?

craig.topper added inline comments.Thu, Apr 15, 9:24 AM
llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
135

I think the ordered propery is in RecurrenceDescriptor after https://reviews.llvm.org/D98435. But getArithmeticReductionCost/getMinMaxReductionCost don't receive the RecurrenceDescriptor.

frasercrmck added inline comments.Fri, Apr 16, 2:43 AM
llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
135

Yeah fair enough, that sounds fine then. Part of me also finds it weird that we'd say it's legal to generate a fixed-length fmin/fmax/mul reduction even though we'd expand it 100% of the time. But perhaps it's just that this API's job isn't perfectly clear.

luke957 updated this revision to Diff 339667.Thu, Apr 22, 8:58 AM
luke957 added inline comments.Thu, Apr 22, 9:35 AM
llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
135

The ordered propery is added for RecurrenceDescriptor in https://reviews.llvm.org/D98435 while in-order reduction support is off by default and controlled with the -enable-strict-reductions flag. Would ordered floating point reduction be fixed in function InnerLoopVectorizer::fixVectorizedLoop() if -enable-strict-reductions flag is used?

135

I agree the API's name is weird.

frasercrmck added inline comments.Wed, May 5, 8:58 AM
llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
154

You can update this now that D101518 went through.