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Differential D98599

[AArch64] Zero extended extract_vector_elt pattern
ClosedPublic

Authored by dmgreen on Mar 14 2021, 8:20 AM.

Details

Reviewers
fhahn
efriedma
SjoerdMeijer
NickGuy
t.p.northover
sdesmalen
david-arm
Commits
rG0b2aae42e5ea: [AArch64] Zero extended extract_vector_elt pattern
Summary

This adds a pattern for i64 zext_inreg(i32 extract_vector_elt X), producing a single UMOVvi16 instruction that is already expected to clear the top bits. The exact pattern that this matches is and(anyext(vector_extract X, lane), 0xff), similar to the sext patterns higher up in the same file.

Diff Detail

Event Timeline

dmgreen created this revision.Mar 14 2021, 8:20 AM
Herald added subscribers: danielkiss, hiraditya, kristof.beyls. · View Herald TranscriptMar 14 2021, 8:20 AM
dmgreen requested review of this revision.Mar 14 2021, 8:20 AM
Herald added a project: Restricted Project. · View Herald TranscriptMar 14 2021, 8:20 AM
Harbormaster completed remote builds in B93708: Diff 330505.Mar 14 2021, 8:21 AM
dmgreen added reviewers: sdesmalen, david-arm.Mar 14 2021, 8:21 AM
sdesmalen accepted this revision.Mar 15 2021, 2:10 AM

Looks like a valid pattern, and a nice improvement, thanks.

This revision is now accepted and ready to land.Mar 15 2021, 2:10 AM
This revision was landed with ongoing or failed builds.Mar 15 2021, 7:56 AM
Closed by commit rG0b2aae42e5ea: [AArch64] Zero extended extract_vector_elt pattern (authored by dmgreen). · Explain Why
This revision was automatically updated to reflect the committed changes.
dmgreen added a commit: rG0b2aae42e5ea: [AArch64] Zero extended extract_vector_elt pattern.

Revision Contents

PathSize
llvm/
lib/
Target/
AArch64/
7 lines
test/
CodeGen/
AArch64/
32 lines

Diff 330505

llvm/lib/Target/AArch64/AArch64InstrInfo.td

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// bits of the destination register. // bits of the destination register.
def : Pat<(and (vector_extract (v16i8 V128:$Rn), VectorIndexB:$idx), def : Pat<(and (vector_extract (v16i8 V128:$Rn), VectorIndexB:$idx),
(i32 0xff)), (i32 0xff)),
(i32 (UMOVvi8 V128:$Rn, VectorIndexB:$idx))>; (i32 (UMOVvi8 V128:$Rn, VectorIndexB:$idx))>;
def : Pat<(and (vector_extract (v8i16 V128:$Rn), VectorIndexH:$idx), def : Pat<(and (vector_extract (v8i16 V128:$Rn), VectorIndexH:$idx),
(i32 0xffff)), (i32 0xffff)),
(i32 (UMOVvi16 V128:$Rn, VectorIndexH:$idx))>; (i32 (UMOVvi16 V128:$Rn, VectorIndexH:$idx))>;
def : Pat<(i64 (and (i64 (anyext (i32 (vector_extract (v16i8 V128:$Rn),
VectorIndexB:$idx)))), (i64 0xff))),
(SUBREG_TO_REG (i64 0), (i32 (UMOVvi8 V128:$Rn, VectorIndexB:$idx)), sub_32)>;
def : Pat<(i64 (and (i64 (anyext (i32 (vector_extract (v8i16 V128:$Rn),
VectorIndexH:$idx)))), (i64 0xffff))),
(SUBREG_TO_REG (i64 0), (i32 (UMOVvi16 V128:$Rn, VectorIndexH:$idx)), sub_32)>;
defm INS : SIMDIns; defm INS : SIMDIns;
def : Pat<(v16i8 (scalar_to_vector GPR32:$Rn)), def : Pat<(v16i8 (scalar_to_vector GPR32:$Rn)),
(SUBREG_TO_REG (i32 0), (SUBREG_TO_REG (i32 0),
(f32 (COPY_TO_REGCLASS GPR32:$Rn, FPR32)), ssub)>; (f32 (COPY_TO_REGCLASS GPR32:$Rn, FPR32)), ssub)>;
def : Pat<(v8i8 (scalar_to_vector GPR32:$Rn)), def : Pat<(v8i8 (scalar_to_vector GPR32:$Rn)),
(SUBREG_TO_REG (i32 0), (SUBREG_TO_REG (i32 0),
(f32 (COPY_TO_REGCLASS GPR32:$Rn, FPR32)), ssub)>; (f32 (COPY_TO_REGCLASS GPR32:$Rn, FPR32)), ssub)>;
▲ Show 20 Lines • Show All 2,610 Lines • Show Last 20 Lines

llvm/test/CodeGen/AArch64/build-vector-extract.ll

Show First 20 Lines • Show All 202 Lines • ▼ Show 20 Lines; CHECK-NEXT: ret
%r = insertelement <2 x i64> zeroinitializer, i64 %z, i32 1 %r = insertelement <2 x i64> zeroinitializer, i64 %z, i32 1
ret <2 x i64> %r ret <2 x i64> %r
} }
define <2 x i64> @extract0_i16_zext_insert0_i64_undef(<8 x i16> %x) { define <2 x i64> @extract0_i16_zext_insert0_i64_undef(<8 x i16> %x) {
; CHECK-LABEL: extract0_i16_zext_insert0_i64_undef: ; CHECK-LABEL: extract0_i16_zext_insert0_i64_undef:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: umov w8, v0.h[0] ; CHECK-NEXT: umov w8, v0.h[0]
; CHECK-NEXT: and x8, x8, #0xffff
; CHECK-NEXT: fmov d0, x8 ; CHECK-NEXT: fmov d0, x8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%e = extractelement <8 x i16> %x, i32 0 %e = extractelement <8 x i16> %x, i32 0
%z = zext i16 %e to i64 %z = zext i16 %e to i64
%r = insertelement <2 x i64> undef, i64 %z, i32 0 %r = insertelement <2 x i64> undef, i64 %z, i32 0
ret <2 x i64> %r ret <2 x i64> %r
} }
define <2 x i64> @extract0_i16_zext_insert0_i64_zero(<8 x i16> %x) { define <2 x i64> @extract0_i16_zext_insert0_i64_zero(<8 x i16> %x) {
; CHECK-LABEL: extract0_i16_zext_insert0_i64_zero: ; CHECK-LABEL: extract0_i16_zext_insert0_i64_zero:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: umov w8, v0.h[0] ; CHECK-NEXT: umov w8, v0.h[0]
; CHECK-NEXT: and x8, x8, #0xffff
; CHECK-NEXT: movi v0.2d, #0000000000000000 ; CHECK-NEXT: movi v0.2d, #0000000000000000
; CHECK-NEXT: mov v0.d[0], x8 ; CHECK-NEXT: mov v0.d[0], x8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%e = extractelement <8 x i16> %x, i32 0 %e = extractelement <8 x i16> %x, i32 0
%z = zext i16 %e to i64 %z = zext i16 %e to i64
%r = insertelement <2 x i64> zeroinitializer, i64 %z, i32 0 %r = insertelement <2 x i64> zeroinitializer, i64 %z, i32 0
ret <2 x i64> %r ret <2 x i64> %r
} }
define <2 x i64> @extract1_i16_zext_insert0_i64_undef(<8 x i16> %x) { define <2 x i64> @extract1_i16_zext_insert0_i64_undef(<8 x i16> %x) {
; CHECK-LABEL: extract1_i16_zext_insert0_i64_undef: ; CHECK-LABEL: extract1_i16_zext_insert0_i64_undef:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: umov w8, v0.h[1] ; CHECK-NEXT: umov w8, v0.h[1]
; CHECK-NEXT: and x8, x8, #0xffff
; CHECK-NEXT: fmov d0, x8 ; CHECK-NEXT: fmov d0, x8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%e = extractelement <8 x i16> %x, i32 1 %e = extractelement <8 x i16> %x, i32 1
%z = zext i16 %e to i64 %z = zext i16 %e to i64
%r = insertelement <2 x i64> undef, i64 %z, i32 0 %r = insertelement <2 x i64> undef, i64 %z, i32 0
ret <2 x i64> %r ret <2 x i64> %r
} }
define <2 x i64> @extract1_i16_zext_insert0_i64_zero(<8 x i16> %x) { define <2 x i64> @extract1_i16_zext_insert0_i64_zero(<8 x i16> %x) {
; CHECK-LABEL: extract1_i16_zext_insert0_i64_zero: ; CHECK-LABEL: extract1_i16_zext_insert0_i64_zero:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: umov w8, v0.h[1] ; CHECK-NEXT: umov w8, v0.h[1]
; CHECK-NEXT: and x8, x8, #0xffff
; CHECK-NEXT: movi v0.2d, #0000000000000000 ; CHECK-NEXT: movi v0.2d, #0000000000000000
; CHECK-NEXT: mov v0.d[0], x8 ; CHECK-NEXT: mov v0.d[0], x8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%e = extractelement <8 x i16> %x, i32 1 %e = extractelement <8 x i16> %x, i32 1
%z = zext i16 %e to i64 %z = zext i16 %e to i64
%r = insertelement <2 x i64> zeroinitializer, i64 %z, i32 0 %r = insertelement <2 x i64> zeroinitializer, i64 %z, i32 0
ret <2 x i64> %r ret <2 x i64> %r
} }
define <2 x i64> @extract2_i16_zext_insert0_i64_undef(<8 x i16> %x) { define <2 x i64> @extract2_i16_zext_insert0_i64_undef(<8 x i16> %x) {
; CHECK-LABEL: extract2_i16_zext_insert0_i64_undef: ; CHECK-LABEL: extract2_i16_zext_insert0_i64_undef:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: umov w8, v0.h[2] ; CHECK-NEXT: umov w8, v0.h[2]
; CHECK-NEXT: and x8, x8, #0xffff
; CHECK-NEXT: fmov d0, x8 ; CHECK-NEXT: fmov d0, x8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%e = extractelement <8 x i16> %x, i32 2 %e = extractelement <8 x i16> %x, i32 2
%z = zext i16 %e to i64 %z = zext i16 %e to i64
%r = insertelement <2 x i64> undef, i64 %z, i32 0 %r = insertelement <2 x i64> undef, i64 %z, i32 0
ret <2 x i64> %r ret <2 x i64> %r
} }
define <2 x i64> @extract2_i16_zext_insert0_i64_zero(<8 x i16> %x) { define <2 x i64> @extract2_i16_zext_insert0_i64_zero(<8 x i16> %x) {
; CHECK-LABEL: extract2_i16_zext_insert0_i64_zero: ; CHECK-LABEL: extract2_i16_zext_insert0_i64_zero:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: umov w8, v0.h[2] ; CHECK-NEXT: umov w8, v0.h[2]
; CHECK-NEXT: and x8, x8, #0xffff
; CHECK-NEXT: movi v0.2d, #0000000000000000 ; CHECK-NEXT: movi v0.2d, #0000000000000000
; CHECK-NEXT: mov v0.d[0], x8 ; CHECK-NEXT: mov v0.d[0], x8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%e = extractelement <8 x i16> %x, i32 2 %e = extractelement <8 x i16> %x, i32 2
%z = zext i16 %e to i64 %z = zext i16 %e to i64
%r = insertelement <2 x i64> zeroinitializer, i64 %z, i32 0 %r = insertelement <2 x i64> zeroinitializer, i64 %z, i32 0
ret <2 x i64> %r ret <2 x i64> %r
} }
define <2 x i64> @extract3_i16_zext_insert0_i64_undef(<8 x i16> %x) { define <2 x i64> @extract3_i16_zext_insert0_i64_undef(<8 x i16> %x) {
; CHECK-LABEL: extract3_i16_zext_insert0_i64_undef: ; CHECK-LABEL: extract3_i16_zext_insert0_i64_undef:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: umov w8, v0.h[3] ; CHECK-NEXT: umov w8, v0.h[3]
; CHECK-NEXT: and x8, x8, #0xffff
; CHECK-NEXT: fmov d0, x8 ; CHECK-NEXT: fmov d0, x8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%e = extractelement <8 x i16> %x, i32 3 %e = extractelement <8 x i16> %x, i32 3
%z = zext i16 %e to i64 %z = zext i16 %e to i64
%r = insertelement <2 x i64> undef, i64 %z, i32 0 %r = insertelement <2 x i64> undef, i64 %z, i32 0
ret <2 x i64> %r ret <2 x i64> %r
} }
define <2 x i64> @extract3_i16_zext_insert0_i64_zero(<8 x i16> %x) { define <2 x i64> @extract3_i16_zext_insert0_i64_zero(<8 x i16> %x) {
; CHECK-LABEL: extract3_i16_zext_insert0_i64_zero: ; CHECK-LABEL: extract3_i16_zext_insert0_i64_zero:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: umov w8, v0.h[3] ; CHECK-NEXT: umov w8, v0.h[3]
; CHECK-NEXT: and x8, x8, #0xffff
; CHECK-NEXT: movi v0.2d, #0000000000000000 ; CHECK-NEXT: movi v0.2d, #0000000000000000
; CHECK-NEXT: mov v0.d[0], x8 ; CHECK-NEXT: mov v0.d[0], x8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%e = extractelement <8 x i16> %x, i32 3 %e = extractelement <8 x i16> %x, i32 3
%z = zext i16 %e to i64 %z = zext i16 %e to i64
%r = insertelement <2 x i64> zeroinitializer, i64 %z, i32 0 %r = insertelement <2 x i64> zeroinitializer, i64 %z, i32 0
ret <2 x i64> %r ret <2 x i64> %r
} }
define <2 x i64> @extract0_i16_zext_insert1_i64_undef(<8 x i16> %x) { define <2 x i64> @extract0_i16_zext_insert1_i64_undef(<8 x i16> %x) {
; CHECK-LABEL: extract0_i16_zext_insert1_i64_undef: ; CHECK-LABEL: extract0_i16_zext_insert1_i64_undef:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: umov w8, v0.h[0] ; CHECK-NEXT: umov w8, v0.h[0]
; CHECK-NEXT: and x8, x8, #0xffff
; CHECK-NEXT: dup v0.2d, x8 ; CHECK-NEXT: dup v0.2d, x8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%e = extractelement <8 x i16> %x, i32 0 %e = extractelement <8 x i16> %x, i32 0
%z = zext i16 %e to i64 %z = zext i16 %e to i64
%r = insertelement <2 x i64> undef, i64 %z, i32 1 %r = insertelement <2 x i64> undef, i64 %z, i32 1
ret <2 x i64> %r ret <2 x i64> %r
} }
define <2 x i64> @extract0_i16_zext_insert1_i64_zero(<8 x i16> %x) { define <2 x i64> @extract0_i16_zext_insert1_i64_zero(<8 x i16> %x) {
; CHECK-LABEL: extract0_i16_zext_insert1_i64_zero: ; CHECK-LABEL: extract0_i16_zext_insert1_i64_zero:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: umov w8, v0.h[0] ; CHECK-NEXT: umov w8, v0.h[0]
; CHECK-NEXT: and x8, x8, #0xffff
; CHECK-NEXT: movi v0.2d, #0000000000000000 ; CHECK-NEXT: movi v0.2d, #0000000000000000
; CHECK-NEXT: mov v0.d[1], x8 ; CHECK-NEXT: mov v0.d[1], x8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%e = extractelement <8 x i16> %x, i32 0 %e = extractelement <8 x i16> %x, i32 0
%z = zext i16 %e to i64 %z = zext i16 %e to i64
%r = insertelement <2 x i64> zeroinitializer, i64 %z, i32 1 %r = insertelement <2 x i64> zeroinitializer, i64 %z, i32 1
ret <2 x i64> %r ret <2 x i64> %r
} }
define <2 x i64> @extract1_i16_zext_insert1_i64_undef(<8 x i16> %x) { define <2 x i64> @extract1_i16_zext_insert1_i64_undef(<8 x i16> %x) {
; CHECK-LABEL: extract1_i16_zext_insert1_i64_undef: ; CHECK-LABEL: extract1_i16_zext_insert1_i64_undef:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: umov w8, v0.h[1] ; CHECK-NEXT: umov w8, v0.h[1]
; CHECK-NEXT: and x8, x8, #0xffff
; CHECK-NEXT: dup v0.2d, x8 ; CHECK-NEXT: dup v0.2d, x8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%e = extractelement <8 x i16> %x, i32 1 %e = extractelement <8 x i16> %x, i32 1
%z = zext i16 %e to i64 %z = zext i16 %e to i64
%r = insertelement <2 x i64> undef, i64 %z, i32 1 %r = insertelement <2 x i64> undef, i64 %z, i32 1
ret <2 x i64> %r ret <2 x i64> %r
} }
define <2 x i64> @extract1_i16_zext_insert1_i64_zero(<8 x i16> %x) { define <2 x i64> @extract1_i16_zext_insert1_i64_zero(<8 x i16> %x) {
; CHECK-LABEL: extract1_i16_zext_insert1_i64_zero: ; CHECK-LABEL: extract1_i16_zext_insert1_i64_zero:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: umov w8, v0.h[1] ; CHECK-NEXT: umov w8, v0.h[1]
; CHECK-NEXT: and x8, x8, #0xffff
; CHECK-NEXT: movi v0.2d, #0000000000000000 ; CHECK-NEXT: movi v0.2d, #0000000000000000
; CHECK-NEXT: mov v0.d[1], x8 ; CHECK-NEXT: mov v0.d[1], x8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%e = extractelement <8 x i16> %x, i32 1 %e = extractelement <8 x i16> %x, i32 1
%z = zext i16 %e to i64 %z = zext i16 %e to i64
%r = insertelement <2 x i64> zeroinitializer, i64 %z, i32 1 %r = insertelement <2 x i64> zeroinitializer, i64 %z, i32 1
ret <2 x i64> %r ret <2 x i64> %r
} }
define <2 x i64> @extract2_i16_zext_insert1_i64_undef(<8 x i16> %x) { define <2 x i64> @extract2_i16_zext_insert1_i64_undef(<8 x i16> %x) {
; CHECK-LABEL: extract2_i16_zext_insert1_i64_undef: ; CHECK-LABEL: extract2_i16_zext_insert1_i64_undef:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: umov w8, v0.h[2] ; CHECK-NEXT: umov w8, v0.h[2]
; CHECK-NEXT: and x8, x8, #0xffff
; CHECK-NEXT: dup v0.2d, x8 ; CHECK-NEXT: dup v0.2d, x8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%e = extractelement <8 x i16> %x, i32 2 %e = extractelement <8 x i16> %x, i32 2
%z = zext i16 %e to i64 %z = zext i16 %e to i64
%r = insertelement <2 x i64> undef, i64 %z, i32 1 %r = insertelement <2 x i64> undef, i64 %z, i32 1
ret <2 x i64> %r ret <2 x i64> %r
} }
define <2 x i64> @extract2_i16_zext_insert1_i64_zero(<8 x i16> %x) { define <2 x i64> @extract2_i16_zext_insert1_i64_zero(<8 x i16> %x) {
; CHECK-LABEL: extract2_i16_zext_insert1_i64_zero: ; CHECK-LABEL: extract2_i16_zext_insert1_i64_zero:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: umov w8, v0.h[2] ; CHECK-NEXT: umov w8, v0.h[2]
; CHECK-NEXT: and x8, x8, #0xffff
; CHECK-NEXT: movi v0.2d, #0000000000000000 ; CHECK-NEXT: movi v0.2d, #0000000000000000
; CHECK-NEXT: mov v0.d[1], x8 ; CHECK-NEXT: mov v0.d[1], x8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%e = extractelement <8 x i16> %x, i32 2 %e = extractelement <8 x i16> %x, i32 2
%z = zext i16 %e to i64 %z = zext i16 %e to i64
%r = insertelement <2 x i64> zeroinitializer, i64 %z, i32 1 %r = insertelement <2 x i64> zeroinitializer, i64 %z, i32 1
ret <2 x i64> %r ret <2 x i64> %r
} }
define <2 x i64> @extract3_i16_zext_insert1_i64_undef(<8 x i16> %x) { define <2 x i64> @extract3_i16_zext_insert1_i64_undef(<8 x i16> %x) {
; CHECK-LABEL: extract3_i16_zext_insert1_i64_undef: ; CHECK-LABEL: extract3_i16_zext_insert1_i64_undef:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: umov w8, v0.h[3] ; CHECK-NEXT: umov w8, v0.h[3]
; CHECK-NEXT: and x8, x8, #0xffff
; CHECK-NEXT: dup v0.2d, x8 ; CHECK-NEXT: dup v0.2d, x8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%e = extractelement <8 x i16> %x, i32 3 %e = extractelement <8 x i16> %x, i32 3
%z = zext i16 %e to i64 %z = zext i16 %e to i64
%r = insertelement <2 x i64> undef, i64 %z, i32 1 %r = insertelement <2 x i64> undef, i64 %z, i32 1
ret <2 x i64> %r ret <2 x i64> %r
} }
define <2 x i64> @extract3_i16_zext_insert1_i64_zero(<8 x i16> %x) { define <2 x i64> @extract3_i16_zext_insert1_i64_zero(<8 x i16> %x) {
; CHECK-LABEL: extract3_i16_zext_insert1_i64_zero: ; CHECK-LABEL: extract3_i16_zext_insert1_i64_zero:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: umov w8, v0.h[3] ; CHECK-NEXT: umov w8, v0.h[3]
; CHECK-NEXT: and x8, x8, #0xffff
; CHECK-NEXT: movi v0.2d, #0000000000000000 ; CHECK-NEXT: movi v0.2d, #0000000000000000
; CHECK-NEXT: mov v0.d[1], x8 ; CHECK-NEXT: mov v0.d[1], x8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%e = extractelement <8 x i16> %x, i32 3 %e = extractelement <8 x i16> %x, i32 3
%z = zext i16 %e to i64 %z = zext i16 %e to i64
%r = insertelement <2 x i64> zeroinitializer, i64 %z, i32 1 %r = insertelement <2 x i64> zeroinitializer, i64 %z, i32 1
ret <2 x i64> %r ret <2 x i64> %r
} }
; i8 ; i8
define <2 x i64> @extract0_i8_zext_insert0_i64_undef(<16 x i8> %x) { define <2 x i64> @extract0_i8_zext_insert0_i64_undef(<16 x i8> %x) {
; CHECK-LABEL: extract0_i8_zext_insert0_i64_undef: ; CHECK-LABEL: extract0_i8_zext_insert0_i64_undef:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: umov w8, v0.b[0] ; CHECK-NEXT: umov w8, v0.b[0]
; CHECK-NEXT: and x8, x8, #0xff
; CHECK-NEXT: fmov d0, x8 ; CHECK-NEXT: fmov d0, x8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%e = extractelement <16 x i8> %x, i32 0 %e = extractelement <16 x i8> %x, i32 0
%z = zext i8 %e to i64 %z = zext i8 %e to i64
%r = insertelement <2 x i64> undef, i64 %z, i32 0 %r = insertelement <2 x i64> undef, i64 %z, i32 0
ret <2 x i64> %r ret <2 x i64> %r
} }
define <2 x i64> @extract0_i8_zext_insert0_i64_zero(<16 x i8> %x) { define <2 x i64> @extract0_i8_zext_insert0_i64_zero(<16 x i8> %x) {
; CHECK-LABEL: extract0_i8_zext_insert0_i64_zero: ; CHECK-LABEL: extract0_i8_zext_insert0_i64_zero:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: umov w8, v0.b[0] ; CHECK-NEXT: umov w8, v0.b[0]
; CHECK-NEXT: and x8, x8, #0xff
; CHECK-NEXT: movi v0.2d, #0000000000000000 ; CHECK-NEXT: movi v0.2d, #0000000000000000
; CHECK-NEXT: mov v0.d[0], x8 ; CHECK-NEXT: mov v0.d[0], x8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%e = extractelement <16 x i8> %x, i32 0 %e = extractelement <16 x i8> %x, i32 0
%z = zext i8 %e to i64 %z = zext i8 %e to i64
%r = insertelement <2 x i64> zeroinitializer, i64 %z, i32 0 %r = insertelement <2 x i64> zeroinitializer, i64 %z, i32 0
ret <2 x i64> %r ret <2 x i64> %r
} }
define <2 x i64> @extract1_i8_zext_insert0_i64_undef(<16 x i8> %x) { define <2 x i64> @extract1_i8_zext_insert0_i64_undef(<16 x i8> %x) {
; CHECK-LABEL: extract1_i8_zext_insert0_i64_undef: ; CHECK-LABEL: extract1_i8_zext_insert0_i64_undef:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: umov w8, v0.b[1] ; CHECK-NEXT: umov w8, v0.b[1]
; CHECK-NEXT: and x8, x8, #0xff
; CHECK-NEXT: fmov d0, x8 ; CHECK-NEXT: fmov d0, x8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%e = extractelement <16 x i8> %x, i32 1 %e = extractelement <16 x i8> %x, i32 1
%z = zext i8 %e to i64 %z = zext i8 %e to i64
%r = insertelement <2 x i64> undef, i64 %z, i32 0 %r = insertelement <2 x i64> undef, i64 %z, i32 0
ret <2 x i64> %r ret <2 x i64> %r
} }
define <2 x i64> @extract1_i8_zext_insert0_i64_zero(<16 x i8> %x) { define <2 x i64> @extract1_i8_zext_insert0_i64_zero(<16 x i8> %x) {
; CHECK-LABEL: extract1_i8_zext_insert0_i64_zero: ; CHECK-LABEL: extract1_i8_zext_insert0_i64_zero:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: umov w8, v0.b[1] ; CHECK-NEXT: umov w8, v0.b[1]
; CHECK-NEXT: and x8, x8, #0xff
; CHECK-NEXT: movi v0.2d, #0000000000000000 ; CHECK-NEXT: movi v0.2d, #0000000000000000
; CHECK-NEXT: mov v0.d[0], x8 ; CHECK-NEXT: mov v0.d[0], x8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%e = extractelement <16 x i8> %x, i32 1 %e = extractelement <16 x i8> %x, i32 1
%z = zext i8 %e to i64 %z = zext i8 %e to i64
%r = insertelement <2 x i64> zeroinitializer, i64 %z, i32 0 %r = insertelement <2 x i64> zeroinitializer, i64 %z, i32 0
ret <2 x i64> %r ret <2 x i64> %r
} }
define <2 x i64> @extract2_i8_zext_insert0_i64_undef(<16 x i8> %x) { define <2 x i64> @extract2_i8_zext_insert0_i64_undef(<16 x i8> %x) {
; CHECK-LABEL: extract2_i8_zext_insert0_i64_undef: ; CHECK-LABEL: extract2_i8_zext_insert0_i64_undef:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: umov w8, v0.b[2] ; CHECK-NEXT: umov w8, v0.b[2]
; CHECK-NEXT: and x8, x8, #0xff
; CHECK-NEXT: fmov d0, x8 ; CHECK-NEXT: fmov d0, x8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%e = extractelement <16 x i8> %x, i32 2 %e = extractelement <16 x i8> %x, i32 2
%z = zext i8 %e to i64 %z = zext i8 %e to i64
%r = insertelement <2 x i64> undef, i64 %z, i32 0 %r = insertelement <2 x i64> undef, i64 %z, i32 0
ret <2 x i64> %r ret <2 x i64> %r
} }
define <2 x i64> @extract2_i8_zext_insert0_i64_zero(<16 x i8> %x) { define <2 x i64> @extract2_i8_zext_insert0_i64_zero(<16 x i8> %x) {
; CHECK-LABEL: extract2_i8_zext_insert0_i64_zero: ; CHECK-LABEL: extract2_i8_zext_insert0_i64_zero:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: umov w8, v0.b[2] ; CHECK-NEXT: umov w8, v0.b[2]
; CHECK-NEXT: and x8, x8, #0xff
; CHECK-NEXT: movi v0.2d, #0000000000000000 ; CHECK-NEXT: movi v0.2d, #0000000000000000
; CHECK-NEXT: mov v0.d[0], x8 ; CHECK-NEXT: mov v0.d[0], x8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%e = extractelement <16 x i8> %x, i32 2 %e = extractelement <16 x i8> %x, i32 2
%z = zext i8 %e to i64 %z = zext i8 %e to i64
%r = insertelement <2 x i64> zeroinitializer, i64 %z, i32 0 %r = insertelement <2 x i64> zeroinitializer, i64 %z, i32 0
ret <2 x i64> %r ret <2 x i64> %r
} }
define <2 x i64> @extract3_i8_zext_insert0_i64_undef(<16 x i8> %x) { define <2 x i64> @extract3_i8_zext_insert0_i64_undef(<16 x i8> %x) {
; CHECK-LABEL: extract3_i8_zext_insert0_i64_undef: ; CHECK-LABEL: extract3_i8_zext_insert0_i64_undef:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: umov w8, v0.b[3] ; CHECK-NEXT: umov w8, v0.b[3]
; CHECK-NEXT: and x8, x8, #0xff
; CHECK-NEXT: fmov d0, x8 ; CHECK-NEXT: fmov d0, x8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%e = extractelement <16 x i8> %x, i32 3 %e = extractelement <16 x i8> %x, i32 3
%z = zext i8 %e to i64 %z = zext i8 %e to i64
%r = insertelement <2 x i64> undef, i64 %z, i32 0 %r = insertelement <2 x i64> undef, i64 %z, i32 0
ret <2 x i64> %r ret <2 x i64> %r
} }
define <2 x i64> @extract3_i8_zext_insert0_i64_zero(<16 x i8> %x) { define <2 x i64> @extract3_i8_zext_insert0_i64_zero(<16 x i8> %x) {
; CHECK-LABEL: extract3_i8_zext_insert0_i64_zero: ; CHECK-LABEL: extract3_i8_zext_insert0_i64_zero:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: umov w8, v0.b[3] ; CHECK-NEXT: umov w8, v0.b[3]
; CHECK-NEXT: and x8, x8, #0xff
; CHECK-NEXT: movi v0.2d, #0000000000000000 ; CHECK-NEXT: movi v0.2d, #0000000000000000
; CHECK-NEXT: mov v0.d[0], x8 ; CHECK-NEXT: mov v0.d[0], x8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%e = extractelement <16 x i8> %x, i32 3 %e = extractelement <16 x i8> %x, i32 3
%z = zext i8 %e to i64 %z = zext i8 %e to i64
%r = insertelement <2 x i64> zeroinitializer, i64 %z, i32 0 %r = insertelement <2 x i64> zeroinitializer, i64 %z, i32 0
ret <2 x i64> %r ret <2 x i64> %r
} }
define <2 x i64> @extract0_i8_zext_insert1_i64_undef(<16 x i8> %x) { define <2 x i64> @extract0_i8_zext_insert1_i64_undef(<16 x i8> %x) {
; CHECK-LABEL: extract0_i8_zext_insert1_i64_undef: ; CHECK-LABEL: extract0_i8_zext_insert1_i64_undef:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: umov w8, v0.b[0] ; CHECK-NEXT: umov w8, v0.b[0]
; CHECK-NEXT: and x8, x8, #0xff
; CHECK-NEXT: dup v0.2d, x8 ; CHECK-NEXT: dup v0.2d, x8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%e = extractelement <16 x i8> %x, i32 0 %e = extractelement <16 x i8> %x, i32 0
%z = zext i8 %e to i64 %z = zext i8 %e to i64
%r = insertelement <2 x i64> undef, i64 %z, i32 1 %r = insertelement <2 x i64> undef, i64 %z, i32 1
ret <2 x i64> %r ret <2 x i64> %r
} }
define <2 x i64> @extract0_i8_zext_insert1_i64_zero(<16 x i8> %x) { define <2 x i64> @extract0_i8_zext_insert1_i64_zero(<16 x i8> %x) {
; CHECK-LABEL: extract0_i8_zext_insert1_i64_zero: ; CHECK-LABEL: extract0_i8_zext_insert1_i64_zero:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: umov w8, v0.b[0] ; CHECK-NEXT: umov w8, v0.b[0]
; CHECK-NEXT: and x8, x8, #0xff
; CHECK-NEXT: movi v0.2d, #0000000000000000 ; CHECK-NEXT: movi v0.2d, #0000000000000000
; CHECK-NEXT: mov v0.d[1], x8 ; CHECK-NEXT: mov v0.d[1], x8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%e = extractelement <16 x i8> %x, i32 0 %e = extractelement <16 x i8> %x, i32 0
%z = zext i8 %e to i64 %z = zext i8 %e to i64
%r = insertelement <2 x i64> zeroinitializer, i64 %z, i32 1 %r = insertelement <2 x i64> zeroinitializer, i64 %z, i32 1
ret <2 x i64> %r ret <2 x i64> %r
} }
define <2 x i64> @extract1_i8_zext_insert1_i64_undef(<16 x i8> %x) { define <2 x i64> @extract1_i8_zext_insert1_i64_undef(<16 x i8> %x) {
; CHECK-LABEL: extract1_i8_zext_insert1_i64_undef: ; CHECK-LABEL: extract1_i8_zext_insert1_i64_undef:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: umov w8, v0.b[1] ; CHECK-NEXT: umov w8, v0.b[1]
; CHECK-NEXT: and x8, x8, #0xff
; CHECK-NEXT: dup v0.2d, x8 ; CHECK-NEXT: dup v0.2d, x8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%e = extractelement <16 x i8> %x, i32 1 %e = extractelement <16 x i8> %x, i32 1
%z = zext i8 %e to i64 %z = zext i8 %e to i64
%r = insertelement <2 x i64> undef, i64 %z, i32 1 %r = insertelement <2 x i64> undef, i64 %z, i32 1
ret <2 x i64> %r ret <2 x i64> %r
} }
define <2 x i64> @extract1_i8_zext_insert1_i64_zero(<16 x i8> %x) { define <2 x i64> @extract1_i8_zext_insert1_i64_zero(<16 x i8> %x) {
; CHECK-LABEL: extract1_i8_zext_insert1_i64_zero: ; CHECK-LABEL: extract1_i8_zext_insert1_i64_zero:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: umov w8, v0.b[1] ; CHECK-NEXT: umov w8, v0.b[1]
; CHECK-NEXT: and x8, x8, #0xff
; CHECK-NEXT: movi v0.2d, #0000000000000000 ; CHECK-NEXT: movi v0.2d, #0000000000000000
; CHECK-NEXT: mov v0.d[1], x8 ; CHECK-NEXT: mov v0.d[1], x8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%e = extractelement <16 x i8> %x, i32 1 %e = extractelement <16 x i8> %x, i32 1
%z = zext i8 %e to i64 %z = zext i8 %e to i64
%r = insertelement <2 x i64> zeroinitializer, i64 %z, i32 1 %r = insertelement <2 x i64> zeroinitializer, i64 %z, i32 1
ret <2 x i64> %r ret <2 x i64> %r
} }
define <2 x i64> @extract2_i8_zext_insert1_i64_undef(<16 x i8> %x) { define <2 x i64> @extract2_i8_zext_insert1_i64_undef(<16 x i8> %x) {
; CHECK-LABEL: extract2_i8_zext_insert1_i64_undef: ; CHECK-LABEL: extract2_i8_zext_insert1_i64_undef:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: umov w8, v0.b[2] ; CHECK-NEXT: umov w8, v0.b[2]
; CHECK-NEXT: and x8, x8, #0xff
; CHECK-NEXT: dup v0.2d, x8 ; CHECK-NEXT: dup v0.2d, x8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%e = extractelement <16 x i8> %x, i32 2 %e = extractelement <16 x i8> %x, i32 2
%z = zext i8 %e to i64 %z = zext i8 %e to i64
%r = insertelement <2 x i64> undef, i64 %z, i32 1 %r = insertelement <2 x i64> undef, i64 %z, i32 1
ret <2 x i64> %r ret <2 x i64> %r
} }
define <2 x i64> @extract2_i8_zext_insert1_i64_zero(<16 x i8> %x) { define <2 x i64> @extract2_i8_zext_insert1_i64_zero(<16 x i8> %x) {
; CHECK-LABEL: extract2_i8_zext_insert1_i64_zero: ; CHECK-LABEL: extract2_i8_zext_insert1_i64_zero:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: umov w8, v0.b[2] ; CHECK-NEXT: umov w8, v0.b[2]
; CHECK-NEXT: and x8, x8, #0xff
; CHECK-NEXT: movi v0.2d, #0000000000000000 ; CHECK-NEXT: movi v0.2d, #0000000000000000
; CHECK-NEXT: mov v0.d[1], x8 ; CHECK-NEXT: mov v0.d[1], x8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%e = extractelement <16 x i8> %x, i32 2 %e = extractelement <16 x i8> %x, i32 2
%z = zext i8 %e to i64 %z = zext i8 %e to i64
%r = insertelement <2 x i64> zeroinitializer, i64 %z, i32 1 %r = insertelement <2 x i64> zeroinitializer, i64 %z, i32 1
ret <2 x i64> %r ret <2 x i64> %r
} }
define <2 x i64> @extract3_i8_zext_insert1_i64_undef(<16 x i8> %x) { define <2 x i64> @extract3_i8_zext_insert1_i64_undef(<16 x i8> %x) {
; CHECK-LABEL: extract3_i8_zext_insert1_i64_undef: ; CHECK-LABEL: extract3_i8_zext_insert1_i64_undef:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: umov w8, v0.b[3] ; CHECK-NEXT: umov w8, v0.b[3]
; CHECK-NEXT: and x8, x8, #0xff
; CHECK-NEXT: dup v0.2d, x8 ; CHECK-NEXT: dup v0.2d, x8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%e = extractelement <16 x i8> %x, i32 3 %e = extractelement <16 x i8> %x, i32 3
%z = zext i8 %e to i64 %z = zext i8 %e to i64
%r = insertelement <2 x i64> undef, i64 %z, i32 1 %r = insertelement <2 x i64> undef, i64 %z, i32 1
ret <2 x i64> %r ret <2 x i64> %r
} }
define <2 x i64> @extract3_i8_zext_insert1_i64_zero(<16 x i8> %x) { define <2 x i64> @extract3_i8_zext_insert1_i64_zero(<16 x i8> %x) {
; CHECK-LABEL: extract3_i8_zext_insert1_i64_zero: ; CHECK-LABEL: extract3_i8_zext_insert1_i64_zero:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: umov w8, v0.b[3] ; CHECK-NEXT: umov w8, v0.b[3]
; CHECK-NEXT: and x8, x8, #0xff
; CHECK-NEXT: movi v0.2d, #0000000000000000 ; CHECK-NEXT: movi v0.2d, #0000000000000000
; CHECK-NEXT: mov v0.d[1], x8 ; CHECK-NEXT: mov v0.d[1], x8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%e = extractelement <16 x i8> %x, i32 3 %e = extractelement <16 x i8> %x, i32 3
%z = zext i8 %e to i64 %z = zext i8 %e to i64
%r = insertelement <2 x i64> zeroinitializer, i64 %z, i32 1 %r = insertelement <2 x i64> zeroinitializer, i64 %z, i32 1
ret <2 x i64> %r ret <2 x i64> %r
} }
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