[RISCV] Make the hasStdExtM() check in RISCVInstrInfo::getVLENFactoredAmount emit a diagnostic rather than an assert.

[craig.topper]

Summary

As far as I know we're not enforcing the StdExtM must be enabled
to use the V extension. If we use an assert here and hit this
code in a release build we'll silently emit an invalid instruction.

By using a diagnostic we report the error to the user in release
builds. I think there may still be a later fatal error from
the code emitter though.

[jrtc27]

llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

1200

MF.getFunction().getContext().diagnose(DiagnosticInfoUnsupported{
    MF.getFunction(),
    "M-extension must ..."});

perhaps, if you want a friendlier experience?

[craig.topper]

Use a diagnostic instead. I don't this stops the build immediately, but that should be fine.

[frasercrmck]

This is better than an assert, but do we absolutely require M? Couldn't we fall back to compiler-rt, for instance?

[craig.topper]

In D97970#2610621, @frasercrmck wrote:

This is better than an assert, but do we absolutely require M? Couldn't we fall back to compiler-rt, for instance?

Maybe. I'm not sure if I we're able to inject a call at the point in the compiler where this is used.

[frasercrmck]

In D97970#2611530, @craig.topper wrote:

Maybe. I'm not sure if I we're able to inject a call at the point in the compiler where this is used.

Yeah, I thought that might be case. Perhaps we'd have to lower it differently/earlier without M. Since that code would be elsewhere, this diagnostic is still an improvement so I'm happy for it to go in. We can always come back to this issue if/when it's important.

llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

 //===-- RISCVInstrInfo.cpp - RISCV Instruction Information ------*- C++ -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
if (isPowerOf2_32(NumOfVReg)) {
     BuildMI(MBB, II, DL, TII->get(RISCV::SLLI), FactorRegister)
         .addReg(SizeOfVector, RegState::Kill)
         .addImm(ShiftAmount);
   } else {
     Register VN = MRI.createVirtualRegister(&RISCV::GPRRegClass);
     BuildMI(MBB, II, DL, TII->get(RISCV::ADDI), VN)
         .addReg(RISCV::X0)
         .addImm(NumOfVReg);
-    assert(MF.getSubtarget<RISCVSubtarget>().hasStdExtM() &&
-           "M-extension must be enabled to calculate the vscaled size/offset.");
+    if (!MF.getSubtarget<RISCVSubtarget>().hasStdExtM())
+      report_fatal_error("M-extension must be enabled to calculate the vscaled "
+                         "size/offset.");
     BuildMI(MBB, II, DL, TII->get(RISCV::MUL), FactorRegister)
         .addReg(SizeOfVector, RegState::Kill)
         .addReg(VN, RegState::Kill);
   }
 
   return FactorRegister;
 }