[RISCV] Implement vsoxseg/vsuxseg intrinsics.

[HsiangKai]

Summary

Define vsoxseg/vsuxseg intrinsics and pseudo instructions. Lower vsoxseg/vsuxseg intrinsics to pseudo instructions in RISCVDAGToDAGISel.

[HsiangKai]

Add test cases for rv32. It does not contain all combinations for vsxseg due to the revision will be too large to upload.

[craig.topper]

llvm/include/llvm/IR/IntrinsicsRISCV.td

998

Make this a FIXME or TODO

llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td

2834

Make this a FIXME or TODO

[craig.topper]

LGTM

[HsiangKai]

• Update to v1.0.

[HsiangKai]

Put test cases to D95194, D95195, D95196, and D95197.

llvm/include/llvm/IR/IntrinsicsRISCV.td

class RISCVSSegStoreMask<int nf>
         : Intrinsic<[],
                     !listconcat([llvm_anyvector_ty],
                                 !listsplat(LLVMMatchType<0>, !add(nf, -1)),
                                 [LLVMPointerToElt<0>, llvm_anyint_ty,
                                  LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
                                  LLVMMatchType<1>]),
                     [NoCapture<ArgIndex<nf>>, IntrWriteMem]>, RISCVVIntrinsic;
 
+  // For indexed segment store
+  // Input: (value, pointer, offset, vl)
+  class RISCVISegStore<int nf>
+        : Intrinsic<[],
+                    !listconcat([llvm_anyvector_ty],
+                                !listsplat(LLVMMatchType<0>, !add(nf, -1)),
+                                [LLVMPointerToElt<0>, llvm_anyvector_ty,
+                                 llvm_anyint_ty]),
+                    [NoCapture<ArgIndex<nf>>, IntrWriteMem]>, RISCVVIntrinsic;
+  // For indexed segment store with mask
+  // Input: (value, pointer, offset, mask, vl)
+  class RISCVISegStoreMask<int nf>
+        : Intrinsic<[],
+                    !listconcat([llvm_anyvector_ty],
+                                !listsplat(LLVMMatchType<0>, !add(nf, -1)),
+                                [LLVMPointerToElt<0>, llvm_anyvector_ty,
+                                 LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
+                                 llvm_anyint_ty]),
+                    [NoCapture<ArgIndex<nf>>, IntrWriteMem]>, RISCVVIntrinsic;
+
   multiclass RISCVUSLoad {
     def "int_riscv_" # NAME : RISCVUSLoad;
     def "int_riscv_" # NAME # "_mask" : RISCVUSLoadMask;
   }
   multiclass RISCVSLoad {
     def "int_riscv_" # NAME : RISCVSLoad;
     def "int_riscv_" # NAME # "_mask" : RISCVSLoadMask;
   }
let TargetPrefix = "riscv" in {
   multiclass RISCVUSSegStore<int nf> {
     def "int_riscv_" # NAME : RISCVUSSegStore<nf>;
     def "int_riscv_" # NAME # "_mask" : RISCVUSSegStoreMask<nf>;
   }
   multiclass RISCVSSegStore<int nf> {
     def "int_riscv_" # NAME : RISCVSSegStore<nf>;
     def "int_riscv_" # NAME # "_mask" : RISCVSSegStoreMask<nf>;
   }
+  multiclass RISCVISegStore<int nf> {
+    def "int_riscv_" # NAME : RISCVISegStore<nf>;
+    def "int_riscv_" # NAME # "_mask" : RISCVISegStoreMask<nf>;
+  }
 
   defm vle : RISCVUSLoad;
   defm vleff : RISCVUSLoad;
   defm vse : RISCVUSStore;
   defm vlse: RISCVSLoad;
   defm vsse: RISCVSStore;
   defm vlxe: RISCVILoad;
   defm vsxe: RISCVIStore;
let TargetPrefix = "riscv" in {
 
   foreach nf = [2, 3, 4, 5, 6, 7, 8] in {
     defm vlseg # nf : RISCVUSSegLoad<nf>;
     defm vlsseg # nf : RISCVSSegLoad<nf>;
     // In v1.0, it should be vloxseg.
     defm vlxseg # nf : RISCVISegLoad<nf>;
     defm vsseg # nf : RISCVUSSegStore<nf>;
     defm vssseg # nf : RISCVSSegStore<nf>;
+    // In v1.0, it should be vsoxseg.
+    defm vsxseg # nf : RISCVISegStore<nf>;
   }
 
 } // TargetPrefix = "riscv"

llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h

public:
   bool selectVSplatUimm5(SDValue N, SDValue &SplatVal);
 
   void selectVLSEG(SDNode *Node, unsigned IntNo, bool IsStride);
   void selectVLSEGMask(SDNode *Node, unsigned IntNo, bool IsStride);
   void selectVLXSEG(SDNode *Node, unsigned IntNo);
   void selectVLXSEGMask(SDNode *Node, unsigned IntNo);
   void selectVSSEG(SDNode *Node, unsigned IntNo, bool IsStride);
   void selectVSSEGMask(SDNode *Node, unsigned IntNo, bool IsStride);
+  void selectVSXSEG(SDNode *Node, unsigned IntNo);
+  void selectVSXSEGMask(SDNode *Node, unsigned IntNo);
 
 // Include the pieces autogenerated from the target description.
 #include "RISCVGenDAGISel.inc"
 
 private:
   void doPeepholeLoadStoreADDI();
 };
 }
 
 #endif

llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

void RISCVDAGToDAGISel::selectVSSEGMask(SDNode *Node, unsigned IntNo, bool IsStride) {
   const RISCVZvlssegTable::RISCVZvlsseg *P = RISCVZvlssegTable::getPseudo(
       IntNo, ScalarSize, static_cast<unsigned>(LMUL),
       static_cast<unsigned>(RISCVVLMUL::LMUL_1));
   SDNode *Store =
       CurDAG->getMachineNode(P->Pseudo, DL, Node->getValueType(0), Operands);
   ReplaceNode(Node, Store);
 }
 
+void RISCVDAGToDAGISel::selectVSXSEG(SDNode *Node, unsigned IntNo) {
+  SDLoc DL(Node);
+  unsigned NF = Node->getNumOperands() - 5;
+  EVT VT = Node->getOperand(2)->getValueType(0);
+  unsigned ScalarSize = VT.getScalarSizeInBits();
+  MVT XLenVT = Subtarget->getXLenVT();
+  RISCVVLMUL LMUL = getLMUL(VT);
+  SDValue SEW = CurDAG->getTargetConstant(ScalarSize, DL, XLenVT);
+  SmallVector<SDValue, 8> Regs(Node->op_begin() + 2, Node->op_begin() + 2 + NF);
+  SDValue StoreVal = createTuple(*CurDAG, Regs, NF, LMUL);
+  SDValue Operands[] = {
+      StoreVal,
+      Node->getOperand(2 + NF), // Base pointer.
+      Node->getOperand(3 + NF), // Index.
+      Node->getOperand(4 + NF), // VL.
+      SEW,
+      Node->getOperand(0) // Chain.
+  };
+
+  EVT IndexVT = Node->getOperand(3 + NF)->getValueType(0);
+  RISCVVLMUL IndexLMUL = getLMUL(IndexVT);
+  unsigned IndexScalarSize = IndexVT.getScalarSizeInBits();
+  const RISCVZvlssegTable::RISCVZvlsseg *P = RISCVZvlssegTable::getPseudo(
+      IntNo, IndexScalarSize, static_cast<unsigned>(LMUL),
+      static_cast<unsigned>(IndexLMUL));
+  SDNode *Store =
+      CurDAG->getMachineNode(P->Pseudo, DL, Node->getValueType(0), Operands);
+  ReplaceNode(Node, Store);
+}
+
+void RISCVDAGToDAGISel::selectVSXSEGMask(SDNode *Node, unsigned IntNo) {
+  SDLoc DL(Node);
+  unsigned NF = Node->getNumOperands() - 6;
+  EVT VT = Node->getOperand(2)->getValueType(0);
+  unsigned ScalarSize = VT.getScalarSizeInBits();
+  MVT XLenVT = Subtarget->getXLenVT();
+  RISCVVLMUL LMUL = getLMUL(VT);
+  SDValue SEW = CurDAG->getTargetConstant(ScalarSize, DL, XLenVT);
+  SmallVector<SDValue, 8> Regs(Node->op_begin() + 2, Node->op_begin() + 2 + NF);
+  SDValue StoreVal = createTuple(*CurDAG, Regs, NF, LMUL);
+  SDValue Operands[] = {
+      StoreVal,
+      Node->getOperand(2 + NF), // Base pointer.
+      Node->getOperand(3 + NF), // Index.
+      Node->getOperand(4 + NF), // Mask.
+      Node->getOperand(5 + NF), // VL.
+      SEW,
+      Node->getOperand(0) // Chain.
+  };
+
+  EVT IndexVT = Node->getOperand(3 + NF)->getValueType(0);
+  RISCVVLMUL IndexLMUL = getLMUL(IndexVT);
+  unsigned IndexScalarSize = IndexVT.getScalarSizeInBits();
+  const RISCVZvlssegTable::RISCVZvlsseg *P = RISCVZvlssegTable::getPseudo(
+      IntNo, IndexScalarSize, static_cast<unsigned>(LMUL),
+      static_cast<unsigned>(IndexLMUL));
+  SDNode *Store =
+      CurDAG->getMachineNode(P->Pseudo, DL, Node->getValueType(0), Operands);
+  ReplaceNode(Node, Store);
+}
+
 void RISCVDAGToDAGISel::Select(SDNode *Node) {
   // If we have a custom node, we have already selected.
   if (Node->isMachineOpcode()) {
     LLVM_DEBUG(dbgs() << "== "; Node->dump(CurDAG); dbgs() << "\n");
     Node->setNodeId(-1);
     return;
   }
 
case ISD::INTRINSIC_VOID: {
     case Intrinsic::riscv_vssseg4_mask:
     case Intrinsic::riscv_vssseg5_mask:
     case Intrinsic::riscv_vssseg6_mask:
     case Intrinsic::riscv_vssseg7_mask:
     case Intrinsic::riscv_vssseg8_mask: {
       selectVSSEGMask(Node, IntNo, /*IsStride=*/true);
       return;
     }
+    case Intrinsic::riscv_vsxseg2:
+    case Intrinsic::riscv_vsxseg3:
+    case Intrinsic::riscv_vsxseg4:
+    case Intrinsic::riscv_vsxseg5:
+    case Intrinsic::riscv_vsxseg6:
+    case Intrinsic::riscv_vsxseg7:
+    case Intrinsic::riscv_vsxseg8: {
+      selectVSXSEG(Node, IntNo);
+      return;
+    }
+    case Intrinsic::riscv_vsxseg2_mask:
+    case Intrinsic::riscv_vsxseg3_mask:
+    case Intrinsic::riscv_vsxseg4_mask:
+    case Intrinsic::riscv_vsxseg5_mask:
+    case Intrinsic::riscv_vsxseg6_mask:
+    case Intrinsic::riscv_vsxseg7_mask:
+    case Intrinsic::riscv_vsxseg8_mask: {
+      selectVSXSEGMask(Node, IntNo);
+      return;
+    }
     }
     break;
   }
   }
 
   // Select the default instruction.
   SelectCode(Node);
 }

llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td

string VInst = !subst("_M8", "",
                  !subst("Pseudo", "", PseudoInst))))))))))))))));
 }
 
 class ToLowerCase<string Upper> {
   string L = !subst("VLSEG", "vlseg",
              !subst("VLSSEG", "vlsseg",
              !subst("VSSEG", "vsseg",
              !subst("VSSSEG", "vssseg",
-             !subst("VLXSEG", "vlxseg", Upper)))));
+             !subst("VLXSEG", "vlxseg",
+             !subst("VSXSEG", "vsxseg", Upper))))));
 }
 
 // Example: PseudoVLSEG2E32_V_M2 -> int_riscv_vlseg2
 // Example: PseudoVLSEG2E32_V_M2_MASK -> int_riscv_vlseg2_mask
 class PseudoToIntrinsic<string PseudoInst, bit IsMasked> {
   string Intrinsic = !strconcat("int_riscv_",
                         ToLowerCase<
                         !subst("E8", "",
class VPseudoSSegStoreMask<VReg ValClass, bits<11> EEW>:
   let hasSideEffects = 0;
   let usesCustomInserter = 1;
   let Uses = [VL, VTYPE];
   let HasVLOp = 1;
   let HasSEWOp = 1;
   let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
 }
 
+class VPseudoISegStoreNoMask<VReg ValClass, VReg IdxClass, bits<11> EEW, bits<3> LMUL>:
+      Pseudo<(outs),
+             (ins ValClass:$rd, GPR:$rs1, IdxClass: $index,
+                  GPR:$vl, ixlenimm:$sew),[]>,
+      RISCVVPseudo,
+      RISCVZvlsseg<PseudoToIntrinsic<NAME, false>.Intrinsic, EEW, VLMul, LMUL> {
+  let mayLoad = 0;
+  let mayStore = 1;
+  let hasSideEffects = 0;
+  let usesCustomInserter = 1;
+  let Uses = [VL, VTYPE];
+  let HasVLOp = 1;
+  let HasSEWOp = 1;
+  let HasDummyMask = 1;
+  let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
+}
+
+class VPseudoISegStoreMask<VReg ValClass, VReg IdxClass, bits<11> EEW, bits<3> LMUL>:
+      Pseudo<(outs),
+             (ins ValClass:$rd, GPR:$rs1, IdxClass: $index,
+                  VMaskOp:$vm, GPR:$vl, ixlenimm:$sew),[]>,
+      RISCVVPseudo,
+      RISCVZvlsseg<PseudoToIntrinsic<NAME, true>.Intrinsic, EEW, VLMul, LMUL> {
+  let mayLoad = 0;
+  let mayStore = 1;
+  let hasSideEffects = 0;
+  let usesCustomInserter = 1;
+  let Uses = [VL, VTYPE];
+  let HasVLOp = 1;
+  let HasSEWOp = 1;
+  let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
+}
+
 multiclass VPseudoUSLoad {
   foreach lmul = MxList.m in {
     defvar LInfo = lmul.MX;
     defvar vreg = lmul.vrclass;
     let VLMul = lmul.value in {
       def "_V_" # LInfo : VPseudoUSLoadNoMask<vreg>;
       def "_V_" # LInfo # "_MASK" : VPseudoUSLoadMask<vreg>;
     }
foreach lmul = MxSet<eew>.m in {
           def nf # "E" # eew # "_V_" # LInfo : VPseudoSSegStoreNoMask<vreg, eew>;
           def nf # "E" # eew # "_V_" # LInfo # "_MASK" : VPseudoSSegStoreMask<vreg, eew>;
         }
       }
     }
   }
 }
 
+multiclass VPseudoISegStore {
+  foreach idx_eew = EEWList in {  // EEW for index argument.
+    foreach idx_lmul = MxSet<idx_eew>.m in {  // LMUL for index argument.
+      foreach val_lmul = MxList.m in {  // LMUL for the value.
+        defvar IdxLInfo = idx_lmul.MX;
+        defvar IdxVreg = idx_lmul.vrclass;
+        defvar ValLInfo = val_lmul.MX;
+        let VLMul = val_lmul.value in {
+          foreach nf = NFSet<val_lmul>.L in {
+            defvar ValVreg = SegRegClass<val_lmul, nf>.RC;
+            def nf # "EI" # idx_eew # "_V_" # IdxLInfo # "_" # ValLInfo :
+              VPseudoISegStoreNoMask<ValVreg, IdxVreg, idx_eew, idx_lmul.value>;
+            def nf # "EI" # idx_eew # "_V_" # IdxLInfo # "_" # ValLInfo # "_MASK" :
+              VPseudoISegStoreMask<ValVreg, IdxVreg, idx_eew, idx_lmul.value>;
+          }
+        }
+      }
+    }
+  }
+}
+
 //===----------------------------------------------------------------------===//
 // Helpers to define the intrinsic patterns.
 //===----------------------------------------------------------------------===//
 
 class VPatUnaryNoMask<string intrinsic_name,
                       string inst,
                       string kind,
                       ValueType result_type,

 // 7.8. Vector Load/Store Segment Instructions
 //===----------------------------------------------------------------------===//
 defm PseudoVLSEG : VPseudoUSSegLoad;
 defm PseudoVLSSEG : VPseudoSSegLoad;
 // In v1.0, it should be PseudoVLOXSEG.
 defm PseudoVLXSEG : VPseudoISegLoad;
 defm PseudoVSSEG : VPseudoUSSegStore;
 defm PseudoVSSSEG : VPseudoSSegStore;
+// In v1.0, it should be PseudoVSOXSEG.
+defm PseudoVSXSEG : VPseudoISegStore;
 
 //===----------------------------------------------------------------------===//
 // Pseudo Instructions
 //===----------------------------------------------------------------------===//
 
 //===----------------------------------------------------------------------===//
 // 12. Vector Integer Arithmetic Instructions
 //===----------------------------------------------------------------------===//

llvm/test/CodeGen/RISCV/rvv/vsxseg.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv64 -mattr=+d,+experimental-zvlsseg,+experimental-zfh \
+; RUN:     -verify-machineinstrs < %s | FileCheck %s
+
+declare void @llvm.riscv.vsxseg2.nxv16i16.nxv16i16(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 16 x i16>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv16i16.nxv16i16(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 16 x i16>, <vscale x 16 x i1>, i64)
+
+define void @test_vsxseg2_nxv16i16_nxv16i16(<vscale x 16 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv16i16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv4r.v v28, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v28
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv16i16.nxv16i16(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv16i16_nxv16i16(<vscale x 16 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv16i16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv4r.v v28, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v28, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv16i16.nxv16i16(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv16i16.nxv32i16(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 32 x i16>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv16i16.nxv32i16(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 32 x i16>, <vscale x 16 x i1>, i64)
+
+define void @test_vsxseg2_nxv16i16_nxv32i16(<vscale x 16 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv16i16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv16i16.nxv32i16(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv16i16_nxv32i16(<vscale x 16 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv16i16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv16i16.nxv32i16(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv16i16.nxv4i32(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 4 x i32>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv16i16.nxv4i32(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 4 x i32>, <vscale x 16 x i1>, i64)
+
+define void @test_vsxseg2_nxv16i16_nxv4i32(<vscale x 16 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv16i16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv2r.v v26, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v26
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv16i16.nxv4i32(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv16i16_nxv4i32(<vscale x 16 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv16i16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv2r.v v26, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v26, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv16i16.nxv4i32(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv16i16.nxv16i8(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 16 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv16i16.nxv16i8(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 16 x i8>, <vscale x 16 x i1>, i64)
+
+define void @test_vsxseg2_nxv16i16_nxv16i8(<vscale x 16 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv16i16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv2r.v v26, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v26
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv16i16.nxv16i8(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv16i16_nxv16i8(<vscale x 16 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv16i16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv2r.v v26, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v26, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv16i16.nxv16i8(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv16i16.nxv1i64(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv16i16.nxv1i64(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 1 x i64>, <vscale x 16 x i1>, i64)
+
+define void @test_vsxseg2_nxv16i16_nxv1i64(<vscale x 16 x i16> %val, i16* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv16i16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv1r.v v25, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv16i16.nxv1i64(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 1 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv16i16_nxv1i64(<vscale x 16 x i16> %val, i16* %base, <vscale x 1 x i64> %index, <vscale x 16 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv16i16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv1r.v v25, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv16i16.nxv1i64(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 1 x i64> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv16i16.nxv1i32(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv16i16.nxv1i32(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 1 x i32>, <vscale x 16 x i1>, i64)
+
+define void @test_vsxseg2_nxv16i16_nxv1i32(<vscale x 16 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv16i16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv1r.v v25, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv16i16.nxv1i32(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv16i16_nxv1i32(<vscale x 16 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv16i16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv1r.v v25, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv16i16.nxv1i32(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv16i16.nxv8i16(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 8 x i16>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv16i16.nxv8i16(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 8 x i16>, <vscale x 16 x i1>, i64)
+
+define void @test_vsxseg2_nxv16i16_nxv8i16(<vscale x 16 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv16i16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv2r.v v26, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v26
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv16i16.nxv8i16(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv16i16_nxv8i16(<vscale x 16 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv16i16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv2r.v v26, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v26, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv16i16.nxv8i16(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv16i16.nxv4i8(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 4 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv16i16.nxv4i8(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 4 x i8>, <vscale x 16 x i1>, i64)
+
+define void @test_vsxseg2_nxv16i16_nxv4i8(<vscale x 16 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv16i16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv1r.v v25, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv16i16.nxv4i8(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv16i16_nxv4i8(<vscale x 16 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv16i16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv1r.v v25, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv16i16.nxv4i8(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv16i16.nxv1i16(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv16i16.nxv1i16(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 1 x i16>, <vscale x 16 x i1>, i64)
+
+define void @test_vsxseg2_nxv16i16_nxv1i16(<vscale x 16 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv16i16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv1r.v v25, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv16i16.nxv1i16(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv16i16_nxv1i16(<vscale x 16 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv16i16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv1r.v v25, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv16i16.nxv1i16(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv16i16.nxv2i32(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 2 x i32>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv16i16.nxv2i32(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 2 x i32>, <vscale x 16 x i1>, i64)
+
+define void @test_vsxseg2_nxv16i16_nxv2i32(<vscale x 16 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv16i16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv1r.v v25, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv16i16.nxv2i32(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv16i16_nxv2i32(<vscale x 16 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv16i16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv1r.v v25, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv16i16.nxv2i32(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv16i16.nxv8i8(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 8 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv16i16.nxv8i8(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 8 x i8>, <vscale x 16 x i1>, i64)
+
+define void @test_vsxseg2_nxv16i16_nxv8i8(<vscale x 16 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv16i16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv1r.v v25, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv16i16.nxv8i8(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv16i16_nxv8i8(<vscale x 16 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv16i16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv1r.v v25, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv16i16.nxv8i8(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv16i16.nxv4i64(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 4 x i64>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv16i16.nxv4i64(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 4 x i64>, <vscale x 16 x i1>, i64)
+
+define void @test_vsxseg2_nxv16i16_nxv4i64(<vscale x 16 x i16> %val, i16* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv16i16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv4r.v v28, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v28
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv16i16.nxv4i64(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 4 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv16i16_nxv4i64(<vscale x 16 x i16> %val, i16* %base, <vscale x 4 x i64> %index, <vscale x 16 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv16i16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv4r.v v28, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v28, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv16i16.nxv4i64(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 4 x i64> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv16i16.nxv64i8(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 64 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv16i16.nxv64i8(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 64 x i8>, <vscale x 16 x i1>, i64)
+
+define void @test_vsxseg2_nxv16i16_nxv64i8(<vscale x 16 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv16i16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv16i16.nxv64i8(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv16i16_nxv64i8(<vscale x 16 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv16i16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv16i16.nxv64i8(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv16i16.nxv4i16(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 4 x i16>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv16i16.nxv4i16(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 4 x i16>, <vscale x 16 x i1>, i64)
+
+define void @test_vsxseg2_nxv16i16_nxv4i16(<vscale x 16 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv16i16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv1r.v v25, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv16i16.nxv4i16(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv16i16_nxv4i16(<vscale x 16 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv16i16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv1r.v v25, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv16i16.nxv4i16(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv16i16.nxv8i64(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 8 x i64>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv16i16.nxv8i64(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 8 x i64>, <vscale x 16 x i1>, i64)
+
+define void @test_vsxseg2_nxv16i16_nxv8i64(<vscale x 16 x i16> %val, i16* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv16i16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv16i16.nxv8i64(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 8 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv16i16_nxv8i64(<vscale x 16 x i16> %val, i16* %base, <vscale x 8 x i64> %index, <vscale x 16 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv16i16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv16i16.nxv8i64(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 8 x i64> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv16i16.nxv1i8(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv16i16.nxv1i8(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 1 x i8>, <vscale x 16 x i1>, i64)
+
+define void @test_vsxseg2_nxv16i16_nxv1i8(<vscale x 16 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv16i16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv1r.v v25, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv16i16.nxv1i8(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv16i16_nxv1i8(<vscale x 16 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv16i16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv1r.v v25, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv16i16.nxv1i8(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv16i16.nxv2i8(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 2 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv16i16.nxv2i8(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 2 x i8>, <vscale x 16 x i1>, i64)
+
+define void @test_vsxseg2_nxv16i16_nxv2i8(<vscale x 16 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv16i16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv1r.v v25, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv16i16.nxv2i8(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv16i16_nxv2i8(<vscale x 16 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv16i16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv1r.v v25, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv16i16.nxv2i8(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv16i16.nxv8i32(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 8 x i32>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv16i16.nxv8i32(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 8 x i32>, <vscale x 16 x i1>, i64)
+
+define void @test_vsxseg2_nxv16i16_nxv8i32(<vscale x 16 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv16i16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv4r.v v28, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v28
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv16i16.nxv8i32(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv16i16_nxv8i32(<vscale x 16 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv16i16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv4r.v v28, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v28, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv16i16.nxv8i32(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv16i16.nxv32i8(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 32 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv16i16.nxv32i8(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 32 x i8>, <vscale x 16 x i1>, i64)
+
+define void @test_vsxseg2_nxv16i16_nxv32i8(<vscale x 16 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv16i16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv4r.v v28, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v28
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv16i16.nxv32i8(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv16i16_nxv32i8(<vscale x 16 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv16i16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv4r.v v28, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v28, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv16i16.nxv32i8(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv16i16.nxv16i32(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 16 x i32>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv16i16.nxv16i32(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 16 x i32>, <vscale x 16 x i1>, i64)
+
+define void @test_vsxseg2_nxv16i16_nxv16i32(<vscale x 16 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv16i16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv16i16.nxv16i32(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv16i16_nxv16i32(<vscale x 16 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv16i16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv16i16.nxv16i32(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv16i16.nxv2i16(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 2 x i16>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv16i16.nxv2i16(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 2 x i16>, <vscale x 16 x i1>, i64)
+
+define void @test_vsxseg2_nxv16i16_nxv2i16(<vscale x 16 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv16i16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv1r.v v25, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv16i16.nxv2i16(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv16i16_nxv2i16(<vscale x 16 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv16i16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv1r.v v25, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv16i16.nxv2i16(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv16i16.nxv2i64(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 2 x i64>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv16i16.nxv2i64(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 2 x i64>, <vscale x 16 x i1>, i64)
+
+define void @test_vsxseg2_nxv16i16_nxv2i64(<vscale x 16 x i16> %val, i16* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv16i16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv2r.v v26, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v26
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv16i16.nxv2i64(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 2 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv16i16_nxv2i64(<vscale x 16 x i16> %val, i16* %base, <vscale x 2 x i64> %index, <vscale x 16 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv16i16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv2r.v v26, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v26, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv16i16.nxv2i64(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 2 x i64> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv4i32.nxv16i16(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 16 x i16>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv4i32.nxv16i16(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 16 x i16>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg2_nxv4i32_nxv16i16(<vscale x 4 x i32> %val, i32* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv4i32_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv4i32.nxv16i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 16 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv4i32_nxv16i16(<vscale x 4 x i32> %val, i32* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv4i32_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv4i32.nxv16i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv4i32.nxv32i16(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 32 x i16>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv4i32.nxv32i16(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 32 x i16>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg2_nxv4i32_nxv32i16(<vscale x 4 x i32> %val, i32* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv4i32_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv4i32.nxv32i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 32 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv4i32_nxv32i16(<vscale x 4 x i32> %val, i32* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv4i32_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv4i32.nxv32i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv4i32.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i32>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv4i32.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i32>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg2_nxv4i32_nxv4i32(<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv4i32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv2r.v v26, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v26
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv4i32.nxv4i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv4i32_nxv4i32(<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv4i32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv2r.v v26, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v26, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv4i32.nxv4i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv4i32.nxv16i8(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 16 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv4i32.nxv16i8(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 16 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg2_nxv4i32_nxv16i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv4i32_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv2r.v v26, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v26
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv4i32.nxv16i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 16 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv4i32_nxv16i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv4i32_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv2r.v v26, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v26, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv4i32.nxv16i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv4i32.nxv1i64(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv4i32.nxv1i64(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 1 x i64>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg2_nxv4i32_nxv1i64(<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv4i32_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv1r.v v25, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv4i32.nxv1i64(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv4i32_nxv1i64(<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv4i32_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv1r.v v25, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv4i32.nxv1i64(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv4i32.nxv1i32(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv4i32.nxv1i32(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 1 x i32>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg2_nxv4i32_nxv1i32(<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv4i32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv1r.v v25, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv4i32.nxv1i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv4i32_nxv1i32(<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv4i32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv1r.v v25, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv4i32.nxv1i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv4i32.nxv8i16(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 8 x i16>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv4i32.nxv8i16(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 8 x i16>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg2_nxv4i32_nxv8i16(<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv4i32_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv2r.v v26, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v26
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv4i32.nxv8i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv4i32_nxv8i16(<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv4i32_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv2r.v v26, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v26, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv4i32.nxv8i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv4i32.nxv4i8(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv4i32.nxv4i8(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg2_nxv4i32_nxv4i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv4i32_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv1r.v v25, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv4i32.nxv4i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv4i32_nxv4i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv4i32_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv1r.v v25, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv4i32.nxv4i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv4i32.nxv1i16(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv4i32.nxv1i16(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 1 x i16>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg2_nxv4i32_nxv1i16(<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv4i32_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv1r.v v25, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv4i32.nxv1i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv4i32_nxv1i16(<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv4i32_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv1r.v v25, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv4i32.nxv1i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv4i32.nxv2i32(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 2 x i32>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv4i32.nxv2i32(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 2 x i32>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg2_nxv4i32_nxv2i32(<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv4i32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv1r.v v25, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv4i32.nxv2i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv4i32_nxv2i32(<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv4i32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv1r.v v25, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv4i32.nxv2i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv4i32.nxv8i8(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 8 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv4i32.nxv8i8(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 8 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg2_nxv4i32_nxv8i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv4i32_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv1r.v v25, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv4i32.nxv8i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv4i32_nxv8i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv4i32_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv1r.v v25, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv4i32.nxv8i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv4i32.nxv4i64(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i64>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv4i32.nxv4i64(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i64>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg2_nxv4i32_nxv4i64(<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv4i32_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv4i32.nxv4i64(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv4i32_nxv4i64(<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv4i32_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv4i32.nxv4i64(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv4i32.nxv64i8(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 64 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv4i32.nxv64i8(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 64 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg2_nxv4i32_nxv64i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv4i32_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv4i32.nxv64i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 64 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv4i32_nxv64i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv4i32_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv4i32.nxv64i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv4i32.nxv4i16(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i16>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv4i32.nxv4i16(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i16>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg2_nxv4i32_nxv4i16(<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv4i32_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv1r.v v25, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv4i32.nxv4i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv4i32_nxv4i16(<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv4i32_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv1r.v v25, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv4i32.nxv4i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv4i32.nxv8i64(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 8 x i64>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv4i32.nxv8i64(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 8 x i64>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg2_nxv4i32_nxv8i64(<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv4i32_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv4i32.nxv8i64(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv4i32_nxv8i64(<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv4i32_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv4i32.nxv8i64(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv4i32.nxv1i8(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv4i32.nxv1i8(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 1 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg2_nxv4i32_nxv1i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv4i32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv1r.v v25, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv4i32.nxv1i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv4i32_nxv1i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv4i32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv1r.v v25, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv4i32.nxv1i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv4i32.nxv2i8(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 2 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv4i32.nxv2i8(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 2 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg2_nxv4i32_nxv2i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv4i32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv1r.v v25, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv4i32.nxv2i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv4i32_nxv2i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv4i32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv1r.v v25, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv4i32.nxv2i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv4i32.nxv8i32(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 8 x i32>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv4i32.nxv8i32(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 8 x i32>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg2_nxv4i32_nxv8i32(<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv4i32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv4i32.nxv8i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv4i32_nxv8i32(<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv4i32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv4i32.nxv8i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv4i32.nxv32i8(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 32 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv4i32.nxv32i8(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 32 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg2_nxv4i32_nxv32i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv4i32_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv4i32.nxv32i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 32 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv4i32_nxv32i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv4i32_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv4i32.nxv32i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv4i32.nxv16i32(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 16 x i32>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv4i32.nxv16i32(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 16 x i32>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg2_nxv4i32_nxv16i32(<vscale x 4 x i32> %val, i32* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv4i32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv4i32.nxv16i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 16 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv4i32_nxv16i32(<vscale x 4 x i32> %val, i32* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv4i32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv4i32.nxv16i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv4i32.nxv2i16(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 2 x i16>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv4i32.nxv2i16(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 2 x i16>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg2_nxv4i32_nxv2i16(<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv4i32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv1r.v v25, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv4i32.nxv2i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv4i32_nxv2i16(<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv4i32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv1r.v v25, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv4i32.nxv2i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv4i32.nxv2i64(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 2 x i64>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv4i32.nxv2i64(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 2 x i64>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg2_nxv4i32_nxv2i64(<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv4i32_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv2r.v v26, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v26
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv4i32.nxv2i64(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv4i32_nxv2i64(<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv4i32_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv2r.v v26, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v26, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv4i32.nxv2i64(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv4i32.nxv16i16(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 16 x i16>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv4i32.nxv16i16(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 16 x i16>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg3_nxv4i32_nxv16i16(<vscale x 4 x i32> %val, i32* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv4i32_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv4i32.nxv16i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 16 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv4i32_nxv16i16(<vscale x 4 x i32> %val, i32* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv4i32_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v2, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv4i32.nxv16i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv4i32.nxv32i16(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 32 x i16>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv4i32.nxv32i16(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 32 x i16>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg3_nxv4i32_nxv32i16(<vscale x 4 x i32> %val, i32* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv4i32_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vmv2r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv4i32.nxv32i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 32 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv4i32_nxv32i16(<vscale x 4 x i32> %val, i32* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv4i32_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vmv2r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv4i32.nxv32i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv4i32.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i32>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv4i32.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i32>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg3_nxv4i32_nxv4i32(<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv4i32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv4i32.nxv4i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv4i32_nxv4i32(<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv4i32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv4i32.nxv4i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv4i32.nxv16i8(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 16 x i8>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv4i32.nxv16i8(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 16 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg3_nxv4i32_nxv16i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv4i32_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv4i32.nxv16i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 16 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv4i32_nxv16i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv4i32_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv4i32.nxv16i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv4i32.nxv1i64(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv4i32.nxv1i64(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 1 x i64>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg3_nxv4i32_nxv1i64(<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv4i32_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei64.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv4i32.nxv1i64(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv4i32_nxv1i64(<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv4i32_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei64.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv4i32.nxv1i64(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv4i32.nxv1i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv4i32.nxv1i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 1 x i32>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg3_nxv4i32_nxv1i32(<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv4i32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv4i32.nxv1i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv4i32_nxv1i32(<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv4i32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv4i32.nxv1i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv4i32.nxv8i16(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 8 x i16>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv4i32.nxv8i16(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 8 x i16>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg3_nxv4i32_nxv8i16(<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv4i32_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv4i32.nxv8i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv4i32_nxv8i16(<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv4i32_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv4i32.nxv8i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv4i32.nxv4i8(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i8>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv4i32.nxv4i8(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg3_nxv4i32_nxv4i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv4i32_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv4i32.nxv4i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv4i32_nxv4i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv4i32_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv4i32.nxv4i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv4i32.nxv1i16(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv4i32.nxv1i16(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 1 x i16>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg3_nxv4i32_nxv1i16(<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv4i32_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv4i32.nxv1i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv4i32_nxv1i16(<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv4i32_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv4i32.nxv1i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv4i32.nxv2i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 2 x i32>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv4i32.nxv2i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 2 x i32>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg3_nxv4i32_nxv2i32(<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv4i32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv4i32.nxv2i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv4i32_nxv2i32(<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv4i32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv4i32.nxv2i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv4i32.nxv8i8(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 8 x i8>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv4i32.nxv8i8(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 8 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg3_nxv4i32_nxv8i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv4i32_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv4i32.nxv8i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv4i32_nxv8i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv4i32_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv4i32.nxv8i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv4i32.nxv4i64(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i64>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv4i32.nxv4i64(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i64>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg3_nxv4i32_nxv4i64(<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv4i32_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei64.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv4i32.nxv4i64(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv4i32_nxv4i64(<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv4i32_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei64.v v2, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv4i32.nxv4i64(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv4i32.nxv64i8(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 64 x i8>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv4i32.nxv64i8(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 64 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg3_nxv4i32_nxv64i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv4i32_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vmv2r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv4i32.nxv64i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 64 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv4i32_nxv64i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv4i32_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vmv2r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv4i32.nxv64i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv4i32.nxv4i16(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i16>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv4i32.nxv4i16(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i16>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg3_nxv4i32_nxv4i16(<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv4i32_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv4i32.nxv4i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv4i32_nxv4i16(<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv4i32_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv4i32.nxv4i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv4i32.nxv8i64(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 8 x i64>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv4i32.nxv8i64(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 8 x i64>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg3_nxv4i32_nxv8i64(<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv4i32_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vmv2r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei64.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv4i32.nxv8i64(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv4i32_nxv8i64(<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv4i32_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vmv2r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei64.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv4i32.nxv8i64(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv4i32.nxv1i8(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv4i32.nxv1i8(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 1 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg3_nxv4i32_nxv1i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv4i32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv4i32.nxv1i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv4i32_nxv1i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv4i32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv4i32.nxv1i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv4i32.nxv2i8(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 2 x i8>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv4i32.nxv2i8(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 2 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg3_nxv4i32_nxv2i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv4i32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv4i32.nxv2i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv4i32_nxv2i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv4i32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv4i32.nxv2i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv4i32.nxv8i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 8 x i32>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv4i32.nxv8i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 8 x i32>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg3_nxv4i32_nxv8i32(<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv4i32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv4i32.nxv8i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv4i32_nxv8i32(<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv4i32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v2, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv4i32.nxv8i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv4i32.nxv32i8(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 32 x i8>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv4i32.nxv32i8(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 32 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg3_nxv4i32_nxv32i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv4i32_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv4i32.nxv32i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 32 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv4i32_nxv32i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv4i32_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v2, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv4i32.nxv32i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv4i32.nxv16i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 16 x i32>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv4i32.nxv16i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 16 x i32>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg3_nxv4i32_nxv16i32(<vscale x 4 x i32> %val, i32* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv4i32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vmv2r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv4i32.nxv16i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 16 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv4i32_nxv16i32(<vscale x 4 x i32> %val, i32* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv4i32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vmv2r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv4i32.nxv16i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv4i32.nxv2i16(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 2 x i16>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv4i32.nxv2i16(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 2 x i16>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg3_nxv4i32_nxv2i16(<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv4i32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv4i32.nxv2i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv4i32_nxv2i16(<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv4i32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv4i32.nxv2i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv4i32.nxv2i64(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 2 x i64>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv4i32.nxv2i64(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 2 x i64>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg3_nxv4i32_nxv2i64(<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv4i32_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei64.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv4i32.nxv2i64(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv4i32_nxv2i64(<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv4i32_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei64.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv4i32.nxv2i64(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv4i32.nxv16i16(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 16 x i16>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv4i32.nxv16i16(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 16 x i16>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg4_nxv4i32_nxv16i16(<vscale x 4 x i32> %val, i32* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv4i32_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vmv2r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv4i32.nxv16i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 16 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv4i32_nxv16i16(<vscale x 4 x i32> %val, i32* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv4i32_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v2, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv4i32.nxv16i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv4i32.nxv32i16(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 32 x i16>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv4i32.nxv32i16(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 32 x i16>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg4_nxv4i32_nxv32i16(<vscale x 4 x i32> %val, i32* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv4i32_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2_v22m2
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vmv2r.v v20, v16
+; CHECK-NEXT:    vmv2r.v v22, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv4i32.nxv32i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 32 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv4i32_nxv32i16(<vscale x 4 x i32> %val, i32* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv4i32_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2_v22m2
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vmv2r.v v20, v16
+; CHECK-NEXT:    vmv2r.v v22, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv4i32.nxv32i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv4i32.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i32>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv4i32.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i32>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg4_nxv4i32_nxv4i32(<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv4i32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vmv2r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv4i32.nxv4i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv4i32_nxv4i32(<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv4i32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv4i32.nxv4i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv4i32.nxv16i8(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 16 x i8>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv4i32.nxv16i8(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 16 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg4_nxv4i32_nxv16i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv4i32_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vmv2r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv4i32.nxv16i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 16 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv4i32_nxv16i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv4i32_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv4i32.nxv16i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv4i32.nxv1i64(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv4i32.nxv1i64(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 1 x i64>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg4_nxv4i32_nxv1i64(<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv4i32_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vmv2r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei64.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv4i32.nxv1i64(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv4i32_nxv1i64(<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv4i32_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei64.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv4i32.nxv1i64(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv4i32.nxv1i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv4i32.nxv1i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 1 x i32>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg4_nxv4i32_nxv1i32(<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv4i32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vmv2r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv4i32.nxv1i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv4i32_nxv1i32(<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv4i32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv4i32.nxv1i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv4i32.nxv8i16(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 8 x i16>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv4i32.nxv8i16(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 8 x i16>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg4_nxv4i32_nxv8i16(<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv4i32_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vmv2r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv4i32.nxv8i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv4i32_nxv8i16(<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv4i32_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv4i32.nxv8i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv4i32.nxv4i8(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i8>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv4i32.nxv4i8(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg4_nxv4i32_nxv4i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv4i32_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vmv2r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv4i32.nxv4i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv4i32_nxv4i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv4i32_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv4i32.nxv4i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv4i32.nxv1i16(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv4i32.nxv1i16(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 1 x i16>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg4_nxv4i32_nxv1i16(<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv4i32_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vmv2r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv4i32.nxv1i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv4i32_nxv1i16(<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv4i32_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv4i32.nxv1i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv4i32.nxv2i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 2 x i32>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv4i32.nxv2i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 2 x i32>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg4_nxv4i32_nxv2i32(<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv4i32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vmv2r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv4i32.nxv2i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv4i32_nxv2i32(<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv4i32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv4i32.nxv2i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv4i32.nxv8i8(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 8 x i8>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv4i32.nxv8i8(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 8 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg4_nxv4i32_nxv8i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv4i32_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vmv2r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv4i32.nxv8i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv4i32_nxv8i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv4i32_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv4i32.nxv8i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv4i32.nxv4i64(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i64>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv4i32.nxv4i64(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i64>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg4_nxv4i32_nxv4i64(<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv4i32_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vmv2r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei64.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv4i32.nxv4i64(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv4i32_nxv4i64(<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv4i32_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei64.v v2, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv4i32.nxv4i64(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv4i32.nxv64i8(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 64 x i8>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv4i32.nxv64i8(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 64 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg4_nxv4i32_nxv64i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv4i32_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2_v22m2
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vmv2r.v v20, v16
+; CHECK-NEXT:    vmv2r.v v22, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv4i32.nxv64i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 64 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv4i32_nxv64i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv4i32_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2_v22m2
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vmv2r.v v20, v16
+; CHECK-NEXT:    vmv2r.v v22, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv4i32.nxv64i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv4i32.nxv4i16(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i16>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv4i32.nxv4i16(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i16>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg4_nxv4i32_nxv4i16(<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv4i32_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vmv2r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv4i32.nxv4i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv4i32_nxv4i16(<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv4i32_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv4i32.nxv4i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv4i32.nxv8i64(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 8 x i64>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv4i32.nxv8i64(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 8 x i64>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg4_nxv4i32_nxv8i64(<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv4i32_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2_v22m2
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vmv2r.v v20, v16
+; CHECK-NEXT:    vmv2r.v v22, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei64.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv4i32.nxv8i64(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv4i32_nxv8i64(<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv4i32_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2_v22m2
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vmv2r.v v20, v16
+; CHECK-NEXT:    vmv2r.v v22, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei64.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv4i32.nxv8i64(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv4i32.nxv1i8(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv4i32.nxv1i8(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 1 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg4_nxv4i32_nxv1i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv4i32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vmv2r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv4i32.nxv1i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv4i32_nxv1i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv4i32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv4i32.nxv1i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv4i32.nxv2i8(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 2 x i8>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv4i32.nxv2i8(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 2 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg4_nxv4i32_nxv2i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv4i32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vmv2r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv4i32.nxv2i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv4i32_nxv2i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv4i32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv4i32.nxv2i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv4i32.nxv8i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 8 x i32>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv4i32.nxv8i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 8 x i32>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg4_nxv4i32_nxv8i32(<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv4i32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vmv2r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv4i32.nxv8i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv4i32_nxv8i32(<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv4i32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v2, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv4i32.nxv8i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv4i32.nxv32i8(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 32 x i8>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv4i32.nxv32i8(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 32 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg4_nxv4i32_nxv32i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv4i32_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vmv2r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv4i32.nxv32i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 32 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv4i32_nxv32i8(<vscale x 4 x i32> %val, i32* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv4i32_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v2, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv4i32.nxv32i8(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv4i32.nxv16i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 16 x i32>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv4i32.nxv16i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 16 x i32>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg4_nxv4i32_nxv16i32(<vscale x 4 x i32> %val, i32* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv4i32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2_v22m2
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vmv2r.v v20, v16
+; CHECK-NEXT:    vmv2r.v v22, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv4i32.nxv16i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 16 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv4i32_nxv16i32(<vscale x 4 x i32> %val, i32* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv4i32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2_v22m2
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vmv2r.v v20, v16
+; CHECK-NEXT:    vmv2r.v v22, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv4i32.nxv16i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv4i32.nxv2i16(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 2 x i16>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv4i32.nxv2i16(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 2 x i16>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg4_nxv4i32_nxv2i16(<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv4i32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vmv2r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv4i32.nxv2i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv4i32_nxv2i16(<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv4i32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv4i32.nxv2i16(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv4i32.nxv2i64(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 2 x i64>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv4i32.nxv2i64(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 2 x i64>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg4_nxv4i32_nxv2i64(<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv4i32_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vmv2r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei64.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv4i32.nxv2i64(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv4i32_nxv2i64(<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv4i32_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei64.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv4i32.nxv2i64(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 2 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv16i8.nxv16i16(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i16>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv16i8.nxv16i16(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i16>, <vscale x 16 x i1>, i64)
+
+define void @test_vsxseg2_nxv16i8_nxv16i16(<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv16i8_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv16i8.nxv16i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv16i8_nxv16i16(<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv16i8_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv16i8.nxv16i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv16i8.nxv32i16(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 32 x i16>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv16i8.nxv32i16(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 32 x i16>, <vscale x 16 x i1>, i64)
+
+define void @test_vsxseg2_nxv16i8_nxv32i16(<vscale x 16 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv16i8_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv16i8.nxv32i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv16i8_nxv32i16(<vscale x 16 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv16i8_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv16i8.nxv32i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv16i8.nxv4i32(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 4 x i32>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv16i8.nxv4i32(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 4 x i32>, <vscale x 16 x i1>, i64)
+
+define void @test_vsxseg2_nxv16i8_nxv4i32(<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv16i8_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv2r.v v26, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v26
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv16i8.nxv4i32(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv16i8_nxv4i32(<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv16i8_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv2r.v v26, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v26, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv16i8.nxv4i32(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv16i8.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv16i8.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i8>, <vscale x 16 x i1>, i64)
+
+define void @test_vsxseg2_nxv16i8_nxv16i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv16i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv2r.v v26, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v26
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv16i8.nxv16i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv16i8_nxv16i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv16i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv2r.v v26, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v26, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv16i8.nxv16i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv16i8.nxv1i64(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv16i8.nxv1i64(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 1 x i64>, <vscale x 16 x i1>, i64)
+
+define void @test_vsxseg2_nxv16i8_nxv1i64(<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv16i8_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv1r.v v25, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv16i8.nxv1i64(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv16i8_nxv1i64(<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i64> %index, <vscale x 16 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv16i8_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv1r.v v25, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv16i8.nxv1i64(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i64> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv16i8.nxv1i32(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv16i8.nxv1i32(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 1 x i32>, <vscale x 16 x i1>, i64)
+
+define void @test_vsxseg2_nxv16i8_nxv1i32(<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv16i8_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv1r.v v25, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv16i8.nxv1i32(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv16i8_nxv1i32(<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv16i8_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv1r.v v25, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv16i8.nxv1i32(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv16i8.nxv8i16(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 8 x i16>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv16i8.nxv8i16(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 8 x i16>, <vscale x 16 x i1>, i64)
+
+define void @test_vsxseg2_nxv16i8_nxv8i16(<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv16i8_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv2r.v v26, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v26
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv16i8.nxv8i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv16i8_nxv8i16(<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv16i8_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv2r.v v26, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v26, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv16i8.nxv8i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv16i8.nxv4i8(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 4 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv16i8.nxv4i8(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 4 x i8>, <vscale x 16 x i1>, i64)
+
+define void @test_vsxseg2_nxv16i8_nxv4i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv16i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv1r.v v25, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv16i8.nxv4i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv16i8_nxv4i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv16i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv1r.v v25, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv16i8.nxv4i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv16i8.nxv1i16(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv16i8.nxv1i16(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 1 x i16>, <vscale x 16 x i1>, i64)
+
+define void @test_vsxseg2_nxv16i8_nxv1i16(<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv16i8_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv1r.v v25, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv16i8.nxv1i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv16i8_nxv1i16(<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv16i8_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv1r.v v25, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv16i8.nxv1i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv16i8.nxv2i32(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 2 x i32>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv16i8.nxv2i32(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 2 x i32>, <vscale x 16 x i1>, i64)
+
+define void @test_vsxseg2_nxv16i8_nxv2i32(<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv16i8_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv1r.v v25, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv16i8.nxv2i32(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv16i8_nxv2i32(<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv16i8_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv1r.v v25, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv16i8.nxv2i32(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv16i8.nxv8i8(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 8 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv16i8.nxv8i8(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 8 x i8>, <vscale x 16 x i1>, i64)
+
+define void @test_vsxseg2_nxv16i8_nxv8i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv16i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv1r.v v25, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv16i8.nxv8i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv16i8_nxv8i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv16i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv1r.v v25, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv16i8.nxv8i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv16i8.nxv4i64(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 4 x i64>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv16i8.nxv4i64(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 4 x i64>, <vscale x 16 x i1>, i64)
+
+define void @test_vsxseg2_nxv16i8_nxv4i64(<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv16i8_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv16i8.nxv4i64(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv16i8_nxv4i64(<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i64> %index, <vscale x 16 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv16i8_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv16i8.nxv4i64(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i64> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv16i8.nxv64i8(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 64 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv16i8.nxv64i8(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 64 x i8>, <vscale x 16 x i1>, i64)
+
+define void @test_vsxseg2_nxv16i8_nxv64i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv16i8_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv16i8.nxv64i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv16i8_nxv64i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv16i8_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv16i8.nxv64i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv16i8.nxv4i16(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 4 x i16>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv16i8.nxv4i16(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 4 x i16>, <vscale x 16 x i1>, i64)
+
+define void @test_vsxseg2_nxv16i8_nxv4i16(<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv16i8_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv1r.v v25, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv16i8.nxv4i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv16i8_nxv4i16(<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv16i8_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv1r.v v25, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv16i8.nxv4i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv16i8.nxv8i64(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 8 x i64>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv16i8.nxv8i64(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 8 x i64>, <vscale x 16 x i1>, i64)
+
+define void @test_vsxseg2_nxv16i8_nxv8i64(<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv16i8_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv16i8.nxv8i64(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv16i8_nxv8i64(<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i64> %index, <vscale x 16 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv16i8_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv16i8.nxv8i64(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i64> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv16i8.nxv1i8(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv16i8.nxv1i8(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 1 x i8>, <vscale x 16 x i1>, i64)
+
+define void @test_vsxseg2_nxv16i8_nxv1i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv16i8_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv1r.v v25, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv16i8.nxv1i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv16i8_nxv1i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv16i8_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv1r.v v25, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv16i8.nxv1i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv16i8.nxv2i8(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 2 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv16i8.nxv2i8(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 2 x i8>, <vscale x 16 x i1>, i64)
+
+define void @test_vsxseg2_nxv16i8_nxv2i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv16i8_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv1r.v v25, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv16i8.nxv2i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv16i8_nxv2i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv16i8_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv1r.v v25, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv16i8.nxv2i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv16i8.nxv8i32(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 8 x i32>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv16i8.nxv8i32(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 8 x i32>, <vscale x 16 x i1>, i64)
+
+define void @test_vsxseg2_nxv16i8_nxv8i32(<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv16i8_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv16i8.nxv8i32(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv16i8_nxv8i32(<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv16i8_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv16i8.nxv8i32(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv16i8.nxv32i8(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 32 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv16i8.nxv32i8(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 32 x i8>, <vscale x 16 x i1>, i64)
+
+define void @test_vsxseg2_nxv16i8_nxv32i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv16i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv16i8.nxv32i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv16i8_nxv32i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv16i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv16i8.nxv32i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv16i8.nxv16i32(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i32>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv16i8.nxv16i32(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i32>, <vscale x 16 x i1>, i64)
+
+define void @test_vsxseg2_nxv16i8_nxv16i32(<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv16i8_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv16i8.nxv16i32(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv16i8_nxv16i32(<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv16i8_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv16i8.nxv16i32(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv16i8.nxv2i16(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 2 x i16>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv16i8.nxv2i16(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 2 x i16>, <vscale x 16 x i1>, i64)
+
+define void @test_vsxseg2_nxv16i8_nxv2i16(<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv16i8_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv1r.v v25, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv16i8.nxv2i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv16i8_nxv2i16(<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv16i8_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv1r.v v25, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv16i8.nxv2i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv16i8.nxv2i64(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 2 x i64>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv16i8.nxv2i64(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 2 x i64>, <vscale x 16 x i1>, i64)
+
+define void @test_vsxseg2_nxv16i8_nxv2i64(<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv16i8_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv2r.v v26, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v26
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv16i8.nxv2i64(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv16i8_nxv2i64(<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i64> %index, <vscale x 16 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv16i8_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv2r.v v26, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v26, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv16i8.nxv2i64(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i64> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv16i8.nxv16i16(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i16>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv16i8.nxv16i16(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i16>, <vscale x 16 x i1>, i64)
+
+define void @test_vsxseg3_nxv16i8_nxv16i16(<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv16i8_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv16i8.nxv16i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv16i8_nxv16i16(<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv16i8_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v2, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv16i8.nxv16i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv16i8.nxv32i16(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 32 x i16>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv16i8.nxv32i16(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 32 x i16>, <vscale x 16 x i1>, i64)
+
+define void @test_vsxseg3_nxv16i8_nxv32i16(<vscale x 16 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv16i8_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vmv2r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv16i8.nxv32i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv16i8_nxv32i16(<vscale x 16 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv16i8_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vmv2r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv16i8.nxv32i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv16i8.nxv4i32(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 4 x i32>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv16i8.nxv4i32(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 4 x i32>, <vscale x 16 x i1>, i64)
+
+define void @test_vsxseg3_nxv16i8_nxv4i32(<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv16i8_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv16i8.nxv4i32(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv16i8_nxv4i32(<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv16i8_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv16i8.nxv4i32(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv16i8.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i8>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv16i8.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i8>, <vscale x 16 x i1>, i64)
+
+define void @test_vsxseg3_nxv16i8_nxv16i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv16i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv16i8.nxv16i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv16i8_nxv16i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv16i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv16i8.nxv16i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv16i8.nxv1i64(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv16i8.nxv1i64(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 1 x i64>, <vscale x 16 x i1>, i64)
+
+define void @test_vsxseg3_nxv16i8_nxv1i64(<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv16i8_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei64.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv16i8.nxv1i64(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv16i8_nxv1i64(<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i64> %index, <vscale x 16 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv16i8_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei64.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv16i8.nxv1i64(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i64> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv16i8.nxv1i32(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv16i8.nxv1i32(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 1 x i32>, <vscale x 16 x i1>, i64)
+
+define void @test_vsxseg3_nxv16i8_nxv1i32(<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv16i8_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv16i8.nxv1i32(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv16i8_nxv1i32(<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv16i8_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv16i8.nxv1i32(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv16i8.nxv8i16(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 8 x i16>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv16i8.nxv8i16(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 8 x i16>, <vscale x 16 x i1>, i64)
+
+define void @test_vsxseg3_nxv16i8_nxv8i16(<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv16i8_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv16i8.nxv8i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv16i8_nxv8i16(<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv16i8_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv16i8.nxv8i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv16i8.nxv4i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 4 x i8>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv16i8.nxv4i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 4 x i8>, <vscale x 16 x i1>, i64)
+
+define void @test_vsxseg3_nxv16i8_nxv4i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv16i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv16i8.nxv4i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv16i8_nxv4i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv16i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv16i8.nxv4i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv16i8.nxv1i16(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv16i8.nxv1i16(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 1 x i16>, <vscale x 16 x i1>, i64)
+
+define void @test_vsxseg3_nxv16i8_nxv1i16(<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv16i8_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv16i8.nxv1i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv16i8_nxv1i16(<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv16i8_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv16i8.nxv1i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv16i8.nxv2i32(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 2 x i32>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv16i8.nxv2i32(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 2 x i32>, <vscale x 16 x i1>, i64)
+
+define void @test_vsxseg3_nxv16i8_nxv2i32(<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv16i8_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv16i8.nxv2i32(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv16i8_nxv2i32(<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv16i8_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv16i8.nxv2i32(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv16i8.nxv8i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 8 x i8>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv16i8.nxv8i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 8 x i8>, <vscale x 16 x i1>, i64)
+
+define void @test_vsxseg3_nxv16i8_nxv8i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv16i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv16i8.nxv8i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv16i8_nxv8i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv16i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv16i8.nxv8i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv16i8.nxv4i64(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 4 x i64>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv16i8.nxv4i64(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 4 x i64>, <vscale x 16 x i1>, i64)
+
+define void @test_vsxseg3_nxv16i8_nxv4i64(<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv16i8_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei64.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv16i8.nxv4i64(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv16i8_nxv4i64(<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i64> %index, <vscale x 16 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv16i8_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei64.v v2, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv16i8.nxv4i64(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i64> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv16i8.nxv64i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 64 x i8>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv16i8.nxv64i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 64 x i8>, <vscale x 16 x i1>, i64)
+
+define void @test_vsxseg3_nxv16i8_nxv64i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv16i8_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vmv2r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv16i8.nxv64i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv16i8_nxv64i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv16i8_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vmv2r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv16i8.nxv64i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv16i8.nxv4i16(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 4 x i16>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv16i8.nxv4i16(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 4 x i16>, <vscale x 16 x i1>, i64)
+
+define void @test_vsxseg3_nxv16i8_nxv4i16(<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv16i8_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv16i8.nxv4i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv16i8_nxv4i16(<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv16i8_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv16i8.nxv4i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv16i8.nxv8i64(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 8 x i64>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv16i8.nxv8i64(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 8 x i64>, <vscale x 16 x i1>, i64)
+
+define void @test_vsxseg3_nxv16i8_nxv8i64(<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv16i8_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vmv2r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei64.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv16i8.nxv8i64(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv16i8_nxv8i64(<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i64> %index, <vscale x 16 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv16i8_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vmv2r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei64.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv16i8.nxv8i64(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i64> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv16i8.nxv1i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv16i8.nxv1i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 1 x i8>, <vscale x 16 x i1>, i64)
+
+define void @test_vsxseg3_nxv16i8_nxv1i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv16i8_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv16i8.nxv1i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv16i8_nxv1i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv16i8_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv16i8.nxv1i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv16i8.nxv2i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 2 x i8>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv16i8.nxv2i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 2 x i8>, <vscale x 16 x i1>, i64)
+
+define void @test_vsxseg3_nxv16i8_nxv2i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv16i8_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv16i8.nxv2i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv16i8_nxv2i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv16i8_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv16i8.nxv2i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv16i8.nxv8i32(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 8 x i32>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv16i8.nxv8i32(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 8 x i32>, <vscale x 16 x i1>, i64)
+
+define void @test_vsxseg3_nxv16i8_nxv8i32(<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv16i8_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv16i8.nxv8i32(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv16i8_nxv8i32(<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv16i8_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v2, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv16i8.nxv8i32(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv16i8.nxv32i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 32 x i8>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv16i8.nxv32i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 32 x i8>, <vscale x 16 x i1>, i64)
+
+define void @test_vsxseg3_nxv16i8_nxv32i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv16i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv16i8.nxv32i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv16i8_nxv32i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv16i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v2, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv16i8.nxv32i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv16i8.nxv16i32(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i32>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv16i8.nxv16i32(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i32>, <vscale x 16 x i1>, i64)
+
+define void @test_vsxseg3_nxv16i8_nxv16i32(<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv16i8_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vmv2r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv16i8.nxv16i32(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv16i8_nxv16i32(<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv16i8_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vmv2r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv16i8.nxv16i32(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv16i8.nxv2i16(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 2 x i16>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv16i8.nxv2i16(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 2 x i16>, <vscale x 16 x i1>, i64)
+
+define void @test_vsxseg3_nxv16i8_nxv2i16(<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv16i8_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv16i8.nxv2i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv16i8_nxv2i16(<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv16i8_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv16i8.nxv2i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv16i8.nxv2i64(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 2 x i64>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv16i8.nxv2i64(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 2 x i64>, <vscale x 16 x i1>, i64)
+
+define void @test_vsxseg3_nxv16i8_nxv2i64(<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv16i8_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei64.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv16i8.nxv2i64(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv16i8_nxv2i64(<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i64> %index, <vscale x 16 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv16i8_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei64.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv16i8.nxv2i64(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i64> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv16i8.nxv16i16(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i16>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv16i8.nxv16i16(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i16>, <vscale x 16 x i1>, i64)
+
+define void @test_vsxseg4_nxv16i8_nxv16i16(<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv16i8_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vmv2r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv16i8.nxv16i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv16i8_nxv16i16(<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv16i8_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v2, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv16i8.nxv16i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv16i8.nxv32i16(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 32 x i16>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv16i8.nxv32i16(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 32 x i16>, <vscale x 16 x i1>, i64)
+
+define void @test_vsxseg4_nxv16i8_nxv32i16(<vscale x 16 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv16i8_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2_v22m2
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vmv2r.v v20, v16
+; CHECK-NEXT:    vmv2r.v v22, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv16i8.nxv32i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv16i8_nxv32i16(<vscale x 16 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv16i8_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2_v22m2
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vmv2r.v v20, v16
+; CHECK-NEXT:    vmv2r.v v22, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv16i8.nxv32i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv16i8.nxv4i32(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 4 x i32>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv16i8.nxv4i32(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 4 x i32>, <vscale x 16 x i1>, i64)
+
+define void @test_vsxseg4_nxv16i8_nxv4i32(<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv16i8_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vmv2r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv16i8.nxv4i32(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv16i8_nxv4i32(<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv16i8_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv16i8.nxv4i32(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv16i8.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i8>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv16i8.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i8>, <vscale x 16 x i1>, i64)
+
+define void @test_vsxseg4_nxv16i8_nxv16i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv16i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vmv2r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv16i8.nxv16i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv16i8_nxv16i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv16i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv16i8.nxv16i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv16i8.nxv1i64(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv16i8.nxv1i64(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 1 x i64>, <vscale x 16 x i1>, i64)
+
+define void @test_vsxseg4_nxv16i8_nxv1i64(<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv16i8_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vmv2r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei64.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv16i8.nxv1i64(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv16i8_nxv1i64(<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i64> %index, <vscale x 16 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv16i8_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei64.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv16i8.nxv1i64(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i64> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv16i8.nxv1i32(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv16i8.nxv1i32(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 1 x i32>, <vscale x 16 x i1>, i64)
+
+define void @test_vsxseg4_nxv16i8_nxv1i32(<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv16i8_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vmv2r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv16i8.nxv1i32(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv16i8_nxv1i32(<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv16i8_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv16i8.nxv1i32(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv16i8.nxv8i16(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 8 x i16>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv16i8.nxv8i16(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 8 x i16>, <vscale x 16 x i1>, i64)
+
+define void @test_vsxseg4_nxv16i8_nxv8i16(<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv16i8_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vmv2r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv16i8.nxv8i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv16i8_nxv8i16(<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv16i8_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv16i8.nxv8i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv16i8.nxv4i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 4 x i8>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv16i8.nxv4i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 4 x i8>, <vscale x 16 x i1>, i64)
+
+define void @test_vsxseg4_nxv16i8_nxv4i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv16i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vmv2r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv16i8.nxv4i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv16i8_nxv4i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv16i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv16i8.nxv4i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv16i8.nxv1i16(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv16i8.nxv1i16(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 1 x i16>, <vscale x 16 x i1>, i64)
+
+define void @test_vsxseg4_nxv16i8_nxv1i16(<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv16i8_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vmv2r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv16i8.nxv1i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv16i8_nxv1i16(<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv16i8_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv16i8.nxv1i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv16i8.nxv2i32(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 2 x i32>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv16i8.nxv2i32(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 2 x i32>, <vscale x 16 x i1>, i64)
+
+define void @test_vsxseg4_nxv16i8_nxv2i32(<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv16i8_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vmv2r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv16i8.nxv2i32(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv16i8_nxv2i32(<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv16i8_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv16i8.nxv2i32(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv16i8.nxv8i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 8 x i8>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv16i8.nxv8i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 8 x i8>, <vscale x 16 x i1>, i64)
+
+define void @test_vsxseg4_nxv16i8_nxv8i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv16i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vmv2r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv16i8.nxv8i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv16i8_nxv8i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv16i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv16i8.nxv8i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv16i8.nxv4i64(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 4 x i64>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv16i8.nxv4i64(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 4 x i64>, <vscale x 16 x i1>, i64)
+
+define void @test_vsxseg4_nxv16i8_nxv4i64(<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv16i8_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vmv2r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei64.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv16i8.nxv4i64(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv16i8_nxv4i64(<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i64> %index, <vscale x 16 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv16i8_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei64.v v2, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv16i8.nxv4i64(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i64> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv16i8.nxv64i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 64 x i8>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv16i8.nxv64i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 64 x i8>, <vscale x 16 x i1>, i64)
+
+define void @test_vsxseg4_nxv16i8_nxv64i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv16i8_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2_v22m2
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vmv2r.v v20, v16
+; CHECK-NEXT:    vmv2r.v v22, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv16i8.nxv64i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv16i8_nxv64i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv16i8_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2_v22m2
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vmv2r.v v20, v16
+; CHECK-NEXT:    vmv2r.v v22, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv16i8.nxv64i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv16i8.nxv4i16(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 4 x i16>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv16i8.nxv4i16(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 4 x i16>, <vscale x 16 x i1>, i64)
+
+define void @test_vsxseg4_nxv16i8_nxv4i16(<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv16i8_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vmv2r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv16i8.nxv4i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv16i8_nxv4i16(<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv16i8_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv16i8.nxv4i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv16i8.nxv8i64(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 8 x i64>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv16i8.nxv8i64(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 8 x i64>, <vscale x 16 x i1>, i64)
+
+define void @test_vsxseg4_nxv16i8_nxv8i64(<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv16i8_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2_v22m2
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vmv2r.v v20, v16
+; CHECK-NEXT:    vmv2r.v v22, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei64.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv16i8.nxv8i64(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv16i8_nxv8i64(<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i64> %index, <vscale x 16 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv16i8_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2_v22m2
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vmv2r.v v20, v16
+; CHECK-NEXT:    vmv2r.v v22, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei64.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv16i8.nxv8i64(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i64> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv16i8.nxv1i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv16i8.nxv1i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 1 x i8>, <vscale x 16 x i1>, i64)
+
+define void @test_vsxseg4_nxv16i8_nxv1i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv16i8_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vmv2r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv16i8.nxv1i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv16i8_nxv1i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv16i8_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv16i8.nxv1i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv16i8.nxv2i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 2 x i8>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv16i8.nxv2i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 2 x i8>, <vscale x 16 x i1>, i64)
+
+define void @test_vsxseg4_nxv16i8_nxv2i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv16i8_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vmv2r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv16i8.nxv2i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv16i8_nxv2i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv16i8_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv16i8.nxv2i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv16i8.nxv8i32(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 8 x i32>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv16i8.nxv8i32(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 8 x i32>, <vscale x 16 x i1>, i64)
+
+define void @test_vsxseg4_nxv16i8_nxv8i32(<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv16i8_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vmv2r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv16i8.nxv8i32(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv16i8_nxv8i32(<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv16i8_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v2, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv16i8.nxv8i32(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv16i8.nxv32i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 32 x i8>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv16i8.nxv32i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 32 x i8>, <vscale x 16 x i1>, i64)
+
+define void @test_vsxseg4_nxv16i8_nxv32i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv16i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vmv2r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv16i8.nxv32i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv16i8_nxv32i8(<vscale x 16 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv16i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v2, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv16i8.nxv32i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv16i8.nxv16i32(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i32>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv16i8.nxv16i32(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i32>, <vscale x 16 x i1>, i64)
+
+define void @test_vsxseg4_nxv16i8_nxv16i32(<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv16i8_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2_v22m2
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vmv2r.v v20, v16
+; CHECK-NEXT:    vmv2r.v v22, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv16i8.nxv16i32(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv16i8_nxv16i32(<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv16i8_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2_v22m2
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vmv2r.v v20, v16
+; CHECK-NEXT:    vmv2r.v v22, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv16i8.nxv16i32(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv16i8.nxv2i16(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 2 x i16>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv16i8.nxv2i16(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 2 x i16>, <vscale x 16 x i1>, i64)
+
+define void @test_vsxseg4_nxv16i8_nxv2i16(<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv16i8_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vmv2r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv16i8.nxv2i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv16i8_nxv2i16(<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv16i8_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv16i8.nxv2i16(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv16i8.nxv2i64(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 2 x i64>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv16i8.nxv2i64(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 2 x i64>, <vscale x 16 x i1>, i64)
+
+define void @test_vsxseg4_nxv16i8_nxv2i64(<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv16i8_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vmv2r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei64.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv16i8.nxv2i64(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv16i8_nxv2i64(<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i64> %index, <vscale x 16 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv16i8_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei64.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv16i8.nxv2i64(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 2 x i64> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv1i64.nxv16i16(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 16 x i16>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv1i64.nxv16i16(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 16 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg2_nxv1i64_nxv16i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv1i64_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv1i64.nxv16i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv1i64_nxv16i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv1i64_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv1i64.nxv16i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv1i64.nxv32i16(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 32 x i16>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv1i64.nxv32i16(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 32 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg2_nxv1i64_nxv32i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv1i64_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a2, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv1i64.nxv32i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 32 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv1i64_nxv32i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv1i64_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a2, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv1i64.nxv32i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv1i64.nxv4i32(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i32>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv1i64.nxv4i32(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg2_nxv1i64_nxv4i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv1i64_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv1i64.nxv4i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv1i64_nxv4i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv1i64_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv1i64.nxv4i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv1i64.nxv16i8(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 16 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv1i64.nxv16i8(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 16 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg2_nxv1i64_nxv16i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv1i64_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv1i64.nxv16i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv1i64_nxv16i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv1i64_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv1i64.nxv16i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv1i64.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv1i64.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg2_nxv1i64_nxv1i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv1i64_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv1i64.nxv1i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv1i64_nxv1i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv1i64_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv1i64.nxv1i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv1i64.nxv1i32(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv1i64.nxv1i32(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg2_nxv1i64_nxv1i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv1i64_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv1i64.nxv1i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv1i64_nxv1i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv1i64_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv1i64.nxv1i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv1i64.nxv8i16(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i16>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv1i64.nxv8i16(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg2_nxv1i64_nxv8i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv1i64_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv1i64.nxv8i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv1i64_nxv8i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv1i64_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv1i64.nxv8i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv1i64.nxv4i8(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv1i64.nxv4i8(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg2_nxv1i64_nxv4i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv1i64_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv1i64.nxv4i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv1i64_nxv4i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv1i64_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv1i64.nxv4i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv1i64.nxv1i16(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv1i64.nxv1i16(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg2_nxv1i64_nxv1i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv1i64_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv1i64.nxv1i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv1i64_nxv1i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv1i64_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv1i64.nxv1i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv1i64.nxv2i32(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i32>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv1i64.nxv2i32(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg2_nxv1i64_nxv2i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv1i64_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv1i64.nxv2i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv1i64_nxv2i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv1i64_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv1i64.nxv2i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv1i64.nxv8i8(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv1i64.nxv8i8(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg2_nxv1i64_nxv8i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv1i64_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv1i64.nxv8i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv1i64_nxv8i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv1i64_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv1i64.nxv8i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv1i64.nxv4i64(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i64>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv1i64.nxv4i64(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg2_nxv1i64_nxv4i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv1i64_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv1i64.nxv4i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv1i64_nxv4i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv1i64_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv1i64.nxv4i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv1i64.nxv64i8(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 64 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv1i64.nxv64i8(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 64 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg2_nxv1i64_nxv64i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv1i64_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a2, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv1i64.nxv64i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 64 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv1i64_nxv64i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv1i64_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a2, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv1i64.nxv64i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv1i64.nxv4i16(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i16>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv1i64.nxv4i16(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg2_nxv1i64_nxv4i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv1i64_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv1i64.nxv4i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv1i64_nxv4i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv1i64_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv1i64.nxv4i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv1i64.nxv8i64(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i64>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv1i64.nxv8i64(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg2_nxv1i64_nxv8i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv1i64_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a2, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv1i64.nxv8i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv1i64_nxv8i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv1i64_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a2, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv1i64.nxv8i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv1i64.nxv1i8(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv1i64.nxv1i8(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg2_nxv1i64_nxv1i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv1i64_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv1i64.nxv1i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv1i64_nxv1i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv1i64_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv1i64.nxv1i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv1i64.nxv2i8(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv1i64.nxv2i8(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg2_nxv1i64_nxv2i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv1i64_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv1i64.nxv2i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv1i64_nxv2i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv1i64_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv1i64.nxv2i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv1i64.nxv8i32(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i32>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv1i64.nxv8i32(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg2_nxv1i64_nxv8i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv1i64_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv1i64.nxv8i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv1i64_nxv8i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv1i64_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv1i64.nxv8i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv1i64.nxv32i8(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 32 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv1i64.nxv32i8(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 32 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg2_nxv1i64_nxv32i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv1i64_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv1i64.nxv32i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 32 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv1i64_nxv32i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv1i64_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv1i64.nxv32i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv1i64.nxv16i32(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 16 x i32>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv1i64.nxv16i32(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 16 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg2_nxv1i64_nxv16i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv1i64_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a2, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv1i64.nxv16i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv1i64_nxv16i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv1i64_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a2, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv1i64.nxv16i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv1i64.nxv2i16(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i16>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv1i64.nxv2i16(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg2_nxv1i64_nxv2i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv1i64_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv1i64.nxv2i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv1i64_nxv2i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv1i64_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv1i64.nxv2i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv1i64.nxv2i64(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i64>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv1i64.nxv2i64(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg2_nxv1i64_nxv2i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv1i64_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv1i64.nxv2i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv1i64_nxv2i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv1i64_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv1i64.nxv2i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv1i64.nxv16i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 16 x i16>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv1i64.nxv16i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 16 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg3_nxv1i64_nxv16i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv1i64_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv1i64.nxv16i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv1i64_nxv16i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv1i64_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv1i64.nxv16i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv1i64.nxv32i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 32 x i16>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv1i64.nxv32i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 32 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg3_nxv1i64_nxv32i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv1i64_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a2, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv1i64.nxv32i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 32 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv1i64_nxv32i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv1i64_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a2, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv1i64.nxv32i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv1i64.nxv4i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i32>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv1i64.nxv4i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg3_nxv1i64_nxv4i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv1i64_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv1i64.nxv4i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv1i64_nxv4i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv1i64_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv1i64.nxv4i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv1i64.nxv16i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 16 x i8>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv1i64.nxv16i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 16 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg3_nxv1i64_nxv16i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv1i64_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv1i64.nxv16i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv1i64_nxv16i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv1i64_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv1i64.nxv16i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv1i64.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv1i64.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg3_nxv1i64_nxv1i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv1i64_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei64.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv1i64.nxv1i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv1i64_nxv1i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv1i64_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei64.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv1i64.nxv1i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv1i64.nxv1i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv1i64.nxv1i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg3_nxv1i64_nxv1i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv1i64_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv1i64.nxv1i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv1i64_nxv1i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv1i64_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv1i64.nxv1i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv1i64.nxv8i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i16>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv1i64.nxv8i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg3_nxv1i64_nxv8i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv1i64_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv1i64.nxv8i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv1i64_nxv8i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv1i64_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv1i64.nxv8i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv1i64.nxv4i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i8>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv1i64.nxv4i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg3_nxv1i64_nxv4i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv1i64_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv1i64.nxv4i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv1i64_nxv4i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv1i64_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv1i64.nxv4i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv1i64.nxv1i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv1i64.nxv1i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg3_nxv1i64_nxv1i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv1i64_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv1i64.nxv1i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv1i64_nxv1i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv1i64_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv1i64.nxv1i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv1i64.nxv2i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i32>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv1i64.nxv2i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg3_nxv1i64_nxv2i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv1i64_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv1i64.nxv2i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv1i64_nxv2i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv1i64_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv1i64.nxv2i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv1i64.nxv8i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i8>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv1i64.nxv8i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg3_nxv1i64_nxv8i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv1i64_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv1i64.nxv8i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv1i64_nxv8i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv1i64_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv1i64.nxv8i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv1i64.nxv4i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i64>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv1i64.nxv4i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg3_nxv1i64_nxv4i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv1i64_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei64.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv1i64.nxv4i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv1i64_nxv4i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv1i64_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei64.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv1i64.nxv4i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv1i64.nxv64i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 64 x i8>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv1i64.nxv64i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 64 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg3_nxv1i64_nxv64i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv1i64_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a2, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv1i64.nxv64i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 64 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv1i64_nxv64i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv1i64_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a2, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv1i64.nxv64i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv1i64.nxv4i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i16>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv1i64.nxv4i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg3_nxv1i64_nxv4i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv1i64_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv1i64.nxv4i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv1i64_nxv4i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv1i64_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv1i64.nxv4i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv1i64.nxv8i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i64>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv1i64.nxv8i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg3_nxv1i64_nxv8i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv1i64_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a2, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei64.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv1i64.nxv8i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv1i64_nxv8i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv1i64_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a2, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei64.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv1i64.nxv8i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv1i64.nxv1i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv1i64.nxv1i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg3_nxv1i64_nxv1i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv1i64_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv1i64.nxv1i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv1i64_nxv1i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv1i64_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv1i64.nxv1i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv1i64.nxv2i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i8>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv1i64.nxv2i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg3_nxv1i64_nxv2i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv1i64_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv1i64.nxv2i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv1i64_nxv2i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv1i64_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv1i64.nxv2i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv1i64.nxv8i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i32>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv1i64.nxv8i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg3_nxv1i64_nxv8i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv1i64_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv1i64.nxv8i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv1i64_nxv8i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv1i64_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv1i64.nxv8i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv1i64.nxv32i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 32 x i8>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv1i64.nxv32i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 32 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg3_nxv1i64_nxv32i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv1i64_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv1i64.nxv32i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 32 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv1i64_nxv32i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv1i64_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv1i64.nxv32i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv1i64.nxv16i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 16 x i32>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv1i64.nxv16i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 16 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg3_nxv1i64_nxv16i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv1i64_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a2, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv1i64.nxv16i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv1i64_nxv16i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv1i64_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a2, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv1i64.nxv16i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv1i64.nxv2i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i16>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv1i64.nxv2i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg3_nxv1i64_nxv2i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv1i64_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv1i64.nxv2i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv1i64_nxv2i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv1i64_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv1i64.nxv2i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv1i64.nxv2i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i64>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv1i64.nxv2i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg3_nxv1i64_nxv2i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv1i64_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei64.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv1i64.nxv2i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv1i64_nxv2i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv1i64_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei64.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv1i64.nxv2i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv1i64.nxv16i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 16 x i16>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv1i64.nxv16i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 16 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg4_nxv1i64_nxv16i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv1i64_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv1i64.nxv16i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv1i64_nxv16i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv1i64_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv1i64.nxv16i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv1i64.nxv32i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 32 x i16>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv1i64.nxv32i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 32 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg4_nxv1i64_nxv32i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv1i64_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a2, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv1i64.nxv32i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 32 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv1i64_nxv32i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv1i64_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a2, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv1i64.nxv32i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv1i64.nxv4i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i32>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv1i64.nxv4i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg4_nxv1i64_nxv4i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv1i64_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv1i64.nxv4i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv1i64_nxv4i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv1i64_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv1i64.nxv4i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv1i64.nxv16i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 16 x i8>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv1i64.nxv16i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 16 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg4_nxv1i64_nxv16i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv1i64_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv1i64.nxv16i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv1i64_nxv16i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv1i64_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv1i64.nxv16i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv1i64.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv1i64.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg4_nxv1i64_nxv1i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv1i64_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei64.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv1i64.nxv1i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv1i64_nxv1i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv1i64_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei64.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv1i64.nxv1i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv1i64.nxv1i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv1i64.nxv1i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg4_nxv1i64_nxv1i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv1i64_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv1i64.nxv1i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv1i64_nxv1i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv1i64_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv1i64.nxv1i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv1i64.nxv8i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i16>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv1i64.nxv8i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg4_nxv1i64_nxv8i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv1i64_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv1i64.nxv8i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv1i64_nxv8i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv1i64_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv1i64.nxv8i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv1i64.nxv4i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i8>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv1i64.nxv4i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg4_nxv1i64_nxv4i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv1i64_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv1i64.nxv4i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv1i64_nxv4i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv1i64_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv1i64.nxv4i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv1i64.nxv1i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv1i64.nxv1i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg4_nxv1i64_nxv1i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv1i64_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv1i64.nxv1i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv1i64_nxv1i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv1i64_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv1i64.nxv1i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv1i64.nxv2i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i32>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv1i64.nxv2i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg4_nxv1i64_nxv2i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv1i64_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv1i64.nxv2i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv1i64_nxv2i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv1i64_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv1i64.nxv2i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv1i64.nxv8i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i8>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv1i64.nxv8i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg4_nxv1i64_nxv8i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv1i64_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv1i64.nxv8i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv1i64_nxv8i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv1i64_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv1i64.nxv8i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv1i64.nxv4i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i64>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv1i64.nxv4i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg4_nxv1i64_nxv4i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv1i64_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei64.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv1i64.nxv4i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv1i64_nxv4i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv1i64_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei64.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv1i64.nxv4i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv1i64.nxv64i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 64 x i8>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv1i64.nxv64i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 64 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg4_nxv1i64_nxv64i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv1i64_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a2, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv1i64.nxv64i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 64 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv1i64_nxv64i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv1i64_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a2, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv1i64.nxv64i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv1i64.nxv4i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i16>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv1i64.nxv4i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg4_nxv1i64_nxv4i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv1i64_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv1i64.nxv4i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv1i64_nxv4i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv1i64_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv1i64.nxv4i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv1i64.nxv8i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i64>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv1i64.nxv8i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg4_nxv1i64_nxv8i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv1i64_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a2, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei64.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv1i64.nxv8i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv1i64_nxv8i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv1i64_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a2, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei64.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv1i64.nxv8i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv1i64.nxv1i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv1i64.nxv1i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg4_nxv1i64_nxv1i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv1i64_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv1i64.nxv1i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv1i64_nxv1i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv1i64_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv1i64.nxv1i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv1i64.nxv2i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i8>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv1i64.nxv2i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg4_nxv1i64_nxv2i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv1i64_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv1i64.nxv2i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv1i64_nxv2i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv1i64_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv1i64.nxv2i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv1i64.nxv8i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i32>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv1i64.nxv8i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg4_nxv1i64_nxv8i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv1i64_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv1i64.nxv8i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv1i64_nxv8i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv1i64_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv1i64.nxv8i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv1i64.nxv32i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 32 x i8>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv1i64.nxv32i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 32 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg4_nxv1i64_nxv32i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv1i64_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv1i64.nxv32i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 32 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv1i64_nxv32i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv1i64_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv1i64.nxv32i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv1i64.nxv16i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 16 x i32>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv1i64.nxv16i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 16 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg4_nxv1i64_nxv16i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv1i64_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a2, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv1i64.nxv16i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv1i64_nxv16i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv1i64_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a2, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv1i64.nxv16i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv1i64.nxv2i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i16>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv1i64.nxv2i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg4_nxv1i64_nxv2i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv1i64_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv1i64.nxv2i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv1i64_nxv2i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv1i64_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv1i64.nxv2i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv1i64.nxv2i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i64>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv1i64.nxv2i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg4_nxv1i64_nxv2i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv1i64_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei64.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv1i64.nxv2i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv1i64_nxv2i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv1i64_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei64.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv1i64.nxv2i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv1i64.nxv16i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 16 x i16>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv1i64.nxv16i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 16 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg5_nxv1i64_nxv16i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv1i64_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv1i64.nxv16i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv1i64_nxv16i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv1i64_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv1i64.nxv16i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv1i64.nxv32i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 32 x i16>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv1i64.nxv32i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 32 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg5_nxv1i64_nxv32i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv1i64_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv1i64.nxv32i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 32 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv1i64_nxv32i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv1i64_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv1i64.nxv32i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv1i64.nxv4i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i32>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv1i64.nxv4i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg5_nxv1i64_nxv4i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv1i64_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei32.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv1i64.nxv4i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv1i64_nxv4i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv1i64_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei32.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv1i64.nxv4i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv1i64.nxv16i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 16 x i8>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv1i64.nxv16i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 16 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg5_nxv1i64_nxv16i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv1i64_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv1i64.nxv16i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv1i64_nxv16i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv1i64_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv1i64.nxv16i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv1i64.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv1i64.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg5_nxv1i64_nxv1i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv1i64_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei64.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv1i64.nxv1i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv1i64_nxv1i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv1i64_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei64.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv1i64.nxv1i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv1i64.nxv1i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv1i64.nxv1i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg5_nxv1i64_nxv1i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv1i64_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv1i64.nxv1i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv1i64_nxv1i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv1i64_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv1i64.nxv1i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv1i64.nxv8i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i16>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv1i64.nxv8i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg5_nxv1i64_nxv8i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv1i64_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv1i64.nxv8i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv1i64_nxv8i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv1i64_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv1i64.nxv8i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv1i64.nxv4i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i8>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv1i64.nxv4i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg5_nxv1i64_nxv4i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv1i64_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv1i64.nxv4i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv1i64_nxv4i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv1i64_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv1i64.nxv4i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv1i64.nxv1i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv1i64.nxv1i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg5_nxv1i64_nxv1i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv1i64_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv1i64.nxv1i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv1i64_nxv1i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv1i64_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv1i64.nxv1i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv1i64.nxv2i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i32>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv1i64.nxv2i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg5_nxv1i64_nxv2i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv1i64_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv1i64.nxv2i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv1i64_nxv2i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv1i64_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv1i64.nxv2i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv1i64.nxv8i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i8>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv1i64.nxv8i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg5_nxv1i64_nxv8i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv1i64_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv1i64.nxv8i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv1i64_nxv8i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv1i64_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv1i64.nxv8i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv1i64.nxv4i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i64>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv1i64.nxv4i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg5_nxv1i64_nxv4i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv1i64_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei64.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv1i64.nxv4i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv1i64_nxv4i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv1i64_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei64.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv1i64.nxv4i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv1i64.nxv64i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 64 x i8>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv1i64.nxv64i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 64 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg5_nxv1i64_nxv64i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv1i64_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv1i64.nxv64i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 64 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv1i64_nxv64i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv1i64_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv1i64.nxv64i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv1i64.nxv4i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i16>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv1i64.nxv4i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg5_nxv1i64_nxv4i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv1i64_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv1i64.nxv4i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv1i64_nxv4i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv1i64_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv1i64.nxv4i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv1i64.nxv8i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i64>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv1i64.nxv8i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg5_nxv1i64_nxv8i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv1i64_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei64.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv1i64.nxv8i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv1i64_nxv8i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv1i64_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei64.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv1i64.nxv8i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv1i64.nxv1i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv1i64.nxv1i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg5_nxv1i64_nxv1i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv1i64_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv1i64.nxv1i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv1i64_nxv1i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv1i64_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv1i64.nxv1i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv1i64.nxv2i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i8>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv1i64.nxv2i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg5_nxv1i64_nxv2i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv1i64_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv1i64.nxv2i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv1i64_nxv2i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv1i64_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv1i64.nxv2i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv1i64.nxv8i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i32>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv1i64.nxv8i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg5_nxv1i64_nxv8i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv1i64_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei32.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv1i64.nxv8i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv1i64_nxv8i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv1i64_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei32.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv1i64.nxv8i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv1i64.nxv32i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 32 x i8>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv1i64.nxv32i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 32 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg5_nxv1i64_nxv32i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv1i64_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv1i64.nxv32i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 32 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv1i64_nxv32i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv1i64_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv1i64.nxv32i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv1i64.nxv16i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 16 x i32>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv1i64.nxv16i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 16 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg5_nxv1i64_nxv16i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv1i64_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei32.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv1i64.nxv16i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv1i64_nxv16i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv1i64_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei32.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv1i64.nxv16i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv1i64.nxv2i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i16>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv1i64.nxv2i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg5_nxv1i64_nxv2i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv1i64_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv1i64.nxv2i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv1i64_nxv2i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv1i64_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv1i64.nxv2i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv1i64.nxv2i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i64>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv1i64.nxv2i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg5_nxv1i64_nxv2i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv1i64_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei64.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv1i64.nxv2i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv1i64_nxv2i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv1i64_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei64.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv1i64.nxv2i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv1i64.nxv16i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 16 x i16>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv1i64.nxv16i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 16 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg6_nxv1i64_nxv16i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv1i64_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv1i64.nxv16i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv1i64_nxv16i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv1i64_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv1i64.nxv16i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv1i64.nxv32i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 32 x i16>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv1i64.nxv32i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 32 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg6_nxv1i64_nxv32i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv1i64_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vsetvli a1, a2, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv1i64.nxv32i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 32 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv1i64_nxv32i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv1i64_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vsetvli a1, a2, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv1i64.nxv32i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv1i64.nxv4i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i32>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv1i64.nxv4i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg6_nxv1i64_nxv4i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv1i64_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei32.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv1i64.nxv4i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv1i64_nxv4i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv1i64_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei32.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv1i64.nxv4i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv1i64.nxv16i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 16 x i8>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv1i64.nxv16i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 16 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg6_nxv1i64_nxv16i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv1i64_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv1i64.nxv16i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv1i64_nxv16i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv1i64_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv1i64.nxv16i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv1i64.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv1i64.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg6_nxv1i64_nxv1i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv1i64_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei64.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv1i64.nxv1i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv1i64_nxv1i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv1i64_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei64.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv1i64.nxv1i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv1i64.nxv1i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv1i64.nxv1i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg6_nxv1i64_nxv1i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv1i64_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv1i64.nxv1i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv1i64_nxv1i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv1i64_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv1i64.nxv1i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv1i64.nxv8i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i16>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv1i64.nxv8i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg6_nxv1i64_nxv8i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv1i64_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv1i64.nxv8i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv1i64_nxv8i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv1i64_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv1i64.nxv8i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv1i64.nxv4i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i8>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv1i64.nxv4i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg6_nxv1i64_nxv4i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv1i64_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv1i64.nxv4i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv1i64_nxv4i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv1i64_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv1i64.nxv4i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv1i64.nxv1i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv1i64.nxv1i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg6_nxv1i64_nxv1i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv1i64_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv1i64.nxv1i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv1i64_nxv1i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv1i64_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv1i64.nxv1i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv1i64.nxv2i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i32>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv1i64.nxv2i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg6_nxv1i64_nxv2i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv1i64_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv1i64.nxv2i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv1i64_nxv2i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv1i64_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv1i64.nxv2i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv1i64.nxv8i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i8>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv1i64.nxv8i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg6_nxv1i64_nxv8i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv1i64_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv1i64.nxv8i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv1i64_nxv8i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv1i64_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv1i64.nxv8i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv1i64.nxv4i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i64>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv1i64.nxv4i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg6_nxv1i64_nxv4i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv1i64_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei64.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv1i64.nxv4i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv1i64_nxv4i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv1i64_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei64.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv1i64.nxv4i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv1i64.nxv64i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 64 x i8>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv1i64.nxv64i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 64 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg6_nxv1i64_nxv64i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv1i64_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vsetvli a1, a2, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv1i64.nxv64i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 64 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv1i64_nxv64i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv1i64_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vsetvli a1, a2, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv1i64.nxv64i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv1i64.nxv4i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i16>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv1i64.nxv4i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg6_nxv1i64_nxv4i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv1i64_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv1i64.nxv4i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv1i64_nxv4i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv1i64_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv1i64.nxv4i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv1i64.nxv8i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i64>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv1i64.nxv8i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg6_nxv1i64_nxv8i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv1i64_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vsetvli a1, a2, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei64.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv1i64.nxv8i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv1i64_nxv8i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv1i64_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vsetvli a1, a2, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei64.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv1i64.nxv8i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv1i64.nxv1i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv1i64.nxv1i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg6_nxv1i64_nxv1i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv1i64_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv1i64.nxv1i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv1i64_nxv1i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv1i64_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv1i64.nxv1i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv1i64.nxv2i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i8>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv1i64.nxv2i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg6_nxv1i64_nxv2i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv1i64_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv1i64.nxv2i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv1i64_nxv2i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv1i64_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv1i64.nxv2i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv1i64.nxv8i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i32>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv1i64.nxv8i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg6_nxv1i64_nxv8i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv1i64_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei32.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv1i64.nxv8i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv1i64_nxv8i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv1i64_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei32.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv1i64.nxv8i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv1i64.nxv32i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 32 x i8>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv1i64.nxv32i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 32 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg6_nxv1i64_nxv32i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv1i64_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv1i64.nxv32i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 32 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv1i64_nxv32i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv1i64_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv1i64.nxv32i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv1i64.nxv16i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 16 x i32>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv1i64.nxv16i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 16 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg6_nxv1i64_nxv16i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv1i64_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vsetvli a1, a2, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei32.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv1i64.nxv16i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv1i64_nxv16i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv1i64_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vsetvli a1, a2, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei32.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv1i64.nxv16i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv1i64.nxv2i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i16>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv1i64.nxv2i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg6_nxv1i64_nxv2i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv1i64_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv1i64.nxv2i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv1i64_nxv2i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv1i64_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv1i64.nxv2i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv1i64.nxv2i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i64>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv1i64.nxv2i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg6_nxv1i64_nxv2i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv1i64_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei64.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv1i64.nxv2i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv1i64_nxv2i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv1i64_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei64.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv1i64.nxv2i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv1i64.nxv16i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 16 x i16>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv1i64.nxv16i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 16 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg7_nxv1i64_nxv16i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv1i64_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv1i64.nxv16i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv1i64_nxv16i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv1i64_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv1i64.nxv16i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv1i64.nxv32i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 32 x i16>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv1i64.nxv32i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 32 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg7_nxv1i64_nxv32i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv1i64_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vsetvli a1, a2, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv1i64.nxv32i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 32 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv1i64_nxv32i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv1i64_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vsetvli a1, a2, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv1i64.nxv32i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv1i64.nxv4i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i32>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv1i64.nxv4i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg7_nxv1i64_nxv4i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv1i64_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei32.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv1i64.nxv4i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv1i64_nxv4i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv1i64_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei32.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv1i64.nxv4i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv1i64.nxv16i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 16 x i8>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv1i64.nxv16i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 16 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg7_nxv1i64_nxv16i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv1i64_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv1i64.nxv16i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv1i64_nxv16i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv1i64_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv1i64.nxv16i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv1i64.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv1i64.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg7_nxv1i64_nxv1i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv1i64_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei64.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv1i64.nxv1i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv1i64_nxv1i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv1i64_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei64.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv1i64.nxv1i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv1i64.nxv1i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv1i64.nxv1i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg7_nxv1i64_nxv1i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv1i64_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv1i64.nxv1i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv1i64_nxv1i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv1i64_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv1i64.nxv1i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv1i64.nxv8i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i16>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv1i64.nxv8i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg7_nxv1i64_nxv8i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv1i64_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv1i64.nxv8i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv1i64_nxv8i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv1i64_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv1i64.nxv8i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv1i64.nxv4i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i8>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv1i64.nxv4i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg7_nxv1i64_nxv4i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv1i64_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv1i64.nxv4i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv1i64_nxv4i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv1i64_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv1i64.nxv4i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv1i64.nxv1i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv1i64.nxv1i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg7_nxv1i64_nxv1i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv1i64_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv1i64.nxv1i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv1i64_nxv1i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv1i64_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv1i64.nxv1i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv1i64.nxv2i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i32>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv1i64.nxv2i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg7_nxv1i64_nxv2i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv1i64_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv1i64.nxv2i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv1i64_nxv2i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv1i64_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv1i64.nxv2i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv1i64.nxv8i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i8>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv1i64.nxv8i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg7_nxv1i64_nxv8i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv1i64_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv1i64.nxv8i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv1i64_nxv8i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv1i64_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv1i64.nxv8i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv1i64.nxv4i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i64>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv1i64.nxv4i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg7_nxv1i64_nxv4i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv1i64_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei64.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv1i64.nxv4i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv1i64_nxv4i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv1i64_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei64.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv1i64.nxv4i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv1i64.nxv64i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 64 x i8>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv1i64.nxv64i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 64 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg7_nxv1i64_nxv64i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv1i64_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vsetvli a1, a2, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv1i64.nxv64i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 64 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv1i64_nxv64i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv1i64_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vsetvli a1, a2, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv1i64.nxv64i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv1i64.nxv4i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i16>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv1i64.nxv4i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg7_nxv1i64_nxv4i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv1i64_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv1i64.nxv4i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv1i64_nxv4i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv1i64_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv1i64.nxv4i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv1i64.nxv8i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i64>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv1i64.nxv8i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg7_nxv1i64_nxv8i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv1i64_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vsetvli a1, a2, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei64.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv1i64.nxv8i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv1i64_nxv8i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv1i64_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vsetvli a1, a2, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei64.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv1i64.nxv8i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv1i64.nxv1i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv1i64.nxv1i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg7_nxv1i64_nxv1i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv1i64_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv1i64.nxv1i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv1i64_nxv1i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv1i64_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv1i64.nxv1i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv1i64.nxv2i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i8>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv1i64.nxv2i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg7_nxv1i64_nxv2i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv1i64_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv1i64.nxv2i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv1i64_nxv2i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv1i64_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv1i64.nxv2i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv1i64.nxv8i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i32>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv1i64.nxv8i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg7_nxv1i64_nxv8i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv1i64_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei32.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv1i64.nxv8i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv1i64_nxv8i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv1i64_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei32.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv1i64.nxv8i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv1i64.nxv32i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 32 x i8>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv1i64.nxv32i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 32 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg7_nxv1i64_nxv32i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv1i64_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv1i64.nxv32i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 32 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv1i64_nxv32i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv1i64_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv1i64.nxv32i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv1i64.nxv16i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 16 x i32>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv1i64.nxv16i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 16 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg7_nxv1i64_nxv16i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv1i64_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vsetvli a1, a2, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei32.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv1i64.nxv16i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv1i64_nxv16i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv1i64_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vsetvli a1, a2, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei32.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv1i64.nxv16i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv1i64.nxv2i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i16>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv1i64.nxv2i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg7_nxv1i64_nxv2i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv1i64_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv1i64.nxv2i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv1i64_nxv2i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv1i64_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv1i64.nxv2i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv1i64.nxv2i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i64>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv1i64.nxv2i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg7_nxv1i64_nxv2i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv1i64_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei64.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv1i64.nxv2i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv1i64_nxv2i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv1i64_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei64.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv1i64.nxv2i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv1i64.nxv16i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 16 x i16>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv1i64.nxv16i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 16 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg8_nxv1i64_nxv16i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv1i64_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv1i64.nxv16i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv1i64_nxv16i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv1i64_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv1i64.nxv16i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv1i64.nxv32i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 32 x i16>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv1i64.nxv32i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 32 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg8_nxv1i64_nxv32i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv1i64_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vmv1r.v v23, v16
+; CHECK-NEXT:    vsetvli a1, a2, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv1i64.nxv32i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 32 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv1i64_nxv32i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv1i64_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vmv1r.v v23, v16
+; CHECK-NEXT:    vsetvli a1, a2, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv1i64.nxv32i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv1i64.nxv4i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i32>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv1i64.nxv4i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg8_nxv1i64_nxv4i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv1i64_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei32.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv1i64.nxv4i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv1i64_nxv4i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv1i64_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei32.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv1i64.nxv4i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv1i64.nxv16i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 16 x i8>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv1i64.nxv16i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 16 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg8_nxv1i64_nxv16i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv1i64_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv1i64.nxv16i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv1i64_nxv16i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv1i64_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv1i64.nxv16i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv1i64.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv1i64.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg8_nxv1i64_nxv1i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv1i64_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei64.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv1i64.nxv1i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv1i64_nxv1i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv1i64_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei64.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv1i64.nxv1i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv1i64.nxv1i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv1i64.nxv1i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg8_nxv1i64_nxv1i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv1i64_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv1i64.nxv1i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv1i64_nxv1i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv1i64_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv1i64.nxv1i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv1i64.nxv8i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i16>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv1i64.nxv8i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg8_nxv1i64_nxv8i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv1i64_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv1i64.nxv8i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv1i64_nxv8i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv1i64_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv1i64.nxv8i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv1i64.nxv4i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i8>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv1i64.nxv4i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg8_nxv1i64_nxv4i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv1i64_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv1i64.nxv4i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv1i64_nxv4i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv1i64_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv1i64.nxv4i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv1i64.nxv1i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv1i64.nxv1i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg8_nxv1i64_nxv1i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv1i64_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv1i64.nxv1i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv1i64_nxv1i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv1i64_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv1i64.nxv1i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv1i64.nxv2i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i32>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv1i64.nxv2i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg8_nxv1i64_nxv2i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv1i64_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv1i64.nxv2i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv1i64_nxv2i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv1i64_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv1i64.nxv2i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv1i64.nxv8i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i8>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv1i64.nxv8i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg8_nxv1i64_nxv8i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv1i64_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv1i64.nxv8i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv1i64_nxv8i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv1i64_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv1i64.nxv8i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv1i64.nxv4i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i64>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv1i64.nxv4i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg8_nxv1i64_nxv4i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv1i64_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei64.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv1i64.nxv4i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv1i64_nxv4i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv1i64_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei64.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv1i64.nxv4i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv1i64.nxv64i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 64 x i8>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv1i64.nxv64i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 64 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg8_nxv1i64_nxv64i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv1i64_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vmv1r.v v23, v16
+; CHECK-NEXT:    vsetvli a1, a2, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv1i64.nxv64i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 64 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv1i64_nxv64i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv1i64_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vmv1r.v v23, v16
+; CHECK-NEXT:    vsetvli a1, a2, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv1i64.nxv64i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv1i64.nxv4i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i16>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv1i64.nxv4i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 4 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg8_nxv1i64_nxv4i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv1i64_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv1i64.nxv4i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv1i64_nxv4i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv1i64_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv1i64.nxv4i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv1i64.nxv8i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i64>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv1i64.nxv8i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg8_nxv1i64_nxv8i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv1i64_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vmv1r.v v23, v16
+; CHECK-NEXT:    vsetvli a1, a2, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei64.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv1i64.nxv8i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv1i64_nxv8i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv1i64_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vmv1r.v v23, v16
+; CHECK-NEXT:    vsetvli a1, a2, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei64.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv1i64.nxv8i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv1i64.nxv1i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv1i64.nxv1i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg8_nxv1i64_nxv1i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv1i64_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv1i64.nxv1i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv1i64_nxv1i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv1i64_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv1i64.nxv1i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv1i64.nxv2i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i8>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv1i64.nxv2i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg8_nxv1i64_nxv2i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv1i64_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv1i64.nxv2i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv1i64_nxv2i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv1i64_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv1i64.nxv2i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv1i64.nxv8i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i32>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv1i64.nxv8i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 8 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg8_nxv1i64_nxv8i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv1i64_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei32.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv1i64.nxv8i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv1i64_nxv8i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv1i64_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei32.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv1i64.nxv8i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv1i64.nxv32i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 32 x i8>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv1i64.nxv32i8(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 32 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg8_nxv1i64_nxv32i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv1i64_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv1i64.nxv32i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 32 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv1i64_nxv32i8(<vscale x 1 x i64> %val, i64* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv1i64_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv1i64.nxv32i8(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv1i64.nxv16i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 16 x i32>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv1i64.nxv16i32(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 16 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg8_nxv1i64_nxv16i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv1i64_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vmv1r.v v23, v16
+; CHECK-NEXT:    vsetvli a1, a2, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei32.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv1i64.nxv16i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv1i64_nxv16i32(<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv1i64_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vmv1r.v v23, v16
+; CHECK-NEXT:    vsetvli a1, a2, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei32.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv1i64.nxv16i32(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv1i64.nxv2i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i16>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv1i64.nxv2i16(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg8_nxv1i64_nxv2i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv1i64_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv1i64.nxv2i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv1i64_nxv2i16(<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv1i64_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv1i64.nxv2i16(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv1i64.nxv2i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i64>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv1i64.nxv2i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 2 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg8_nxv1i64_nxv2i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv1i64_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei64.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv1i64.nxv2i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv1i64_nxv2i64(<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv1i64_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei64.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv1i64.nxv2i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv1i32.nxv16i16(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i16>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv1i32.nxv16i16(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg2_nxv1i32_nxv16i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv1i32_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv1i32.nxv16i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv1i32_nxv16i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv1i32_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv1i32.nxv16i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv1i32.nxv32i16(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 32 x i16>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv1i32.nxv32i16(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 32 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg2_nxv1i32_nxv32i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv1i32_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv1i32.nxv32i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv1i32_nxv32i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv1i32_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv1i32.nxv32i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv1i32.nxv4i32(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i32>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv1i32.nxv4i32(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg2_nxv1i32_nxv4i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv1i32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv1i32.nxv4i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv1i32_nxv4i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv1i32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv1i32.nxv4i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv1i32.nxv16i8(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv1i32.nxv16i8(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg2_nxv1i32_nxv16i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv1i32_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv1i32.nxv16i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv1i32_nxv16i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv1i32_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv1i32.nxv16i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv1i32.nxv1i64(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv1i32.nxv1i64(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg2_nxv1i32_nxv1i64(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv1i32_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv1i32.nxv1i64(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv1i32_nxv1i64(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv1i32_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv1i32.nxv1i64(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv1i32.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv1i32.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg2_nxv1i32_nxv1i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv1i32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv1i32.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv1i32_nxv1i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv1i32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv1i32.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv1i32.nxv8i16(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i16>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv1i32.nxv8i16(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg2_nxv1i32_nxv8i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv1i32_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv1i32.nxv8i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv1i32_nxv8i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv1i32_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv1i32.nxv8i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv1i32.nxv4i8(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv1i32.nxv4i8(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg2_nxv1i32_nxv4i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv1i32_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv1i32.nxv4i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv1i32_nxv4i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv1i32_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv1i32.nxv4i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg2_nxv1i32_nxv1i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv1i32_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv1i32.nxv1i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv1i32_nxv1i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv1i32_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv1i32.nxv1i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv1i32.nxv2i32(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i32>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv1i32.nxv2i32(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg2_nxv1i32_nxv2i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv1i32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv1i32.nxv2i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv1i32_nxv2i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv1i32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv1i32.nxv2i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv1i32.nxv8i8(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv1i32.nxv8i8(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg2_nxv1i32_nxv8i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv1i32_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv1i32.nxv8i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv1i32_nxv8i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv1i32_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv1i32.nxv8i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv1i32.nxv4i64(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i64>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv1i32.nxv4i64(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg2_nxv1i32_nxv4i64(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv1i32_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv1i32.nxv4i64(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv1i32_nxv4i64(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv1i32_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv1i32.nxv4i64(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv1i32.nxv64i8(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 64 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv1i32.nxv64i8(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 64 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg2_nxv1i32_nxv64i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv1i32_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv1i32.nxv64i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 64 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv1i32_nxv64i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv1i32_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv1i32.nxv64i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv1i32.nxv4i16(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i16>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv1i32.nxv4i16(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg2_nxv1i32_nxv4i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv1i32_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv1i32.nxv4i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv1i32_nxv4i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv1i32_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv1i32.nxv4i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv1i32.nxv8i64(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i64>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv1i32.nxv8i64(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg2_nxv1i32_nxv8i64(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv1i32_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv1i32.nxv8i64(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv1i32_nxv8i64(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv1i32_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv1i32.nxv8i64(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv1i32.nxv1i8(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv1i32.nxv1i8(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg2_nxv1i32_nxv1i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv1i32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv1i32.nxv1i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv1i32_nxv1i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv1i32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv1i32.nxv1i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv1i32.nxv2i8(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv1i32.nxv2i8(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg2_nxv1i32_nxv2i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv1i32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv1i32.nxv2i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv1i32_nxv2i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv1i32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv1i32.nxv2i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv1i32.nxv8i32(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i32>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv1i32.nxv8i32(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg2_nxv1i32_nxv8i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv1i32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv1i32.nxv8i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv1i32_nxv8i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv1i32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv1i32.nxv8i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv1i32.nxv32i8(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 32 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv1i32.nxv32i8(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 32 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg2_nxv1i32_nxv32i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv1i32_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv1i32.nxv32i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv1i32_nxv32i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv1i32_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv1i32.nxv32i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv1i32.nxv16i32(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i32>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv1i32.nxv16i32(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg2_nxv1i32_nxv16i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv1i32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv1i32.nxv16i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv1i32_nxv16i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv1i32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv1i32.nxv16i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv1i32.nxv2i16(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i16>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv1i32.nxv2i16(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg2_nxv1i32_nxv2i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv1i32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv1i32.nxv2i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv1i32_nxv2i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv1i32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv1i32.nxv2i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv1i32.nxv2i64(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i64>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv1i32.nxv2i64(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg2_nxv1i32_nxv2i64(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv1i32_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv1i32.nxv2i64(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv1i32_nxv2i64(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv1i32_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv1i32.nxv2i64(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv1i32.nxv16i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i16>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv1i32.nxv16i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg3_nxv1i32_nxv16i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv1i32_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv1i32.nxv16i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv1i32_nxv16i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv1i32_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv1i32.nxv16i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv1i32.nxv32i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 32 x i16>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv1i32.nxv32i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 32 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg3_nxv1i32_nxv32i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv1i32_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv1i32.nxv32i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv1i32_nxv32i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv1i32_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv1i32.nxv32i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv1i32.nxv4i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i32>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv1i32.nxv4i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg3_nxv1i32_nxv4i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv1i32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv1i32.nxv4i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv1i32_nxv4i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv1i32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv1i32.nxv4i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv1i32.nxv16i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i8>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv1i32.nxv16i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg3_nxv1i32_nxv16i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv1i32_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv1i32.nxv16i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv1i32_nxv16i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv1i32_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv1i32.nxv16i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv1i32.nxv1i64(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv1i32.nxv1i64(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg3_nxv1i32_nxv1i64(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv1i32_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei64.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv1i32.nxv1i64(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv1i32_nxv1i64(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv1i32_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei64.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv1i32.nxv1i64(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv1i32.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv1i32.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg3_nxv1i32_nxv1i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv1i32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv1i32.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv1i32_nxv1i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv1i32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv1i32.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv1i32.nxv8i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i16>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv1i32.nxv8i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg3_nxv1i32_nxv8i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv1i32_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv1i32.nxv8i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv1i32_nxv8i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv1i32_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv1i32.nxv8i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv1i32.nxv4i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i8>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv1i32.nxv4i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg3_nxv1i32_nxv4i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv1i32_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv1i32.nxv4i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv1i32_nxv4i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv1i32_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv1i32.nxv4i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg3_nxv1i32_nxv1i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv1i32_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv1i32.nxv1i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv1i32_nxv1i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv1i32_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv1i32.nxv1i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv1i32.nxv2i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i32>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv1i32.nxv2i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg3_nxv1i32_nxv2i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv1i32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv1i32.nxv2i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv1i32_nxv2i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv1i32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv1i32.nxv2i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv1i32.nxv8i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i8>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv1i32.nxv8i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg3_nxv1i32_nxv8i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv1i32_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv1i32.nxv8i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv1i32_nxv8i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv1i32_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv1i32.nxv8i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv1i32.nxv4i64(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i64>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv1i32.nxv4i64(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg3_nxv1i32_nxv4i64(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv1i32_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei64.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv1i32.nxv4i64(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv1i32_nxv4i64(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv1i32_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei64.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv1i32.nxv4i64(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv1i32.nxv64i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 64 x i8>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv1i32.nxv64i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 64 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg3_nxv1i32_nxv64i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv1i32_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv1i32.nxv64i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 64 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv1i32_nxv64i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv1i32_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv1i32.nxv64i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv1i32.nxv4i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i16>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv1i32.nxv4i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg3_nxv1i32_nxv4i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv1i32_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv1i32.nxv4i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv1i32_nxv4i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv1i32_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv1i32.nxv4i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv1i32.nxv8i64(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i64>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv1i32.nxv8i64(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg3_nxv1i32_nxv8i64(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv1i32_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei64.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv1i32.nxv8i64(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv1i32_nxv8i64(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv1i32_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei64.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv1i32.nxv8i64(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv1i32.nxv1i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv1i32.nxv1i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg3_nxv1i32_nxv1i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv1i32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv1i32.nxv1i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv1i32_nxv1i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv1i32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv1i32.nxv1i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv1i32.nxv2i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i8>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv1i32.nxv2i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg3_nxv1i32_nxv2i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv1i32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv1i32.nxv2i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv1i32_nxv2i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv1i32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv1i32.nxv2i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv1i32.nxv8i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i32>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv1i32.nxv8i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg3_nxv1i32_nxv8i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv1i32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv1i32.nxv8i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv1i32_nxv8i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv1i32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv1i32.nxv8i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv1i32.nxv32i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 32 x i8>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv1i32.nxv32i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 32 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg3_nxv1i32_nxv32i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv1i32_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv1i32.nxv32i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv1i32_nxv32i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv1i32_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv1i32.nxv32i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv1i32.nxv16i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i32>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv1i32.nxv16i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg3_nxv1i32_nxv16i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv1i32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv1i32.nxv16i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv1i32_nxv16i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv1i32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv1i32.nxv16i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv1i32.nxv2i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i16>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv1i32.nxv2i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg3_nxv1i32_nxv2i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv1i32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv1i32.nxv2i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv1i32_nxv2i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv1i32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv1i32.nxv2i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv1i32.nxv2i64(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i64>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv1i32.nxv2i64(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg3_nxv1i32_nxv2i64(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv1i32_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei64.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv1i32.nxv2i64(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv1i32_nxv2i64(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv1i32_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei64.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv1i32.nxv2i64(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv1i32.nxv16i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i16>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv1i32.nxv16i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg4_nxv1i32_nxv16i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv1i32_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv1i32.nxv16i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv1i32_nxv16i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv1i32_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv1i32.nxv16i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv1i32.nxv32i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 32 x i16>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv1i32.nxv32i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 32 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg4_nxv1i32_nxv32i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv1i32_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv1i32.nxv32i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv1i32_nxv32i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv1i32_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv1i32.nxv32i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv1i32.nxv4i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i32>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv1i32.nxv4i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg4_nxv1i32_nxv4i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv1i32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv1i32.nxv4i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv1i32_nxv4i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv1i32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv1i32.nxv4i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv1i32.nxv16i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i8>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv1i32.nxv16i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg4_nxv1i32_nxv16i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv1i32_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv1i32.nxv16i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv1i32_nxv16i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv1i32_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv1i32.nxv16i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv1i32.nxv1i64(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv1i32.nxv1i64(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg4_nxv1i32_nxv1i64(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv1i32_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei64.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv1i32.nxv1i64(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv1i32_nxv1i64(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv1i32_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei64.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv1i32.nxv1i64(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv1i32.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv1i32.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg4_nxv1i32_nxv1i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv1i32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv1i32.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv1i32_nxv1i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv1i32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv1i32.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv1i32.nxv8i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i16>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv1i32.nxv8i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg4_nxv1i32_nxv8i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv1i32_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv1i32.nxv8i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv1i32_nxv8i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv1i32_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv1i32.nxv8i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv1i32.nxv4i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i8>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv1i32.nxv4i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg4_nxv1i32_nxv4i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv1i32_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv1i32.nxv4i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv1i32_nxv4i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv1i32_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv1i32.nxv4i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg4_nxv1i32_nxv1i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv1i32_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv1i32.nxv1i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv1i32_nxv1i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv1i32_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv1i32.nxv1i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv1i32.nxv2i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i32>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv1i32.nxv2i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg4_nxv1i32_nxv2i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv1i32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv1i32.nxv2i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv1i32_nxv2i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv1i32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv1i32.nxv2i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv1i32.nxv8i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i8>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv1i32.nxv8i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg4_nxv1i32_nxv8i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv1i32_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv1i32.nxv8i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv1i32_nxv8i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv1i32_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv1i32.nxv8i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv1i32.nxv4i64(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i64>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv1i32.nxv4i64(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg4_nxv1i32_nxv4i64(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv1i32_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei64.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv1i32.nxv4i64(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv1i32_nxv4i64(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv1i32_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei64.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv1i32.nxv4i64(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv1i32.nxv64i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 64 x i8>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv1i32.nxv64i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 64 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg4_nxv1i32_nxv64i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv1i32_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv1i32.nxv64i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 64 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv1i32_nxv64i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv1i32_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv1i32.nxv64i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv1i32.nxv4i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i16>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv1i32.nxv4i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg4_nxv1i32_nxv4i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv1i32_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv1i32.nxv4i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv1i32_nxv4i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv1i32_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv1i32.nxv4i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv1i32.nxv8i64(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i64>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv1i32.nxv8i64(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg4_nxv1i32_nxv8i64(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv1i32_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei64.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv1i32.nxv8i64(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv1i32_nxv8i64(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv1i32_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei64.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv1i32.nxv8i64(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv1i32.nxv1i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv1i32.nxv1i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg4_nxv1i32_nxv1i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv1i32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv1i32.nxv1i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv1i32_nxv1i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv1i32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv1i32.nxv1i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv1i32.nxv2i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i8>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv1i32.nxv2i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg4_nxv1i32_nxv2i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv1i32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv1i32.nxv2i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv1i32_nxv2i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv1i32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv1i32.nxv2i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv1i32.nxv8i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i32>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv1i32.nxv8i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg4_nxv1i32_nxv8i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv1i32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv1i32.nxv8i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv1i32_nxv8i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv1i32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv1i32.nxv8i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv1i32.nxv32i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 32 x i8>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv1i32.nxv32i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 32 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg4_nxv1i32_nxv32i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv1i32_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv1i32.nxv32i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv1i32_nxv32i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv1i32_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv1i32.nxv32i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv1i32.nxv16i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i32>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv1i32.nxv16i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg4_nxv1i32_nxv16i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv1i32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv1i32.nxv16i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv1i32_nxv16i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv1i32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv1i32.nxv16i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv1i32.nxv2i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i16>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv1i32.nxv2i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg4_nxv1i32_nxv2i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv1i32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv1i32.nxv2i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv1i32_nxv2i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv1i32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv1i32.nxv2i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv1i32.nxv2i64(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i64>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv1i32.nxv2i64(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg4_nxv1i32_nxv2i64(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv1i32_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei64.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv1i32.nxv2i64(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv1i32_nxv2i64(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv1i32_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei64.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv1i32.nxv2i64(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv1i32.nxv16i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i16>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv1i32.nxv16i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg5_nxv1i32_nxv16i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv1i32_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv1i32.nxv16i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv1i32_nxv16i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv1i32_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv1i32.nxv16i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv1i32.nxv32i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 32 x i16>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv1i32.nxv32i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 32 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg5_nxv1i32_nxv32i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv1i32_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv1i32.nxv32i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv1i32_nxv32i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv1i32_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv1i32.nxv32i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv1i32.nxv4i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i32>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv1i32.nxv4i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg5_nxv1i32_nxv4i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv1i32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei32.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv1i32.nxv4i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv1i32_nxv4i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv1i32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei32.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv1i32.nxv4i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv1i32.nxv16i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i8>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv1i32.nxv16i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg5_nxv1i32_nxv16i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv1i32_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv1i32.nxv16i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv1i32_nxv16i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv1i32_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv1i32.nxv16i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv1i32.nxv1i64(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv1i32.nxv1i64(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg5_nxv1i32_nxv1i64(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv1i32_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei64.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv1i32.nxv1i64(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv1i32_nxv1i64(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv1i32_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei64.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv1i32.nxv1i64(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv1i32.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv1i32.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg5_nxv1i32_nxv1i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv1i32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv1i32.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv1i32_nxv1i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv1i32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv1i32.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv1i32.nxv8i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i16>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv1i32.nxv8i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg5_nxv1i32_nxv8i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv1i32_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv1i32.nxv8i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv1i32_nxv8i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv1i32_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv1i32.nxv8i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv1i32.nxv4i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i8>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv1i32.nxv4i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg5_nxv1i32_nxv4i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv1i32_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv1i32.nxv4i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv1i32_nxv4i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv1i32_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv1i32.nxv4i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg5_nxv1i32_nxv1i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv1i32_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv1i32.nxv1i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv1i32_nxv1i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv1i32_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv1i32.nxv1i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv1i32.nxv2i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i32>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv1i32.nxv2i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg5_nxv1i32_nxv2i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv1i32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv1i32.nxv2i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv1i32_nxv2i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv1i32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv1i32.nxv2i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv1i32.nxv8i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i8>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv1i32.nxv8i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg5_nxv1i32_nxv8i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv1i32_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv1i32.nxv8i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv1i32_nxv8i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv1i32_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv1i32.nxv8i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv1i32.nxv4i64(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i64>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv1i32.nxv4i64(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg5_nxv1i32_nxv4i64(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv1i32_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei64.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv1i32.nxv4i64(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv1i32_nxv4i64(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv1i32_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei64.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv1i32.nxv4i64(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv1i32.nxv64i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 64 x i8>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv1i32.nxv64i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 64 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg5_nxv1i32_nxv64i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv1i32_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv1i32.nxv64i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 64 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv1i32_nxv64i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv1i32_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv1i32.nxv64i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv1i32.nxv4i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i16>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv1i32.nxv4i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg5_nxv1i32_nxv4i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv1i32_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv1i32.nxv4i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv1i32_nxv4i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv1i32_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv1i32.nxv4i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv1i32.nxv8i64(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i64>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv1i32.nxv8i64(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg5_nxv1i32_nxv8i64(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv1i32_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei64.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv1i32.nxv8i64(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv1i32_nxv8i64(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv1i32_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei64.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv1i32.nxv8i64(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv1i32.nxv1i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv1i32.nxv1i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg5_nxv1i32_nxv1i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv1i32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv1i32.nxv1i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv1i32_nxv1i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv1i32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv1i32.nxv1i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv1i32.nxv2i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i8>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv1i32.nxv2i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg5_nxv1i32_nxv2i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv1i32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv1i32.nxv2i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv1i32_nxv2i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv1i32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv1i32.nxv2i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv1i32.nxv8i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i32>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv1i32.nxv8i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg5_nxv1i32_nxv8i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv1i32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei32.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv1i32.nxv8i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv1i32_nxv8i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv1i32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei32.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv1i32.nxv8i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv1i32.nxv32i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 32 x i8>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv1i32.nxv32i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 32 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg5_nxv1i32_nxv32i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv1i32_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv1i32.nxv32i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv1i32_nxv32i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv1i32_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv1i32.nxv32i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv1i32.nxv16i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i32>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv1i32.nxv16i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg5_nxv1i32_nxv16i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv1i32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei32.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv1i32.nxv16i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv1i32_nxv16i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv1i32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei32.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv1i32.nxv16i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv1i32.nxv2i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i16>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv1i32.nxv2i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg5_nxv1i32_nxv2i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv1i32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv1i32.nxv2i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv1i32_nxv2i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv1i32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv1i32.nxv2i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv1i32.nxv2i64(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i64>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv1i32.nxv2i64(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg5_nxv1i32_nxv2i64(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv1i32_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei64.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv1i32.nxv2i64(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv1i32_nxv2i64(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv1i32_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei64.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv1i32.nxv2i64(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv1i32.nxv16i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i16>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv1i32.nxv16i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg6_nxv1i32_nxv16i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv1i32_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv1i32.nxv16i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv1i32_nxv16i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv1i32_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv1i32.nxv16i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv1i32.nxv32i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 32 x i16>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv1i32.nxv32i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 32 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg6_nxv1i32_nxv32i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv1i32_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv1i32.nxv32i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv1i32_nxv32i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv1i32_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv1i32.nxv32i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv1i32.nxv4i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i32>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv1i32.nxv4i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg6_nxv1i32_nxv4i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv1i32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei32.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv1i32.nxv4i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv1i32_nxv4i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv1i32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei32.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv1i32.nxv4i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv1i32.nxv16i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i8>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv1i32.nxv16i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg6_nxv1i32_nxv16i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv1i32_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv1i32.nxv16i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv1i32_nxv16i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv1i32_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv1i32.nxv16i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv1i32.nxv1i64(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv1i32.nxv1i64(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg6_nxv1i32_nxv1i64(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv1i32_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei64.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv1i32.nxv1i64(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv1i32_nxv1i64(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv1i32_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei64.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv1i32.nxv1i64(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv1i32.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv1i32.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg6_nxv1i32_nxv1i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv1i32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv1i32.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv1i32_nxv1i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv1i32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv1i32.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv1i32.nxv8i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i16>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv1i32.nxv8i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg6_nxv1i32_nxv8i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv1i32_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv1i32.nxv8i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv1i32_nxv8i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv1i32_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv1i32.nxv8i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv1i32.nxv4i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i8>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv1i32.nxv4i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg6_nxv1i32_nxv4i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv1i32_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv1i32.nxv4i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv1i32_nxv4i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv1i32_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv1i32.nxv4i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg6_nxv1i32_nxv1i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv1i32_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv1i32.nxv1i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv1i32_nxv1i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv1i32_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv1i32.nxv1i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv1i32.nxv2i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i32>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv1i32.nxv2i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg6_nxv1i32_nxv2i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv1i32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv1i32.nxv2i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv1i32_nxv2i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv1i32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv1i32.nxv2i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv1i32.nxv8i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i8>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv1i32.nxv8i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg6_nxv1i32_nxv8i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv1i32_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv1i32.nxv8i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv1i32_nxv8i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv1i32_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv1i32.nxv8i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv1i32.nxv4i64(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i64>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv1i32.nxv4i64(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg6_nxv1i32_nxv4i64(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv1i32_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei64.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv1i32.nxv4i64(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv1i32_nxv4i64(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv1i32_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei64.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv1i32.nxv4i64(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv1i32.nxv64i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 64 x i8>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv1i32.nxv64i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 64 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg6_nxv1i32_nxv64i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv1i32_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv1i32.nxv64i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 64 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv1i32_nxv64i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv1i32_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv1i32.nxv64i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv1i32.nxv4i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i16>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv1i32.nxv4i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg6_nxv1i32_nxv4i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv1i32_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv1i32.nxv4i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv1i32_nxv4i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv1i32_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv1i32.nxv4i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv1i32.nxv8i64(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i64>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv1i32.nxv8i64(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg6_nxv1i32_nxv8i64(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv1i32_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei64.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv1i32.nxv8i64(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv1i32_nxv8i64(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv1i32_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei64.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv1i32.nxv8i64(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv1i32.nxv1i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv1i32.nxv1i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg6_nxv1i32_nxv1i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv1i32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv1i32.nxv1i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv1i32_nxv1i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv1i32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv1i32.nxv1i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv1i32.nxv2i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i8>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv1i32.nxv2i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg6_nxv1i32_nxv2i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv1i32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv1i32.nxv2i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv1i32_nxv2i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv1i32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv1i32.nxv2i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv1i32.nxv8i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i32>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv1i32.nxv8i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg6_nxv1i32_nxv8i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv1i32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei32.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv1i32.nxv8i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv1i32_nxv8i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv1i32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei32.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv1i32.nxv8i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv1i32.nxv32i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 32 x i8>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv1i32.nxv32i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 32 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg6_nxv1i32_nxv32i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv1i32_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv1i32.nxv32i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv1i32_nxv32i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv1i32_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv1i32.nxv32i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv1i32.nxv16i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i32>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv1i32.nxv16i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg6_nxv1i32_nxv16i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv1i32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei32.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv1i32.nxv16i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv1i32_nxv16i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv1i32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei32.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv1i32.nxv16i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv1i32.nxv2i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i16>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv1i32.nxv2i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg6_nxv1i32_nxv2i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv1i32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv1i32.nxv2i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv1i32_nxv2i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv1i32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv1i32.nxv2i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv1i32.nxv2i64(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i64>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv1i32.nxv2i64(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg6_nxv1i32_nxv2i64(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv1i32_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei64.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv1i32.nxv2i64(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv1i32_nxv2i64(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv1i32_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei64.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv1i32.nxv2i64(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv1i32.nxv16i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i16>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv1i32.nxv16i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg7_nxv1i32_nxv16i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv1i32_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv1i32.nxv16i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv1i32_nxv16i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv1i32_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv1i32.nxv16i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv1i32.nxv32i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 32 x i16>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv1i32.nxv32i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 32 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg7_nxv1i32_nxv32i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv1i32_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv1i32.nxv32i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv1i32_nxv32i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv1i32_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv1i32.nxv32i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv1i32.nxv4i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i32>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv1i32.nxv4i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg7_nxv1i32_nxv4i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv1i32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei32.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv1i32.nxv4i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv1i32_nxv4i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv1i32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei32.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv1i32.nxv4i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv1i32.nxv16i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i8>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv1i32.nxv16i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg7_nxv1i32_nxv16i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv1i32_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv1i32.nxv16i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv1i32_nxv16i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv1i32_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv1i32.nxv16i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv1i32.nxv1i64(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv1i32.nxv1i64(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg7_nxv1i32_nxv1i64(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv1i32_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei64.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv1i32.nxv1i64(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv1i32_nxv1i64(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv1i32_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei64.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv1i32.nxv1i64(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv1i32.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv1i32.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg7_nxv1i32_nxv1i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv1i32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv1i32.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv1i32_nxv1i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv1i32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv1i32.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv1i32.nxv8i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i16>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv1i32.nxv8i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg7_nxv1i32_nxv8i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv1i32_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv1i32.nxv8i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv1i32_nxv8i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv1i32_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv1i32.nxv8i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv1i32.nxv4i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i8>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv1i32.nxv4i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg7_nxv1i32_nxv4i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv1i32_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv1i32.nxv4i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv1i32_nxv4i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv1i32_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv1i32.nxv4i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg7_nxv1i32_nxv1i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv1i32_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv1i32.nxv1i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv1i32_nxv1i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv1i32_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv1i32.nxv1i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv1i32.nxv2i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i32>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv1i32.nxv2i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg7_nxv1i32_nxv2i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv1i32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv1i32.nxv2i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv1i32_nxv2i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv1i32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv1i32.nxv2i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv1i32.nxv8i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i8>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv1i32.nxv8i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg7_nxv1i32_nxv8i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv1i32_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv1i32.nxv8i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv1i32_nxv8i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv1i32_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv1i32.nxv8i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv1i32.nxv4i64(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i64>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv1i32.nxv4i64(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg7_nxv1i32_nxv4i64(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv1i32_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei64.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv1i32.nxv4i64(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv1i32_nxv4i64(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv1i32_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei64.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv1i32.nxv4i64(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv1i32.nxv64i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 64 x i8>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv1i32.nxv64i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 64 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg7_nxv1i32_nxv64i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv1i32_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv1i32.nxv64i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 64 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv1i32_nxv64i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv1i32_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv1i32.nxv64i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv1i32.nxv4i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i16>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv1i32.nxv4i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg7_nxv1i32_nxv4i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv1i32_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv1i32.nxv4i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv1i32_nxv4i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv1i32_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv1i32.nxv4i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv1i32.nxv8i64(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i64>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv1i32.nxv8i64(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg7_nxv1i32_nxv8i64(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv1i32_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei64.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv1i32.nxv8i64(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv1i32_nxv8i64(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv1i32_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei64.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv1i32.nxv8i64(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv1i32.nxv1i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv1i32.nxv1i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg7_nxv1i32_nxv1i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv1i32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv1i32.nxv1i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv1i32_nxv1i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv1i32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv1i32.nxv1i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv1i32.nxv2i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i8>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv1i32.nxv2i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg7_nxv1i32_nxv2i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv1i32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv1i32.nxv2i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv1i32_nxv2i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv1i32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv1i32.nxv2i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv1i32.nxv8i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i32>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv1i32.nxv8i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg7_nxv1i32_nxv8i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv1i32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei32.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv1i32.nxv8i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv1i32_nxv8i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv1i32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei32.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv1i32.nxv8i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv1i32.nxv32i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 32 x i8>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv1i32.nxv32i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 32 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg7_nxv1i32_nxv32i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv1i32_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv1i32.nxv32i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv1i32_nxv32i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv1i32_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv1i32.nxv32i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv1i32.nxv16i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i32>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv1i32.nxv16i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg7_nxv1i32_nxv16i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv1i32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei32.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv1i32.nxv16i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv1i32_nxv16i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv1i32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei32.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv1i32.nxv16i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv1i32.nxv2i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i16>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv1i32.nxv2i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg7_nxv1i32_nxv2i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv1i32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv1i32.nxv2i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv1i32_nxv2i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv1i32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv1i32.nxv2i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv1i32.nxv2i64(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i64>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv1i32.nxv2i64(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg7_nxv1i32_nxv2i64(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv1i32_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei64.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv1i32.nxv2i64(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv1i32_nxv2i64(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv1i32_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei64.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv1i32.nxv2i64(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv1i32.nxv16i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i16>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv1i32.nxv16i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg8_nxv1i32_nxv16i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv1i32_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv1i32.nxv16i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv1i32_nxv16i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv1i32_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv1i32.nxv16i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv1i32.nxv32i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 32 x i16>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv1i32.nxv32i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 32 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg8_nxv1i32_nxv32i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv1i32_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vmv1r.v v23, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv1i32.nxv32i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv1i32_nxv32i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv1i32_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vmv1r.v v23, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv1i32.nxv32i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv1i32.nxv4i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i32>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv1i32.nxv4i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg8_nxv1i32_nxv4i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv1i32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei32.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv1i32.nxv4i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv1i32_nxv4i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv1i32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei32.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv1i32.nxv4i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv1i32.nxv16i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i8>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv1i32.nxv16i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg8_nxv1i32_nxv16i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv1i32_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv1i32.nxv16i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv1i32_nxv16i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv1i32_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv1i32.nxv16i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv1i32.nxv1i64(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv1i32.nxv1i64(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg8_nxv1i32_nxv1i64(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv1i32_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei64.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv1i32.nxv1i64(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv1i32_nxv1i64(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv1i32_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei64.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv1i32.nxv1i64(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv1i32.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv1i32.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg8_nxv1i32_nxv1i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv1i32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv1i32.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv1i32_nxv1i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv1i32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv1i32.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv1i32.nxv8i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i16>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv1i32.nxv8i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg8_nxv1i32_nxv8i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv1i32_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv1i32.nxv8i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv1i32_nxv8i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv1i32_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv1i32.nxv8i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv1i32.nxv4i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i8>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv1i32.nxv4i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg8_nxv1i32_nxv4i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv1i32_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv1i32.nxv4i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv1i32_nxv4i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv1i32_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv1i32.nxv4i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv1i32.nxv1i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg8_nxv1i32_nxv1i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv1i32_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv1i32.nxv1i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv1i32_nxv1i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv1i32_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv1i32.nxv1i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv1i32.nxv2i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i32>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv1i32.nxv2i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg8_nxv1i32_nxv2i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv1i32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv1i32.nxv2i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv1i32_nxv2i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv1i32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv1i32.nxv2i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv1i32.nxv8i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i8>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv1i32.nxv8i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg8_nxv1i32_nxv8i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv1i32_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv1i32.nxv8i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv1i32_nxv8i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv1i32_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv1i32.nxv8i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv1i32.nxv4i64(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i64>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv1i32.nxv4i64(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg8_nxv1i32_nxv4i64(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv1i32_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei64.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv1i32.nxv4i64(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv1i32_nxv4i64(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv1i32_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei64.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv1i32.nxv4i64(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv1i32.nxv64i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 64 x i8>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv1i32.nxv64i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 64 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg8_nxv1i32_nxv64i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv1i32_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vmv1r.v v23, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv1i32.nxv64i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 64 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv1i32_nxv64i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv1i32_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vmv1r.v v23, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv1i32.nxv64i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv1i32.nxv4i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i16>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv1i32.nxv4i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 4 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg8_nxv1i32_nxv4i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv1i32_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv1i32.nxv4i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv1i32_nxv4i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv1i32_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv1i32.nxv4i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv1i32.nxv8i64(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i64>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv1i32.nxv8i64(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg8_nxv1i32_nxv8i64(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv1i32_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vmv1r.v v23, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei64.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv1i32.nxv8i64(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv1i32_nxv8i64(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv1i32_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vmv1r.v v23, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei64.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv1i32.nxv8i64(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv1i32.nxv1i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv1i32.nxv1i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg8_nxv1i32_nxv1i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv1i32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv1i32.nxv1i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv1i32_nxv1i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv1i32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv1i32.nxv1i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv1i32.nxv2i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i8>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv1i32.nxv2i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg8_nxv1i32_nxv2i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv1i32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv1i32.nxv2i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv1i32_nxv2i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv1i32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv1i32.nxv2i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv1i32.nxv8i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i32>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv1i32.nxv8i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 8 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg8_nxv1i32_nxv8i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv1i32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei32.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv1i32.nxv8i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv1i32_nxv8i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv1i32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei32.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv1i32.nxv8i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv1i32.nxv32i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 32 x i8>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv1i32.nxv32i8(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 32 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg8_nxv1i32_nxv32i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv1i32_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv1i32.nxv32i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv1i32_nxv32i8(<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv1i32_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv1i32.nxv32i8(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv1i32.nxv16i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i32>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv1i32.nxv16i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 16 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg8_nxv1i32_nxv16i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv1i32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vmv1r.v v23, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei32.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv1i32.nxv16i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv1i32_nxv16i32(<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv1i32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vmv1r.v v23, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei32.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv1i32.nxv16i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv1i32.nxv2i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i16>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv1i32.nxv2i16(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg8_nxv1i32_nxv2i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv1i32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv1i32.nxv2i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv1i32_nxv2i16(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv1i32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv1i32.nxv2i16(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv1i32.nxv2i64(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i64>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv1i32.nxv2i64(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 2 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg8_nxv1i32_nxv2i64(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv1i32_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei64.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv1i32.nxv2i64(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv1i32_nxv2i64(<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv1i32_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei64.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv1i32.nxv2i64(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv8i16.nxv16i16(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 16 x i16>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv8i16.nxv16i16(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 16 x i16>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg2_nxv8i16_nxv16i16(<vscale x 8 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv8i16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv8i16.nxv16i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv8i16_nxv16i16(<vscale x 8 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv8i16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv8i16.nxv16i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv8i16.nxv32i16(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 32 x i16>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv8i16.nxv32i16(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 32 x i16>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg2_nxv8i16_nxv32i16(<vscale x 8 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv8i16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv8i16.nxv32i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv8i16_nxv32i16(<vscale x 8 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv8i16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv8i16.nxv32i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv8i16.nxv4i32(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 4 x i32>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv8i16.nxv4i32(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 4 x i32>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg2_nxv8i16_nxv4i32(<vscale x 8 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv8i16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv2r.v v26, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v26
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv8i16.nxv4i32(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv8i16_nxv4i32(<vscale x 8 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv8i16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv2r.v v26, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v26, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv8i16.nxv4i32(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv8i16.nxv16i8(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 16 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv8i16.nxv16i8(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 16 x i8>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg2_nxv8i16_nxv16i8(<vscale x 8 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv8i16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv2r.v v26, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v26
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv8i16.nxv16i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv8i16_nxv16i8(<vscale x 8 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv8i16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv2r.v v26, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v26, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv8i16.nxv16i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv8i16.nxv1i64(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv8i16.nxv1i64(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 1 x i64>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg2_nxv8i16_nxv1i64(<vscale x 8 x i16> %val, i16* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv8i16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv1r.v v25, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv8i16.nxv1i64(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 1 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv8i16_nxv1i64(<vscale x 8 x i16> %val, i16* %base, <vscale x 1 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv8i16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv1r.v v25, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv8i16.nxv1i64(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 1 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv8i16.nxv1i32(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv8i16.nxv1i32(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 1 x i32>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg2_nxv8i16_nxv1i32(<vscale x 8 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv8i16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv1r.v v25, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv8i16.nxv1i32(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv8i16_nxv1i32(<vscale x 8 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv8i16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv1r.v v25, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv8i16.nxv1i32(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv8i16.nxv8i16(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 8 x i16>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv8i16.nxv8i16(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 8 x i16>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg2_nxv8i16_nxv8i16(<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv8i16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv2r.v v26, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v26
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv8i16.nxv8i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv8i16_nxv8i16(<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv8i16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv2r.v v26, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v26, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv8i16.nxv8i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv8i16.nxv4i8(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 4 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv8i16.nxv4i8(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 4 x i8>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg2_nxv8i16_nxv4i8(<vscale x 8 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv8i16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv1r.v v25, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv8i16.nxv4i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv8i16_nxv4i8(<vscale x 8 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv8i16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv1r.v v25, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv8i16.nxv4i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv8i16.nxv1i16(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv8i16.nxv1i16(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 1 x i16>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg2_nxv8i16_nxv1i16(<vscale x 8 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv8i16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv1r.v v25, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv8i16.nxv1i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv8i16_nxv1i16(<vscale x 8 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv8i16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv1r.v v25, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv8i16.nxv1i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv8i16.nxv2i32(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 2 x i32>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv8i16.nxv2i32(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 2 x i32>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg2_nxv8i16_nxv2i32(<vscale x 8 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv8i16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv1r.v v25, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv8i16.nxv2i32(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv8i16_nxv2i32(<vscale x 8 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv8i16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv1r.v v25, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv8i16.nxv2i32(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv8i16.nxv8i8(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 8 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv8i16.nxv8i8(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 8 x i8>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg2_nxv8i16_nxv8i8(<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv8i16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv1r.v v25, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv8i16.nxv8i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv8i16_nxv8i8(<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv8i16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv1r.v v25, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv8i16.nxv8i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv8i16.nxv4i64(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 4 x i64>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv8i16.nxv4i64(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 4 x i64>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg2_nxv8i16_nxv4i64(<vscale x 8 x i16> %val, i16* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv8i16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv8i16.nxv4i64(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 4 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv8i16_nxv4i64(<vscale x 8 x i16> %val, i16* %base, <vscale x 4 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv8i16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv8i16.nxv4i64(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 4 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv8i16.nxv64i8(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 64 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv8i16.nxv64i8(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 64 x i8>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg2_nxv8i16_nxv64i8(<vscale x 8 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv8i16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv8i16.nxv64i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv8i16_nxv64i8(<vscale x 8 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv8i16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv8i16.nxv64i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv8i16.nxv4i16(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 4 x i16>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv8i16.nxv4i16(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 4 x i16>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg2_nxv8i16_nxv4i16(<vscale x 8 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv8i16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv1r.v v25, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv8i16.nxv4i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv8i16_nxv4i16(<vscale x 8 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv8i16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv1r.v v25, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv8i16.nxv4i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv8i16.nxv8i64(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 8 x i64>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv8i16.nxv8i64(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 8 x i64>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg2_nxv8i16_nxv8i64(<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv8i16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv8i16.nxv8i64(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv8i16_nxv8i64(<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv8i16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv8i16.nxv8i64(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv8i16.nxv1i8(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv8i16.nxv1i8(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 1 x i8>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg2_nxv8i16_nxv1i8(<vscale x 8 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv8i16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv1r.v v25, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv8i16.nxv1i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv8i16_nxv1i8(<vscale x 8 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv8i16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv1r.v v25, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv8i16.nxv1i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv8i16.nxv2i8(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 2 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv8i16.nxv2i8(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 2 x i8>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg2_nxv8i16_nxv2i8(<vscale x 8 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv8i16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv1r.v v25, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv8i16.nxv2i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv8i16_nxv2i8(<vscale x 8 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv8i16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv1r.v v25, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv8i16.nxv2i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv8i16.nxv8i32(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 8 x i32>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv8i16.nxv8i32(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 8 x i32>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg2_nxv8i16_nxv8i32(<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv8i16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv8i16.nxv8i32(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv8i16_nxv8i32(<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv8i16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv8i16.nxv8i32(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv8i16.nxv32i8(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 32 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv8i16.nxv32i8(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 32 x i8>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg2_nxv8i16_nxv32i8(<vscale x 8 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv8i16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv8i16.nxv32i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv8i16_nxv32i8(<vscale x 8 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv8i16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv8i16.nxv32i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv8i16.nxv16i32(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 16 x i32>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv8i16.nxv16i32(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 16 x i32>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg2_nxv8i16_nxv16i32(<vscale x 8 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv8i16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv8i16.nxv16i32(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv8i16_nxv16i32(<vscale x 8 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv8i16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv8i16.nxv16i32(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv8i16.nxv2i16(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 2 x i16>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv8i16.nxv2i16(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 2 x i16>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg2_nxv8i16_nxv2i16(<vscale x 8 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv8i16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv1r.v v25, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv8i16.nxv2i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv8i16_nxv2i16(<vscale x 8 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv8i16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv1r.v v25, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv8i16.nxv2i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv8i16.nxv2i64(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 2 x i64>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv8i16.nxv2i64(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 2 x i64>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg2_nxv8i16_nxv2i64(<vscale x 8 x i16> %val, i16* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv8i16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv2r.v v26, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v26
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv8i16.nxv2i64(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 2 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv8i16_nxv2i64(<vscale x 8 x i16> %val, i16* %base, <vscale x 2 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv8i16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv2r.v v26, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v26, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv8i16.nxv2i64(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 2 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv8i16.nxv16i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 16 x i16>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv8i16.nxv16i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 16 x i16>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg3_nxv8i16_nxv16i16(<vscale x 8 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv8i16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv8i16.nxv16i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv8i16_nxv16i16(<vscale x 8 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv8i16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v2, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv8i16.nxv16i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv8i16.nxv32i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 32 x i16>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv8i16.nxv32i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 32 x i16>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg3_nxv8i16_nxv32i16(<vscale x 8 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv8i16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vmv2r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv8i16.nxv32i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv8i16_nxv32i16(<vscale x 8 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv8i16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vmv2r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv8i16.nxv32i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv8i16.nxv4i32(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 4 x i32>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv8i16.nxv4i32(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 4 x i32>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg3_nxv8i16_nxv4i32(<vscale x 8 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv8i16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv8i16.nxv4i32(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv8i16_nxv4i32(<vscale x 8 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv8i16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv8i16.nxv4i32(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv8i16.nxv16i8(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 16 x i8>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv8i16.nxv16i8(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 16 x i8>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg3_nxv8i16_nxv16i8(<vscale x 8 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv8i16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv8i16.nxv16i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv8i16_nxv16i8(<vscale x 8 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv8i16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv8i16.nxv16i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv8i16.nxv1i64(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv8i16.nxv1i64(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 1 x i64>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg3_nxv8i16_nxv1i64(<vscale x 8 x i16> %val, i16* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv8i16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei64.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv8i16.nxv1i64(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 1 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv8i16_nxv1i64(<vscale x 8 x i16> %val, i16* %base, <vscale x 1 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv8i16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei64.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv8i16.nxv1i64(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 1 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv8i16.nxv1i32(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv8i16.nxv1i32(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 1 x i32>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg3_nxv8i16_nxv1i32(<vscale x 8 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv8i16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv8i16.nxv1i32(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv8i16_nxv1i32(<vscale x 8 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv8i16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv8i16.nxv1i32(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv8i16.nxv8i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 8 x i16>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv8i16.nxv8i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 8 x i16>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg3_nxv8i16_nxv8i16(<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv8i16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv8i16.nxv8i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv8i16_nxv8i16(<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv8i16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv8i16.nxv8i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv8i16.nxv4i8(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 4 x i8>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv8i16.nxv4i8(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 4 x i8>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg3_nxv8i16_nxv4i8(<vscale x 8 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv8i16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv8i16.nxv4i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv8i16_nxv4i8(<vscale x 8 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv8i16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv8i16.nxv4i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv8i16.nxv1i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv8i16.nxv1i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 1 x i16>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg3_nxv8i16_nxv1i16(<vscale x 8 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv8i16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv8i16.nxv1i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv8i16_nxv1i16(<vscale x 8 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv8i16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv8i16.nxv1i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv8i16.nxv2i32(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 2 x i32>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv8i16.nxv2i32(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 2 x i32>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg3_nxv8i16_nxv2i32(<vscale x 8 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv8i16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv8i16.nxv2i32(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv8i16_nxv2i32(<vscale x 8 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv8i16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv8i16.nxv2i32(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv8i16.nxv8i8(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 8 x i8>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv8i16.nxv8i8(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 8 x i8>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg3_nxv8i16_nxv8i8(<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv8i16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv8i16.nxv8i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv8i16_nxv8i8(<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv8i16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv8i16.nxv8i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv8i16.nxv4i64(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 4 x i64>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv8i16.nxv4i64(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 4 x i64>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg3_nxv8i16_nxv4i64(<vscale x 8 x i16> %val, i16* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv8i16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei64.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv8i16.nxv4i64(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 4 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv8i16_nxv4i64(<vscale x 8 x i16> %val, i16* %base, <vscale x 4 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv8i16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei64.v v2, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv8i16.nxv4i64(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 4 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv8i16.nxv64i8(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 64 x i8>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv8i16.nxv64i8(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 64 x i8>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg3_nxv8i16_nxv64i8(<vscale x 8 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv8i16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vmv2r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv8i16.nxv64i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv8i16_nxv64i8(<vscale x 8 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv8i16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vmv2r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv8i16.nxv64i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv8i16.nxv4i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 4 x i16>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv8i16.nxv4i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 4 x i16>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg3_nxv8i16_nxv4i16(<vscale x 8 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv8i16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv8i16.nxv4i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv8i16_nxv4i16(<vscale x 8 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv8i16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv8i16.nxv4i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv8i16.nxv8i64(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 8 x i64>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv8i16.nxv8i64(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 8 x i64>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg3_nxv8i16_nxv8i64(<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv8i16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vmv2r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei64.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv8i16.nxv8i64(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv8i16_nxv8i64(<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv8i16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vmv2r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei64.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv8i16.nxv8i64(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv8i16.nxv1i8(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv8i16.nxv1i8(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 1 x i8>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg3_nxv8i16_nxv1i8(<vscale x 8 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv8i16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv8i16.nxv1i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv8i16_nxv1i8(<vscale x 8 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv8i16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv8i16.nxv1i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv8i16.nxv2i8(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 2 x i8>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv8i16.nxv2i8(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 2 x i8>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg3_nxv8i16_nxv2i8(<vscale x 8 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv8i16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv8i16.nxv2i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv8i16_nxv2i8(<vscale x 8 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv8i16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv8i16.nxv2i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv8i16.nxv8i32(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 8 x i32>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv8i16.nxv8i32(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 8 x i32>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg3_nxv8i16_nxv8i32(<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv8i16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv8i16.nxv8i32(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv8i16_nxv8i32(<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv8i16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v2, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv8i16.nxv8i32(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv8i16.nxv32i8(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 32 x i8>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv8i16.nxv32i8(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 32 x i8>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg3_nxv8i16_nxv32i8(<vscale x 8 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv8i16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv8i16.nxv32i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv8i16_nxv32i8(<vscale x 8 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv8i16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v2, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv8i16.nxv32i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv8i16.nxv16i32(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 16 x i32>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv8i16.nxv16i32(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 16 x i32>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg3_nxv8i16_nxv16i32(<vscale x 8 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv8i16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vmv2r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv8i16.nxv16i32(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv8i16_nxv16i32(<vscale x 8 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv8i16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vmv2r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv8i16.nxv16i32(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv8i16.nxv2i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 2 x i16>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv8i16.nxv2i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 2 x i16>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg3_nxv8i16_nxv2i16(<vscale x 8 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv8i16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv8i16.nxv2i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv8i16_nxv2i16(<vscale x 8 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv8i16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv8i16.nxv2i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv8i16.nxv2i64(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 2 x i64>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv8i16.nxv2i64(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 2 x i64>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg3_nxv8i16_nxv2i64(<vscale x 8 x i16> %val, i16* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv8i16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei64.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv8i16.nxv2i64(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 2 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv8i16_nxv2i64(<vscale x 8 x i16> %val, i16* %base, <vscale x 2 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv8i16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei64.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv8i16.nxv2i64(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 2 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv8i16.nxv16i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 16 x i16>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv8i16.nxv16i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 16 x i16>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg4_nxv8i16_nxv16i16(<vscale x 8 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv8i16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vmv2r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv8i16.nxv16i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv8i16_nxv16i16(<vscale x 8 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv8i16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v2, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv8i16.nxv16i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv8i16.nxv32i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 32 x i16>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv8i16.nxv32i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 32 x i16>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg4_nxv8i16_nxv32i16(<vscale x 8 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv8i16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2_v22m2
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vmv2r.v v20, v16
+; CHECK-NEXT:    vmv2r.v v22, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv8i16.nxv32i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv8i16_nxv32i16(<vscale x 8 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv8i16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2_v22m2
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vmv2r.v v20, v16
+; CHECK-NEXT:    vmv2r.v v22, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv8i16.nxv32i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv8i16.nxv4i32(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 4 x i32>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv8i16.nxv4i32(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 4 x i32>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg4_nxv8i16_nxv4i32(<vscale x 8 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv8i16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vmv2r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv8i16.nxv4i32(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv8i16_nxv4i32(<vscale x 8 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv8i16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv8i16.nxv4i32(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv8i16.nxv16i8(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 16 x i8>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv8i16.nxv16i8(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 16 x i8>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg4_nxv8i16_nxv16i8(<vscale x 8 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv8i16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vmv2r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv8i16.nxv16i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv8i16_nxv16i8(<vscale x 8 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv8i16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv8i16.nxv16i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv8i16.nxv1i64(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv8i16.nxv1i64(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 1 x i64>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg4_nxv8i16_nxv1i64(<vscale x 8 x i16> %val, i16* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv8i16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vmv2r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei64.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv8i16.nxv1i64(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 1 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv8i16_nxv1i64(<vscale x 8 x i16> %val, i16* %base, <vscale x 1 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv8i16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei64.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv8i16.nxv1i64(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 1 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv8i16.nxv1i32(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv8i16.nxv1i32(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 1 x i32>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg4_nxv8i16_nxv1i32(<vscale x 8 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv8i16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vmv2r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv8i16.nxv1i32(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv8i16_nxv1i32(<vscale x 8 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv8i16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv8i16.nxv1i32(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv8i16.nxv8i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 8 x i16>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv8i16.nxv8i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 8 x i16>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg4_nxv8i16_nxv8i16(<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv8i16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vmv2r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv8i16.nxv8i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv8i16_nxv8i16(<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv8i16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv8i16.nxv8i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv8i16.nxv4i8(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 4 x i8>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv8i16.nxv4i8(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 4 x i8>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg4_nxv8i16_nxv4i8(<vscale x 8 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv8i16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vmv2r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv8i16.nxv4i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv8i16_nxv4i8(<vscale x 8 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv8i16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv8i16.nxv4i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv8i16.nxv1i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv8i16.nxv1i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 1 x i16>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg4_nxv8i16_nxv1i16(<vscale x 8 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv8i16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vmv2r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv8i16.nxv1i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv8i16_nxv1i16(<vscale x 8 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv8i16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv8i16.nxv1i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv8i16.nxv2i32(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 2 x i32>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv8i16.nxv2i32(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 2 x i32>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg4_nxv8i16_nxv2i32(<vscale x 8 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv8i16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vmv2r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv8i16.nxv2i32(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv8i16_nxv2i32(<vscale x 8 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv8i16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv8i16.nxv2i32(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv8i16.nxv8i8(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 8 x i8>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv8i16.nxv8i8(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 8 x i8>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg4_nxv8i16_nxv8i8(<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv8i16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vmv2r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv8i16.nxv8i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv8i16_nxv8i8(<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv8i16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv8i16.nxv8i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv8i16.nxv4i64(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 4 x i64>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv8i16.nxv4i64(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 4 x i64>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg4_nxv8i16_nxv4i64(<vscale x 8 x i16> %val, i16* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv8i16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vmv2r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei64.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv8i16.nxv4i64(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 4 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv8i16_nxv4i64(<vscale x 8 x i16> %val, i16* %base, <vscale x 4 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv8i16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei64.v v2, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv8i16.nxv4i64(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 4 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv8i16.nxv64i8(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 64 x i8>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv8i16.nxv64i8(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 64 x i8>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg4_nxv8i16_nxv64i8(<vscale x 8 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv8i16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2_v22m2
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vmv2r.v v20, v16
+; CHECK-NEXT:    vmv2r.v v22, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv8i16.nxv64i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv8i16_nxv64i8(<vscale x 8 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv8i16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2_v22m2
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vmv2r.v v20, v16
+; CHECK-NEXT:    vmv2r.v v22, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv8i16.nxv64i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv8i16.nxv4i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 4 x i16>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv8i16.nxv4i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 4 x i16>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg4_nxv8i16_nxv4i16(<vscale x 8 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv8i16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vmv2r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv8i16.nxv4i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv8i16_nxv4i16(<vscale x 8 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv8i16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv8i16.nxv4i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv8i16.nxv8i64(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 8 x i64>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv8i16.nxv8i64(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 8 x i64>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg4_nxv8i16_nxv8i64(<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv8i16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2_v22m2
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vmv2r.v v20, v16
+; CHECK-NEXT:    vmv2r.v v22, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei64.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv8i16.nxv8i64(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv8i16_nxv8i64(<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv8i16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2_v22m2
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vmv2r.v v20, v16
+; CHECK-NEXT:    vmv2r.v v22, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei64.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv8i16.nxv8i64(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv8i16.nxv1i8(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv8i16.nxv1i8(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 1 x i8>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg4_nxv8i16_nxv1i8(<vscale x 8 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv8i16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vmv2r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv8i16.nxv1i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv8i16_nxv1i8(<vscale x 8 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv8i16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv8i16.nxv1i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv8i16.nxv2i8(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 2 x i8>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv8i16.nxv2i8(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 2 x i8>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg4_nxv8i16_nxv2i8(<vscale x 8 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv8i16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vmv2r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv8i16.nxv2i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv8i16_nxv2i8(<vscale x 8 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv8i16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv8i16.nxv2i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv8i16.nxv8i32(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 8 x i32>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv8i16.nxv8i32(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 8 x i32>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg4_nxv8i16_nxv8i32(<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv8i16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vmv2r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv8i16.nxv8i32(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv8i16_nxv8i32(<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv8i16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v2, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv8i16.nxv8i32(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv8i16.nxv32i8(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 32 x i8>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv8i16.nxv32i8(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 32 x i8>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg4_nxv8i16_nxv32i8(<vscale x 8 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv8i16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vmv2r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv8i16.nxv32i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv8i16_nxv32i8(<vscale x 8 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv8i16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v2, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv8i16.nxv32i8(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv8i16.nxv16i32(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 16 x i32>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv8i16.nxv16i32(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 16 x i32>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg4_nxv8i16_nxv16i32(<vscale x 8 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv8i16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2_v22m2
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vmv2r.v v20, v16
+; CHECK-NEXT:    vmv2r.v v22, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv8i16.nxv16i32(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv8i16_nxv16i32(<vscale x 8 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv8i16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2_v22m2
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vmv2r.v v20, v16
+; CHECK-NEXT:    vmv2r.v v22, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv8i16.nxv16i32(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv8i16.nxv2i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 2 x i16>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv8i16.nxv2i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 2 x i16>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg4_nxv8i16_nxv2i16(<vscale x 8 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv8i16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vmv2r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv8i16.nxv2i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv8i16_nxv2i16(<vscale x 8 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv8i16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv8i16.nxv2i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv8i16.nxv2i64(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 2 x i64>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv8i16.nxv2i64(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 2 x i64>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg4_nxv8i16_nxv2i64(<vscale x 8 x i16> %val, i16* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv8i16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vmv2r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei64.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv8i16.nxv2i64(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 2 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv8i16_nxv2i64(<vscale x 8 x i16> %val, i16* %base, <vscale x 2 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv8i16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei64.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv8i16.nxv2i64(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 2 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv4i8.nxv16i16(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i16>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv4i8.nxv16i16(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i16>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg2_nxv4i8_nxv16i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv4i8_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv4i8.nxv16i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv4i8_nxv16i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv4i8_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv4i8.nxv16i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv4i8.nxv32i16(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 32 x i16>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv4i8.nxv32i16(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 32 x i16>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg2_nxv4i8_nxv32i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv4i8_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv4i8.nxv32i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv4i8_nxv32i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv4i8_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv4i8.nxv32i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv4i8.nxv4i32(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i32>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv4i8.nxv4i32(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i32>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg2_nxv4i8_nxv4i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv4i8_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv4i8.nxv4i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv4i8_nxv4i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv4i8_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv4i8.nxv4i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv4i8.nxv16i8(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv4i8.nxv16i8(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg2_nxv4i8_nxv16i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv4i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv4i8.nxv16i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv4i8_nxv16i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv4i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv4i8.nxv16i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv4i8.nxv1i64(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv4i8.nxv1i64(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i64>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg2_nxv4i8_nxv1i64(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv4i8_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv4i8.nxv1i64(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv4i8_nxv1i64(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv4i8_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv4i8.nxv1i64(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv4i8.nxv1i32(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv4i8.nxv1i32(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i32>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg2_nxv4i8_nxv1i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv4i8_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv4i8.nxv1i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv4i8_nxv1i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv4i8_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv4i8.nxv1i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv4i8.nxv8i16(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i16>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv4i8.nxv8i16(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i16>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg2_nxv4i8_nxv8i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv4i8_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv4i8.nxv8i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv4i8_nxv8i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv4i8_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv4i8.nxv8i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv4i8.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv4i8.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg2_nxv4i8_nxv4i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv4i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv4i8.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv4i8_nxv4i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv4i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv4i8.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv4i8.nxv1i16(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv4i8.nxv1i16(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i16>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg2_nxv4i8_nxv1i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv4i8_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv4i8.nxv1i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv4i8_nxv1i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv4i8_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv4i8.nxv1i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv4i8.nxv2i32(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i32>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv4i8.nxv2i32(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i32>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg2_nxv4i8_nxv2i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv4i8_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv4i8.nxv2i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv4i8_nxv2i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv4i8_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv4i8.nxv2i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv4i8.nxv8i8(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv4i8.nxv8i8(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg2_nxv4i8_nxv8i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv4i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv4i8.nxv8i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv4i8_nxv8i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv4i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv4i8.nxv8i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv4i8.nxv4i64(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i64>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv4i8.nxv4i64(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i64>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg2_nxv4i8_nxv4i64(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv4i8_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv4i8.nxv4i64(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv4i8_nxv4i64(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv4i8_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv4i8.nxv4i64(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv4i8.nxv64i8(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 64 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv4i8.nxv64i8(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 64 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg2_nxv4i8_nxv64i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv4i8_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv4i8.nxv64i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv4i8_nxv64i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv4i8_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv4i8.nxv64i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv4i8.nxv4i16(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i16>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv4i8.nxv4i16(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i16>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg2_nxv4i8_nxv4i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv4i8_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv4i8.nxv4i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv4i8_nxv4i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv4i8_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv4i8.nxv4i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv4i8.nxv8i64(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i64>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv4i8.nxv8i64(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i64>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg2_nxv4i8_nxv8i64(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv4i8_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv4i8.nxv8i64(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv4i8_nxv8i64(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv4i8_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv4i8.nxv8i64(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv4i8.nxv1i8(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv4i8.nxv1i8(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg2_nxv4i8_nxv1i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv4i8_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv4i8.nxv1i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv4i8_nxv1i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv4i8_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv4i8.nxv1i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv4i8.nxv2i8(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv4i8.nxv2i8(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg2_nxv4i8_nxv2i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv4i8_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv4i8.nxv2i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv4i8_nxv2i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv4i8_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv4i8.nxv2i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv4i8.nxv8i32(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i32>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv4i8.nxv8i32(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i32>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg2_nxv4i8_nxv8i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv4i8_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv4i8.nxv8i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv4i8_nxv8i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv4i8_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv4i8.nxv8i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv4i8.nxv32i8(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 32 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv4i8.nxv32i8(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 32 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg2_nxv4i8_nxv32i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv4i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv4i8.nxv32i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv4i8_nxv32i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv4i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv4i8.nxv32i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv4i8.nxv16i32(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i32>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv4i8.nxv16i32(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i32>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg2_nxv4i8_nxv16i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv4i8_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv4i8.nxv16i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv4i8_nxv16i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv4i8_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv4i8.nxv16i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv4i8.nxv2i16(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i16>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv4i8.nxv2i16(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i16>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg2_nxv4i8_nxv2i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv4i8_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv4i8.nxv2i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv4i8_nxv2i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv4i8_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv4i8.nxv2i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv4i8.nxv2i64(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i64>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv4i8.nxv2i64(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i64>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg2_nxv4i8_nxv2i64(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv4i8_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv4i8.nxv2i64(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv4i8_nxv2i64(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv4i8_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv4i8.nxv2i64(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv4i8.nxv16i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i16>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv4i8.nxv16i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i16>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg3_nxv4i8_nxv16i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv4i8_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv4i8.nxv16i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv4i8_nxv16i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv4i8_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv4i8.nxv16i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv4i8.nxv32i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 32 x i16>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv4i8.nxv32i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 32 x i16>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg3_nxv4i8_nxv32i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv4i8_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv4i8.nxv32i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv4i8_nxv32i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv4i8_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv4i8.nxv32i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv4i8.nxv4i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i32>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv4i8.nxv4i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i32>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg3_nxv4i8_nxv4i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv4i8_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv4i8.nxv4i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv4i8_nxv4i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv4i8_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv4i8.nxv4i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv4i8.nxv16i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i8>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv4i8.nxv16i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg3_nxv4i8_nxv16i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv4i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv4i8.nxv16i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv4i8_nxv16i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv4i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv4i8.nxv16i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv4i8.nxv1i64(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv4i8.nxv1i64(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i64>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg3_nxv4i8_nxv1i64(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv4i8_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei64.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv4i8.nxv1i64(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv4i8_nxv1i64(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv4i8_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei64.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv4i8.nxv1i64(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv4i8.nxv1i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv4i8.nxv1i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i32>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg3_nxv4i8_nxv1i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv4i8_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv4i8.nxv1i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv4i8_nxv1i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv4i8_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv4i8.nxv1i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv4i8.nxv8i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i16>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv4i8.nxv8i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i16>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg3_nxv4i8_nxv8i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv4i8_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv4i8.nxv8i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv4i8_nxv8i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv4i8_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv4i8.nxv8i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv4i8.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i8>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv4i8.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg3_nxv4i8_nxv4i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv4i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv4i8.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv4i8_nxv4i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv4i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv4i8.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv4i8.nxv1i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv4i8.nxv1i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i16>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg3_nxv4i8_nxv1i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv4i8_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv4i8.nxv1i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv4i8_nxv1i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv4i8_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv4i8.nxv1i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv4i8.nxv2i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i32>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv4i8.nxv2i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i32>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg3_nxv4i8_nxv2i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv4i8_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv4i8.nxv2i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv4i8_nxv2i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv4i8_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv4i8.nxv2i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv4i8.nxv8i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i8>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv4i8.nxv8i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg3_nxv4i8_nxv8i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv4i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv4i8.nxv8i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv4i8_nxv8i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv4i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv4i8.nxv8i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv4i8.nxv4i64(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i64>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv4i8.nxv4i64(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i64>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg3_nxv4i8_nxv4i64(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv4i8_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei64.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv4i8.nxv4i64(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv4i8_nxv4i64(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv4i8_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei64.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv4i8.nxv4i64(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv4i8.nxv64i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 64 x i8>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv4i8.nxv64i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 64 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg3_nxv4i8_nxv64i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv4i8_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv4i8.nxv64i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv4i8_nxv64i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv4i8_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv4i8.nxv64i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv4i8.nxv4i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i16>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv4i8.nxv4i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i16>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg3_nxv4i8_nxv4i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv4i8_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv4i8.nxv4i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv4i8_nxv4i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv4i8_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv4i8.nxv4i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv4i8.nxv8i64(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i64>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv4i8.nxv8i64(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i64>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg3_nxv4i8_nxv8i64(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv4i8_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei64.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv4i8.nxv8i64(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv4i8_nxv8i64(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv4i8_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei64.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv4i8.nxv8i64(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv4i8.nxv1i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv4i8.nxv1i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg3_nxv4i8_nxv1i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv4i8_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv4i8.nxv1i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv4i8_nxv1i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv4i8_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv4i8.nxv1i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv4i8.nxv2i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i8>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv4i8.nxv2i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg3_nxv4i8_nxv2i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv4i8_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv4i8.nxv2i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv4i8_nxv2i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv4i8_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv4i8.nxv2i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv4i8.nxv8i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i32>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv4i8.nxv8i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i32>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg3_nxv4i8_nxv8i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv4i8_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv4i8.nxv8i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv4i8_nxv8i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv4i8_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv4i8.nxv8i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv4i8.nxv32i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 32 x i8>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv4i8.nxv32i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 32 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg3_nxv4i8_nxv32i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv4i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv4i8.nxv32i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv4i8_nxv32i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv4i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv4i8.nxv32i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv4i8.nxv16i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i32>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv4i8.nxv16i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i32>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg3_nxv4i8_nxv16i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv4i8_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv4i8.nxv16i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv4i8_nxv16i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv4i8_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv4i8.nxv16i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv4i8.nxv2i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i16>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv4i8.nxv2i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i16>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg3_nxv4i8_nxv2i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv4i8_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv4i8.nxv2i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv4i8_nxv2i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv4i8_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv4i8.nxv2i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv4i8.nxv2i64(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i64>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv4i8.nxv2i64(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i64>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg3_nxv4i8_nxv2i64(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv4i8_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei64.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv4i8.nxv2i64(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv4i8_nxv2i64(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv4i8_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei64.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv4i8.nxv2i64(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv4i8.nxv16i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i16>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv4i8.nxv16i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i16>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg4_nxv4i8_nxv16i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv4i8_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv4i8.nxv16i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv4i8_nxv16i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv4i8_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv4i8.nxv16i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv4i8.nxv32i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 32 x i16>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv4i8.nxv32i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 32 x i16>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg4_nxv4i8_nxv32i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv4i8_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv4i8.nxv32i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv4i8_nxv32i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv4i8_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv4i8.nxv32i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv4i8.nxv4i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i32>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv4i8.nxv4i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i32>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg4_nxv4i8_nxv4i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv4i8_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv4i8.nxv4i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv4i8_nxv4i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv4i8_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv4i8.nxv4i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv4i8.nxv16i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i8>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv4i8.nxv16i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg4_nxv4i8_nxv16i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv4i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv4i8.nxv16i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv4i8_nxv16i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv4i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv4i8.nxv16i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv4i8.nxv1i64(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv4i8.nxv1i64(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i64>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg4_nxv4i8_nxv1i64(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv4i8_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei64.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv4i8.nxv1i64(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv4i8_nxv1i64(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv4i8_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei64.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv4i8.nxv1i64(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv4i8.nxv1i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv4i8.nxv1i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i32>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg4_nxv4i8_nxv1i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv4i8_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv4i8.nxv1i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv4i8_nxv1i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv4i8_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv4i8.nxv1i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv4i8.nxv8i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i16>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv4i8.nxv8i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i16>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg4_nxv4i8_nxv8i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv4i8_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv4i8.nxv8i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv4i8_nxv8i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv4i8_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv4i8.nxv8i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv4i8.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i8>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv4i8.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg4_nxv4i8_nxv4i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv4i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv4i8.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv4i8_nxv4i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv4i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv4i8.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv4i8.nxv1i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv4i8.nxv1i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i16>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg4_nxv4i8_nxv1i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv4i8_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv4i8.nxv1i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv4i8_nxv1i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv4i8_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv4i8.nxv1i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv4i8.nxv2i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i32>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv4i8.nxv2i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i32>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg4_nxv4i8_nxv2i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv4i8_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv4i8.nxv2i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv4i8_nxv2i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv4i8_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv4i8.nxv2i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv4i8.nxv8i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i8>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv4i8.nxv8i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg4_nxv4i8_nxv8i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv4i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv4i8.nxv8i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv4i8_nxv8i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv4i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv4i8.nxv8i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv4i8.nxv4i64(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i64>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv4i8.nxv4i64(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i64>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg4_nxv4i8_nxv4i64(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv4i8_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei64.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv4i8.nxv4i64(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv4i8_nxv4i64(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv4i8_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei64.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv4i8.nxv4i64(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv4i8.nxv64i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 64 x i8>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv4i8.nxv64i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 64 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg4_nxv4i8_nxv64i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv4i8_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv4i8.nxv64i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv4i8_nxv64i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv4i8_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv4i8.nxv64i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv4i8.nxv4i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i16>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv4i8.nxv4i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i16>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg4_nxv4i8_nxv4i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv4i8_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv4i8.nxv4i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv4i8_nxv4i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv4i8_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv4i8.nxv4i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv4i8.nxv8i64(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i64>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv4i8.nxv8i64(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i64>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg4_nxv4i8_nxv8i64(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv4i8_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei64.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv4i8.nxv8i64(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv4i8_nxv8i64(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv4i8_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei64.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv4i8.nxv8i64(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv4i8.nxv1i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv4i8.nxv1i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg4_nxv4i8_nxv1i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv4i8_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv4i8.nxv1i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv4i8_nxv1i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv4i8_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv4i8.nxv1i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv4i8.nxv2i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i8>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv4i8.nxv2i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg4_nxv4i8_nxv2i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv4i8_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv4i8.nxv2i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv4i8_nxv2i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv4i8_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv4i8.nxv2i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv4i8.nxv8i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i32>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv4i8.nxv8i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i32>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg4_nxv4i8_nxv8i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv4i8_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv4i8.nxv8i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv4i8_nxv8i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv4i8_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv4i8.nxv8i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv4i8.nxv32i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 32 x i8>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv4i8.nxv32i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 32 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg4_nxv4i8_nxv32i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv4i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv4i8.nxv32i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv4i8_nxv32i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv4i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv4i8.nxv32i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv4i8.nxv16i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i32>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv4i8.nxv16i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i32>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg4_nxv4i8_nxv16i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv4i8_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv4i8.nxv16i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv4i8_nxv16i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv4i8_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv4i8.nxv16i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv4i8.nxv2i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i16>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv4i8.nxv2i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i16>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg4_nxv4i8_nxv2i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv4i8_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv4i8.nxv2i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv4i8_nxv2i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv4i8_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv4i8.nxv2i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv4i8.nxv2i64(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i64>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv4i8.nxv2i64(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i64>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg4_nxv4i8_nxv2i64(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv4i8_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei64.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv4i8.nxv2i64(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv4i8_nxv2i64(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv4i8_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei64.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv4i8.nxv2i64(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv4i8.nxv16i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i16>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv4i8.nxv16i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i16>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg5_nxv4i8_nxv16i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv4i8_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv4i8.nxv16i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv4i8_nxv16i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv4i8_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv4i8.nxv16i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv4i8.nxv32i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 32 x i16>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv4i8.nxv32i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 32 x i16>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg5_nxv4i8_nxv32i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv4i8_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv4i8.nxv32i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv4i8_nxv32i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv4i8_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv4i8.nxv32i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv4i8.nxv4i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i32>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv4i8.nxv4i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i32>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg5_nxv4i8_nxv4i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv4i8_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei32.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv4i8.nxv4i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv4i8_nxv4i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv4i8_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei32.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv4i8.nxv4i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv4i8.nxv16i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i8>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv4i8.nxv16i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg5_nxv4i8_nxv16i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv4i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv4i8.nxv16i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv4i8_nxv16i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv4i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv4i8.nxv16i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv4i8.nxv1i64(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv4i8.nxv1i64(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i64>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg5_nxv4i8_nxv1i64(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv4i8_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei64.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv4i8.nxv1i64(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv4i8_nxv1i64(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv4i8_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei64.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv4i8.nxv1i64(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv4i8.nxv1i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv4i8.nxv1i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i32>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg5_nxv4i8_nxv1i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv4i8_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv4i8.nxv1i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv4i8_nxv1i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv4i8_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv4i8.nxv1i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv4i8.nxv8i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i16>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv4i8.nxv8i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i16>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg5_nxv4i8_nxv8i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv4i8_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv4i8.nxv8i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv4i8_nxv8i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv4i8_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv4i8.nxv8i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv4i8.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i8>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv4i8.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg5_nxv4i8_nxv4i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv4i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv4i8.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv4i8_nxv4i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv4i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv4i8.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv4i8.nxv1i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv4i8.nxv1i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i16>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg5_nxv4i8_nxv1i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv4i8_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv4i8.nxv1i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv4i8_nxv1i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv4i8_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv4i8.nxv1i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv4i8.nxv2i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i32>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv4i8.nxv2i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i32>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg5_nxv4i8_nxv2i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv4i8_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv4i8.nxv2i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv4i8_nxv2i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv4i8_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv4i8.nxv2i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv4i8.nxv8i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i8>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv4i8.nxv8i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg5_nxv4i8_nxv8i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv4i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv4i8.nxv8i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv4i8_nxv8i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv4i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv4i8.nxv8i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv4i8.nxv4i64(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i64>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv4i8.nxv4i64(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i64>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg5_nxv4i8_nxv4i64(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv4i8_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei64.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv4i8.nxv4i64(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv4i8_nxv4i64(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv4i8_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei64.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv4i8.nxv4i64(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv4i8.nxv64i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 64 x i8>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv4i8.nxv64i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 64 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg5_nxv4i8_nxv64i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv4i8_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv4i8.nxv64i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv4i8_nxv64i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv4i8_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv4i8.nxv64i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv4i8.nxv4i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i16>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv4i8.nxv4i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i16>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg5_nxv4i8_nxv4i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv4i8_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv4i8.nxv4i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv4i8_nxv4i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv4i8_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv4i8.nxv4i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv4i8.nxv8i64(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i64>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv4i8.nxv8i64(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i64>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg5_nxv4i8_nxv8i64(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv4i8_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei64.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv4i8.nxv8i64(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv4i8_nxv8i64(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv4i8_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei64.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv4i8.nxv8i64(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv4i8.nxv1i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv4i8.nxv1i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg5_nxv4i8_nxv1i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv4i8_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv4i8.nxv1i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv4i8_nxv1i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv4i8_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv4i8.nxv1i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv4i8.nxv2i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i8>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv4i8.nxv2i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg5_nxv4i8_nxv2i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv4i8_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv4i8.nxv2i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv4i8_nxv2i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv4i8_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv4i8.nxv2i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv4i8.nxv8i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i32>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv4i8.nxv8i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i32>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg5_nxv4i8_nxv8i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv4i8_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei32.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv4i8.nxv8i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv4i8_nxv8i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv4i8_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei32.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv4i8.nxv8i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv4i8.nxv32i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 32 x i8>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv4i8.nxv32i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 32 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg5_nxv4i8_nxv32i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv4i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv4i8.nxv32i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv4i8_nxv32i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv4i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv4i8.nxv32i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv4i8.nxv16i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i32>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv4i8.nxv16i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i32>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg5_nxv4i8_nxv16i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv4i8_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei32.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv4i8.nxv16i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv4i8_nxv16i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv4i8_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei32.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv4i8.nxv16i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv4i8.nxv2i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i16>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv4i8.nxv2i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i16>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg5_nxv4i8_nxv2i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv4i8_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv4i8.nxv2i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv4i8_nxv2i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv4i8_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv4i8.nxv2i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv4i8.nxv2i64(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i64>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv4i8.nxv2i64(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i64>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg5_nxv4i8_nxv2i64(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv4i8_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei64.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv4i8.nxv2i64(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv4i8_nxv2i64(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv4i8_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei64.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv4i8.nxv2i64(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv4i8.nxv16i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i16>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv4i8.nxv16i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i16>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg6_nxv4i8_nxv16i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv4i8_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv4i8.nxv16i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv4i8_nxv16i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv4i8_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv4i8.nxv16i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv4i8.nxv32i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 32 x i16>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv4i8.nxv32i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 32 x i16>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg6_nxv4i8_nxv32i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv4i8_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv4i8.nxv32i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv4i8_nxv32i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv4i8_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv4i8.nxv32i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv4i8.nxv4i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i32>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv4i8.nxv4i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i32>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg6_nxv4i8_nxv4i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv4i8_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei32.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv4i8.nxv4i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv4i8_nxv4i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv4i8_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei32.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv4i8.nxv4i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv4i8.nxv16i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i8>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv4i8.nxv16i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg6_nxv4i8_nxv16i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv4i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv4i8.nxv16i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv4i8_nxv16i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv4i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv4i8.nxv16i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv4i8.nxv1i64(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv4i8.nxv1i64(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i64>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg6_nxv4i8_nxv1i64(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv4i8_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei64.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv4i8.nxv1i64(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv4i8_nxv1i64(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv4i8_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei64.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv4i8.nxv1i64(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv4i8.nxv1i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv4i8.nxv1i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i32>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg6_nxv4i8_nxv1i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv4i8_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv4i8.nxv1i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv4i8_nxv1i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv4i8_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv4i8.nxv1i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv4i8.nxv8i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i16>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv4i8.nxv8i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i16>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg6_nxv4i8_nxv8i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv4i8_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv4i8.nxv8i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv4i8_nxv8i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv4i8_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv4i8.nxv8i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv4i8.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i8>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv4i8.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg6_nxv4i8_nxv4i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv4i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv4i8.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv4i8_nxv4i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv4i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv4i8.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv4i8.nxv1i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv4i8.nxv1i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i16>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg6_nxv4i8_nxv1i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv4i8_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv4i8.nxv1i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv4i8_nxv1i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv4i8_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv4i8.nxv1i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv4i8.nxv2i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i32>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv4i8.nxv2i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i32>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg6_nxv4i8_nxv2i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv4i8_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv4i8.nxv2i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv4i8_nxv2i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv4i8_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv4i8.nxv2i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv4i8.nxv8i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i8>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv4i8.nxv8i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg6_nxv4i8_nxv8i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv4i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv4i8.nxv8i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv4i8_nxv8i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv4i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv4i8.nxv8i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv4i8.nxv4i64(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i64>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv4i8.nxv4i64(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i64>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg6_nxv4i8_nxv4i64(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv4i8_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei64.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv4i8.nxv4i64(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv4i8_nxv4i64(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv4i8_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei64.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv4i8.nxv4i64(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv4i8.nxv64i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 64 x i8>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv4i8.nxv64i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 64 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg6_nxv4i8_nxv64i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv4i8_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv4i8.nxv64i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv4i8_nxv64i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv4i8_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv4i8.nxv64i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv4i8.nxv4i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i16>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv4i8.nxv4i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i16>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg6_nxv4i8_nxv4i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv4i8_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv4i8.nxv4i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv4i8_nxv4i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv4i8_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv4i8.nxv4i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv4i8.nxv8i64(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i64>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv4i8.nxv8i64(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i64>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg6_nxv4i8_nxv8i64(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv4i8_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei64.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv4i8.nxv8i64(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv4i8_nxv8i64(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv4i8_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei64.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv4i8.nxv8i64(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv4i8.nxv1i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv4i8.nxv1i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg6_nxv4i8_nxv1i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv4i8_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv4i8.nxv1i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv4i8_nxv1i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv4i8_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv4i8.nxv1i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv4i8.nxv2i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i8>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv4i8.nxv2i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg6_nxv4i8_nxv2i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv4i8_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv4i8.nxv2i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv4i8_nxv2i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv4i8_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv4i8.nxv2i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv4i8.nxv8i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i32>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv4i8.nxv8i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i32>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg6_nxv4i8_nxv8i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv4i8_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei32.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv4i8.nxv8i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv4i8_nxv8i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv4i8_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei32.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv4i8.nxv8i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv4i8.nxv32i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 32 x i8>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv4i8.nxv32i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 32 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg6_nxv4i8_nxv32i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv4i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv4i8.nxv32i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv4i8_nxv32i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv4i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv4i8.nxv32i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv4i8.nxv16i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i32>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv4i8.nxv16i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i32>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg6_nxv4i8_nxv16i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv4i8_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei32.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv4i8.nxv16i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv4i8_nxv16i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv4i8_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei32.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv4i8.nxv16i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv4i8.nxv2i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i16>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv4i8.nxv2i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i16>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg6_nxv4i8_nxv2i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv4i8_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv4i8.nxv2i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv4i8_nxv2i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv4i8_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv4i8.nxv2i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv4i8.nxv2i64(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i64>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv4i8.nxv2i64(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i64>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg6_nxv4i8_nxv2i64(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv4i8_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei64.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv4i8.nxv2i64(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv4i8_nxv2i64(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv4i8_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei64.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv4i8.nxv2i64(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv4i8.nxv16i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i16>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv4i8.nxv16i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i16>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg7_nxv4i8_nxv16i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv4i8_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv4i8.nxv16i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv4i8_nxv16i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv4i8_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv4i8.nxv16i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv4i8.nxv32i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 32 x i16>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv4i8.nxv32i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 32 x i16>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg7_nxv4i8_nxv32i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv4i8_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv4i8.nxv32i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv4i8_nxv32i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv4i8_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv4i8.nxv32i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv4i8.nxv4i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i32>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv4i8.nxv4i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i32>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg7_nxv4i8_nxv4i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv4i8_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei32.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv4i8.nxv4i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv4i8_nxv4i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv4i8_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei32.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv4i8.nxv4i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv4i8.nxv16i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i8>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv4i8.nxv16i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg7_nxv4i8_nxv16i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv4i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv4i8.nxv16i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv4i8_nxv16i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv4i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv4i8.nxv16i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv4i8.nxv1i64(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv4i8.nxv1i64(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i64>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg7_nxv4i8_nxv1i64(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv4i8_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei64.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv4i8.nxv1i64(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv4i8_nxv1i64(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv4i8_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei64.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv4i8.nxv1i64(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv4i8.nxv1i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv4i8.nxv1i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i32>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg7_nxv4i8_nxv1i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv4i8_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv4i8.nxv1i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv4i8_nxv1i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv4i8_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv4i8.nxv1i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv4i8.nxv8i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i16>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv4i8.nxv8i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i16>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg7_nxv4i8_nxv8i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv4i8_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv4i8.nxv8i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv4i8_nxv8i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv4i8_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv4i8.nxv8i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv4i8.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i8>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv4i8.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg7_nxv4i8_nxv4i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv4i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv4i8.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv4i8_nxv4i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv4i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv4i8.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv4i8.nxv1i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv4i8.nxv1i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i16>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg7_nxv4i8_nxv1i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv4i8_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv4i8.nxv1i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv4i8_nxv1i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv4i8_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv4i8.nxv1i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv4i8.nxv2i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i32>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv4i8.nxv2i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i32>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg7_nxv4i8_nxv2i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv4i8_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv4i8.nxv2i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv4i8_nxv2i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv4i8_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv4i8.nxv2i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv4i8.nxv8i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i8>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv4i8.nxv8i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg7_nxv4i8_nxv8i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv4i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv4i8.nxv8i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv4i8_nxv8i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv4i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv4i8.nxv8i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv4i8.nxv4i64(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i64>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv4i8.nxv4i64(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i64>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg7_nxv4i8_nxv4i64(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv4i8_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei64.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv4i8.nxv4i64(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv4i8_nxv4i64(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv4i8_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei64.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv4i8.nxv4i64(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv4i8.nxv64i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 64 x i8>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv4i8.nxv64i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 64 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg7_nxv4i8_nxv64i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv4i8_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv4i8.nxv64i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv4i8_nxv64i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv4i8_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv4i8.nxv64i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv4i8.nxv4i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i16>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv4i8.nxv4i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i16>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg7_nxv4i8_nxv4i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv4i8_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv4i8.nxv4i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv4i8_nxv4i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv4i8_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv4i8.nxv4i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv4i8.nxv8i64(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i64>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv4i8.nxv8i64(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i64>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg7_nxv4i8_nxv8i64(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv4i8_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei64.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv4i8.nxv8i64(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv4i8_nxv8i64(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv4i8_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei64.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv4i8.nxv8i64(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv4i8.nxv1i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv4i8.nxv1i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg7_nxv4i8_nxv1i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv4i8_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv4i8.nxv1i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv4i8_nxv1i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv4i8_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv4i8.nxv1i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv4i8.nxv2i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i8>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv4i8.nxv2i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg7_nxv4i8_nxv2i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv4i8_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv4i8.nxv2i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv4i8_nxv2i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv4i8_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv4i8.nxv2i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv4i8.nxv8i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i32>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv4i8.nxv8i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i32>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg7_nxv4i8_nxv8i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv4i8_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei32.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv4i8.nxv8i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv4i8_nxv8i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv4i8_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei32.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv4i8.nxv8i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv4i8.nxv32i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 32 x i8>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv4i8.nxv32i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 32 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg7_nxv4i8_nxv32i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv4i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv4i8.nxv32i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv4i8_nxv32i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv4i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv4i8.nxv32i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv4i8.nxv16i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i32>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv4i8.nxv16i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i32>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg7_nxv4i8_nxv16i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv4i8_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei32.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv4i8.nxv16i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv4i8_nxv16i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv4i8_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei32.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv4i8.nxv16i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv4i8.nxv2i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i16>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv4i8.nxv2i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i16>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg7_nxv4i8_nxv2i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv4i8_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv4i8.nxv2i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv4i8_nxv2i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv4i8_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv4i8.nxv2i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv4i8.nxv2i64(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i64>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv4i8.nxv2i64(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i64>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg7_nxv4i8_nxv2i64(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv4i8_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei64.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv4i8.nxv2i64(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv4i8_nxv2i64(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv4i8_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei64.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv4i8.nxv2i64(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv4i8.nxv16i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i16>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv4i8.nxv16i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i16>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg8_nxv4i8_nxv16i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv4i8_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv4i8.nxv16i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv4i8_nxv16i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv4i8_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv4i8.nxv16i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv4i8.nxv32i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 32 x i16>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv4i8.nxv32i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 32 x i16>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg8_nxv4i8_nxv32i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv4i8_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vmv1r.v v23, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv4i8.nxv32i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv4i8_nxv32i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv4i8_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vmv1r.v v23, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv4i8.nxv32i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv4i8.nxv4i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i32>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv4i8.nxv4i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i32>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg8_nxv4i8_nxv4i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv4i8_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei32.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv4i8.nxv4i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv4i8_nxv4i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv4i8_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei32.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv4i8.nxv4i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv4i8.nxv16i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i8>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv4i8.nxv16i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg8_nxv4i8_nxv16i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv4i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv4i8.nxv16i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv4i8_nxv16i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv4i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv4i8.nxv16i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv4i8.nxv1i64(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv4i8.nxv1i64(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i64>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg8_nxv4i8_nxv1i64(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv4i8_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei64.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv4i8.nxv1i64(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv4i8_nxv1i64(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv4i8_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei64.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv4i8.nxv1i64(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv4i8.nxv1i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv4i8.nxv1i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i32>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg8_nxv4i8_nxv1i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv4i8_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv4i8.nxv1i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv4i8_nxv1i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv4i8_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv4i8.nxv1i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv4i8.nxv8i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i16>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv4i8.nxv8i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i16>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg8_nxv4i8_nxv8i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv4i8_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv4i8.nxv8i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv4i8_nxv8i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv4i8_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv4i8.nxv8i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv4i8.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i8>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv4i8.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg8_nxv4i8_nxv4i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv4i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv4i8.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv4i8_nxv4i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv4i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv4i8.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv4i8.nxv1i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv4i8.nxv1i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i16>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg8_nxv4i8_nxv1i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv4i8_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv4i8.nxv1i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv4i8_nxv1i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv4i8_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv4i8.nxv1i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv4i8.nxv2i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i32>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv4i8.nxv2i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i32>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg8_nxv4i8_nxv2i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv4i8_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv4i8.nxv2i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv4i8_nxv2i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv4i8_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv4i8.nxv2i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv4i8.nxv8i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i8>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv4i8.nxv8i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg8_nxv4i8_nxv8i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv4i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv4i8.nxv8i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv4i8_nxv8i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv4i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv4i8.nxv8i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv4i8.nxv4i64(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i64>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv4i8.nxv4i64(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i64>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg8_nxv4i8_nxv4i64(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv4i8_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei64.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv4i8.nxv4i64(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv4i8_nxv4i64(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv4i8_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei64.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv4i8.nxv4i64(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv4i8.nxv64i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 64 x i8>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv4i8.nxv64i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 64 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg8_nxv4i8_nxv64i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv4i8_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vmv1r.v v23, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv4i8.nxv64i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv4i8_nxv64i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv4i8_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vmv1r.v v23, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv4i8.nxv64i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv4i8.nxv4i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i16>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv4i8.nxv4i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i16>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg8_nxv4i8_nxv4i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv4i8_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv4i8.nxv4i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv4i8_nxv4i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv4i8_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv4i8.nxv4i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv4i8.nxv8i64(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i64>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv4i8.nxv8i64(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i64>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg8_nxv4i8_nxv8i64(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv4i8_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vmv1r.v v23, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei64.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv4i8.nxv8i64(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv4i8_nxv8i64(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv4i8_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vmv1r.v v23, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei64.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv4i8.nxv8i64(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv4i8.nxv1i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv4i8.nxv1i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 1 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg8_nxv4i8_nxv1i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv4i8_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv4i8.nxv1i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv4i8_nxv1i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv4i8_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv4i8.nxv1i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv4i8.nxv2i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i8>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv4i8.nxv2i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg8_nxv4i8_nxv2i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv4i8_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv4i8.nxv2i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv4i8_nxv2i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv4i8_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv4i8.nxv2i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv4i8.nxv8i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i32>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv4i8.nxv8i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 8 x i32>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg8_nxv4i8_nxv8i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv4i8_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei32.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv4i8.nxv8i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv4i8_nxv8i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv4i8_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei32.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv4i8.nxv8i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv4i8.nxv32i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 32 x i8>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv4i8.nxv32i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 32 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg8_nxv4i8_nxv32i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv4i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv4i8.nxv32i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv4i8_nxv32i8(<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv4i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv4i8.nxv32i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv4i8.nxv16i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i32>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv4i8.nxv16i32(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 16 x i32>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg8_nxv4i8_nxv16i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv4i8_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vmv1r.v v23, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei32.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv4i8.nxv16i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv4i8_nxv16i32(<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv4i8_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vmv1r.v v23, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei32.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv4i8.nxv16i32(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv4i8.nxv2i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i16>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv4i8.nxv2i16(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i16>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg8_nxv4i8_nxv2i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv4i8_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv4i8.nxv2i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv4i8_nxv2i16(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv4i8_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv4i8.nxv2i16(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv4i8.nxv2i64(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i64>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv4i8.nxv2i64(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 2 x i64>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg8_nxv4i8_nxv2i64(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv4i8_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei64.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv4i8.nxv2i64(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv4i8_nxv2i64(<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv4i8_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei64.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv4i8.nxv2i64(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 2 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv1i16.nxv16i16(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i16>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv1i16.nxv16i16(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg2_nxv1i16_nxv16i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv1i16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv1i16.nxv16i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv1i16_nxv16i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv1i16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv1i16.nxv16i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv1i16.nxv32i16(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 32 x i16>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv1i16.nxv32i16(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 32 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg2_nxv1i16_nxv32i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv1i16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv1i16.nxv32i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv1i16_nxv32i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv1i16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv1i16.nxv32i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv1i16.nxv4i32(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i32>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv1i16.nxv4i32(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg2_nxv1i16_nxv4i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv1i16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv1i16.nxv4i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv1i16_nxv4i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv1i16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv1i16.nxv4i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv1i16.nxv16i8(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv1i16.nxv16i8(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg2_nxv1i16_nxv16i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv1i16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv1i16.nxv16i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv1i16_nxv16i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv1i16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv1i16.nxv16i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv1i16.nxv1i64(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv1i16.nxv1i64(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg2_nxv1i16_nxv1i64(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv1i16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv1i16.nxv1i64(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv1i16_nxv1i64(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv1i16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv1i16.nxv1i64(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv1i16.nxv1i32(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv1i16.nxv1i32(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg2_nxv1i16_nxv1i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv1i16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv1i16.nxv1i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv1i16_nxv1i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv1i16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv1i16.nxv1i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv1i16.nxv8i16(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i16>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv1i16.nxv8i16(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg2_nxv1i16_nxv8i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv1i16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv1i16.nxv8i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv1i16_nxv8i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv1i16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv1i16.nxv8i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv1i16.nxv4i8(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv1i16.nxv4i8(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg2_nxv1i16_nxv4i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv1i16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv1i16.nxv4i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv1i16_nxv4i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv1i16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv1i16.nxv4i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv1i16.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv1i16.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg2_nxv1i16_nxv1i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv1i16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv1i16.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv1i16_nxv1i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv1i16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv1i16.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv1i16.nxv2i32(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i32>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv1i16.nxv2i32(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg2_nxv1i16_nxv2i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv1i16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv1i16.nxv2i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv1i16_nxv2i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv1i16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv1i16.nxv2i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv1i16.nxv8i8(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv1i16.nxv8i8(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg2_nxv1i16_nxv8i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv1i16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv1i16.nxv8i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv1i16_nxv8i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv1i16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv1i16.nxv8i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv1i16.nxv4i64(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i64>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv1i16.nxv4i64(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg2_nxv1i16_nxv4i64(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv1i16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv1i16.nxv4i64(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv1i16_nxv4i64(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv1i16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv1i16.nxv4i64(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv1i16.nxv64i8(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 64 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv1i16.nxv64i8(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 64 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg2_nxv1i16_nxv64i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv1i16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv1i16.nxv64i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv1i16_nxv64i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv1i16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv1i16.nxv64i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv1i16.nxv4i16(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i16>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv1i16.nxv4i16(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg2_nxv1i16_nxv4i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv1i16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv1i16.nxv4i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv1i16_nxv4i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv1i16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv1i16.nxv4i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv1i16.nxv8i64(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i64>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv1i16.nxv8i64(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg2_nxv1i16_nxv8i64(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv1i16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv1i16.nxv8i64(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv1i16_nxv8i64(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv1i16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv1i16.nxv8i64(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv1i16.nxv1i8(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv1i16.nxv1i8(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg2_nxv1i16_nxv1i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv1i16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv1i16.nxv1i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv1i16_nxv1i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv1i16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv1i16.nxv1i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv1i16.nxv2i8(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv1i16.nxv2i8(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg2_nxv1i16_nxv2i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv1i16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv1i16.nxv2i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv1i16_nxv2i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv1i16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv1i16.nxv2i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv1i16.nxv8i32(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i32>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv1i16.nxv8i32(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg2_nxv1i16_nxv8i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv1i16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv1i16.nxv8i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv1i16_nxv8i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv1i16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv1i16.nxv8i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv1i16.nxv32i8(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 32 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv1i16.nxv32i8(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 32 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg2_nxv1i16_nxv32i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv1i16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv1i16.nxv32i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv1i16_nxv32i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv1i16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv1i16.nxv32i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv1i16.nxv16i32(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i32>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv1i16.nxv16i32(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg2_nxv1i16_nxv16i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv1i16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv1i16.nxv16i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv1i16_nxv16i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv1i16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv1i16.nxv16i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv1i16.nxv2i16(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i16>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv1i16.nxv2i16(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg2_nxv1i16_nxv2i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv1i16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv1i16.nxv2i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv1i16_nxv2i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv1i16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv1i16.nxv2i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv1i16.nxv2i64(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i64>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv1i16.nxv2i64(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg2_nxv1i16_nxv2i64(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv1i16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv1i16.nxv2i64(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv1i16_nxv2i64(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv1i16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv1i16.nxv2i64(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv1i16.nxv16i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i16>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv1i16.nxv16i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg3_nxv1i16_nxv16i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv1i16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv1i16.nxv16i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv1i16_nxv16i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv1i16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv1i16.nxv16i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv1i16.nxv32i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 32 x i16>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv1i16.nxv32i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 32 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg3_nxv1i16_nxv32i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv1i16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv1i16.nxv32i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv1i16_nxv32i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv1i16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv1i16.nxv32i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv1i16.nxv4i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i32>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv1i16.nxv4i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg3_nxv1i16_nxv4i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv1i16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv1i16.nxv4i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv1i16_nxv4i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv1i16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv1i16.nxv4i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv1i16.nxv16i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i8>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv1i16.nxv16i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg3_nxv1i16_nxv16i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv1i16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv1i16.nxv16i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv1i16_nxv16i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv1i16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv1i16.nxv16i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv1i16.nxv1i64(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv1i16.nxv1i64(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg3_nxv1i16_nxv1i64(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv1i16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg3ei64.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv1i16.nxv1i64(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv1i16_nxv1i64(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv1i16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg3ei64.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv1i16.nxv1i64(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv1i16.nxv1i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv1i16.nxv1i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg3_nxv1i16_nxv1i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv1i16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv1i16.nxv1i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv1i16_nxv1i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv1i16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv1i16.nxv1i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv1i16.nxv8i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i16>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv1i16.nxv8i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg3_nxv1i16_nxv8i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv1i16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv1i16.nxv8i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv1i16_nxv8i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv1i16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv1i16.nxv8i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv1i16.nxv4i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i8>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv1i16.nxv4i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg3_nxv1i16_nxv4i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv1i16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv1i16.nxv4i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv1i16_nxv4i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv1i16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv1i16.nxv4i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv1i16.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv1i16.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg3_nxv1i16_nxv1i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv1i16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv1i16.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv1i16_nxv1i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv1i16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv1i16.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv1i16.nxv2i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i32>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv1i16.nxv2i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg3_nxv1i16_nxv2i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv1i16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv1i16.nxv2i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv1i16_nxv2i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv1i16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv1i16.nxv2i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv1i16.nxv8i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i8>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv1i16.nxv8i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg3_nxv1i16_nxv8i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv1i16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv1i16.nxv8i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv1i16_nxv8i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv1i16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv1i16.nxv8i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv1i16.nxv4i64(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i64>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv1i16.nxv4i64(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg3_nxv1i16_nxv4i64(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv1i16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg3ei64.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv1i16.nxv4i64(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv1i16_nxv4i64(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv1i16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg3ei64.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv1i16.nxv4i64(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv1i16.nxv64i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 64 x i8>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv1i16.nxv64i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 64 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg3_nxv1i16_nxv64i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv1i16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv1i16.nxv64i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv1i16_nxv64i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv1i16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv1i16.nxv64i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv1i16.nxv4i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i16>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv1i16.nxv4i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg3_nxv1i16_nxv4i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv1i16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv1i16.nxv4i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv1i16_nxv4i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv1i16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv1i16.nxv4i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv1i16.nxv8i64(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i64>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv1i16.nxv8i64(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg3_nxv1i16_nxv8i64(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv1i16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg3ei64.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv1i16.nxv8i64(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv1i16_nxv8i64(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv1i16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg3ei64.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv1i16.nxv8i64(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv1i16.nxv1i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv1i16.nxv1i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg3_nxv1i16_nxv1i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv1i16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv1i16.nxv1i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv1i16_nxv1i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv1i16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv1i16.nxv1i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv1i16.nxv2i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i8>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv1i16.nxv2i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg3_nxv1i16_nxv2i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv1i16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv1i16.nxv2i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv1i16_nxv2i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv1i16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv1i16.nxv2i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv1i16.nxv8i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i32>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv1i16.nxv8i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg3_nxv1i16_nxv8i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv1i16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv1i16.nxv8i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv1i16_nxv8i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv1i16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv1i16.nxv8i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv1i16.nxv32i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 32 x i8>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv1i16.nxv32i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 32 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg3_nxv1i16_nxv32i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv1i16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv1i16.nxv32i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv1i16_nxv32i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv1i16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv1i16.nxv32i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv1i16.nxv16i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i32>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv1i16.nxv16i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg3_nxv1i16_nxv16i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv1i16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv1i16.nxv16i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv1i16_nxv16i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv1i16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv1i16.nxv16i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv1i16.nxv2i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i16>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv1i16.nxv2i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg3_nxv1i16_nxv2i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv1i16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv1i16.nxv2i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv1i16_nxv2i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv1i16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv1i16.nxv2i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv1i16.nxv2i64(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i64>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv1i16.nxv2i64(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg3_nxv1i16_nxv2i64(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv1i16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg3ei64.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv1i16.nxv2i64(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv1i16_nxv2i64(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv1i16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg3ei64.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv1i16.nxv2i64(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv1i16.nxv16i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i16>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv1i16.nxv16i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg4_nxv1i16_nxv16i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv1i16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv1i16.nxv16i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv1i16_nxv16i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv1i16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv1i16.nxv16i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv1i16.nxv32i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 32 x i16>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv1i16.nxv32i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 32 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg4_nxv1i16_nxv32i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv1i16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv1i16.nxv32i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv1i16_nxv32i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv1i16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv1i16.nxv32i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv1i16.nxv4i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i32>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv1i16.nxv4i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg4_nxv1i16_nxv4i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv1i16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv1i16.nxv4i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv1i16_nxv4i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv1i16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv1i16.nxv4i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv1i16.nxv16i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i8>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv1i16.nxv16i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg4_nxv1i16_nxv16i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv1i16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv1i16.nxv16i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv1i16_nxv16i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv1i16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv1i16.nxv16i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv1i16.nxv1i64(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv1i16.nxv1i64(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg4_nxv1i16_nxv1i64(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv1i16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg4ei64.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv1i16.nxv1i64(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv1i16_nxv1i64(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv1i16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg4ei64.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv1i16.nxv1i64(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv1i16.nxv1i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv1i16.nxv1i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg4_nxv1i16_nxv1i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv1i16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv1i16.nxv1i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv1i16_nxv1i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv1i16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv1i16.nxv1i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv1i16.nxv8i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i16>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv1i16.nxv8i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg4_nxv1i16_nxv8i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv1i16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv1i16.nxv8i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv1i16_nxv8i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv1i16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv1i16.nxv8i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv1i16.nxv4i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i8>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv1i16.nxv4i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg4_nxv1i16_nxv4i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv1i16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv1i16.nxv4i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv1i16_nxv4i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv1i16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv1i16.nxv4i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv1i16.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv1i16.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg4_nxv1i16_nxv1i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv1i16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv1i16.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv1i16_nxv1i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv1i16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv1i16.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv1i16.nxv2i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i32>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv1i16.nxv2i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg4_nxv1i16_nxv2i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv1i16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv1i16.nxv2i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv1i16_nxv2i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv1i16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv1i16.nxv2i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv1i16.nxv8i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i8>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv1i16.nxv8i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg4_nxv1i16_nxv8i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv1i16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv1i16.nxv8i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv1i16_nxv8i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv1i16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv1i16.nxv8i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv1i16.nxv4i64(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i64>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv1i16.nxv4i64(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg4_nxv1i16_nxv4i64(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv1i16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg4ei64.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv1i16.nxv4i64(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv1i16_nxv4i64(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv1i16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg4ei64.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv1i16.nxv4i64(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv1i16.nxv64i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 64 x i8>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv1i16.nxv64i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 64 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg4_nxv1i16_nxv64i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv1i16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv1i16.nxv64i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv1i16_nxv64i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv1i16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv1i16.nxv64i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv1i16.nxv4i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i16>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv1i16.nxv4i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg4_nxv1i16_nxv4i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv1i16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv1i16.nxv4i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv1i16_nxv4i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv1i16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv1i16.nxv4i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv1i16.nxv8i64(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i64>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv1i16.nxv8i64(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg4_nxv1i16_nxv8i64(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv1i16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg4ei64.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv1i16.nxv8i64(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv1i16_nxv8i64(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv1i16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg4ei64.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv1i16.nxv8i64(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv1i16.nxv1i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv1i16.nxv1i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg4_nxv1i16_nxv1i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv1i16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv1i16.nxv1i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv1i16_nxv1i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv1i16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv1i16.nxv1i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv1i16.nxv2i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i8>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv1i16.nxv2i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg4_nxv1i16_nxv2i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv1i16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv1i16.nxv2i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv1i16_nxv2i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv1i16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv1i16.nxv2i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv1i16.nxv8i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i32>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv1i16.nxv8i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg4_nxv1i16_nxv8i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv1i16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv1i16.nxv8i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv1i16_nxv8i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv1i16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv1i16.nxv8i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv1i16.nxv32i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 32 x i8>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv1i16.nxv32i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 32 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg4_nxv1i16_nxv32i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv1i16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv1i16.nxv32i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv1i16_nxv32i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv1i16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv1i16.nxv32i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv1i16.nxv16i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i32>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv1i16.nxv16i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg4_nxv1i16_nxv16i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv1i16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv1i16.nxv16i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv1i16_nxv16i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv1i16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv1i16.nxv16i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv1i16.nxv2i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i16>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv1i16.nxv2i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg4_nxv1i16_nxv2i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv1i16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv1i16.nxv2i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv1i16_nxv2i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv1i16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv1i16.nxv2i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv1i16.nxv2i64(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i64>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv1i16.nxv2i64(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg4_nxv1i16_nxv2i64(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv1i16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg4ei64.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv1i16.nxv2i64(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv1i16_nxv2i64(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv1i16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg4ei64.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv1i16.nxv2i64(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv1i16.nxv16i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i16>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv1i16.nxv16i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg5_nxv1i16_nxv16i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv1i16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv1i16.nxv16i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv1i16_nxv16i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv1i16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv1i16.nxv16i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv1i16.nxv32i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 32 x i16>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv1i16.nxv32i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 32 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg5_nxv1i16_nxv32i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv1i16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv1i16.nxv32i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv1i16_nxv32i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv1i16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv1i16.nxv32i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv1i16.nxv4i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i32>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv1i16.nxv4i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg5_nxv1i16_nxv4i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv1i16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg5ei32.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv1i16.nxv4i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv1i16_nxv4i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv1i16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg5ei32.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv1i16.nxv4i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv1i16.nxv16i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i8>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv1i16.nxv16i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg5_nxv1i16_nxv16i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv1i16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv1i16.nxv16i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv1i16_nxv16i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv1i16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv1i16.nxv16i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv1i16.nxv1i64(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv1i16.nxv1i64(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg5_nxv1i16_nxv1i64(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv1i16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg5ei64.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv1i16.nxv1i64(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv1i16_nxv1i64(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv1i16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg5ei64.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv1i16.nxv1i64(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv1i16.nxv1i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv1i16.nxv1i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg5_nxv1i16_nxv1i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv1i16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg5ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv1i16.nxv1i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv1i16_nxv1i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv1i16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg5ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv1i16.nxv1i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv1i16.nxv8i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i16>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv1i16.nxv8i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg5_nxv1i16_nxv8i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv1i16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv1i16.nxv8i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv1i16_nxv8i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv1i16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv1i16.nxv8i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv1i16.nxv4i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i8>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv1i16.nxv4i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg5_nxv1i16_nxv4i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv1i16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv1i16.nxv4i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv1i16_nxv4i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv1i16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv1i16.nxv4i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv1i16.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv1i16.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg5_nxv1i16_nxv1i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv1i16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv1i16.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv1i16_nxv1i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv1i16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv1i16.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv1i16.nxv2i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i32>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv1i16.nxv2i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg5_nxv1i16_nxv2i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv1i16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg5ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv1i16.nxv2i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv1i16_nxv2i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv1i16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg5ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv1i16.nxv2i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv1i16.nxv8i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i8>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv1i16.nxv8i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg5_nxv1i16_nxv8i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv1i16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv1i16.nxv8i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv1i16_nxv8i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv1i16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv1i16.nxv8i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv1i16.nxv4i64(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i64>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv1i16.nxv4i64(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg5_nxv1i16_nxv4i64(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv1i16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg5ei64.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv1i16.nxv4i64(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv1i16_nxv4i64(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv1i16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg5ei64.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv1i16.nxv4i64(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv1i16.nxv64i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 64 x i8>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv1i16.nxv64i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 64 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg5_nxv1i16_nxv64i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv1i16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv1i16.nxv64i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv1i16_nxv64i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv1i16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv1i16.nxv64i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv1i16.nxv4i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i16>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv1i16.nxv4i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg5_nxv1i16_nxv4i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv1i16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv1i16.nxv4i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv1i16_nxv4i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv1i16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv1i16.nxv4i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv1i16.nxv8i64(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i64>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv1i16.nxv8i64(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg5_nxv1i16_nxv8i64(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv1i16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg5ei64.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv1i16.nxv8i64(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv1i16_nxv8i64(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv1i16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg5ei64.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv1i16.nxv8i64(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv1i16.nxv1i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv1i16.nxv1i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg5_nxv1i16_nxv1i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv1i16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv1i16.nxv1i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv1i16_nxv1i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv1i16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv1i16.nxv1i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv1i16.nxv2i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i8>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv1i16.nxv2i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg5_nxv1i16_nxv2i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv1i16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv1i16.nxv2i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv1i16_nxv2i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv1i16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv1i16.nxv2i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv1i16.nxv8i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i32>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv1i16.nxv8i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg5_nxv1i16_nxv8i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv1i16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg5ei32.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv1i16.nxv8i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv1i16_nxv8i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv1i16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg5ei32.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv1i16.nxv8i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv1i16.nxv32i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 32 x i8>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv1i16.nxv32i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 32 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg5_nxv1i16_nxv32i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv1i16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv1i16.nxv32i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv1i16_nxv32i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv1i16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv1i16.nxv32i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv1i16.nxv16i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i32>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv1i16.nxv16i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg5_nxv1i16_nxv16i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv1i16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg5ei32.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv1i16.nxv16i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv1i16_nxv16i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv1i16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg5ei32.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv1i16.nxv16i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv1i16.nxv2i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i16>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv1i16.nxv2i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg5_nxv1i16_nxv2i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv1i16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv1i16.nxv2i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv1i16_nxv2i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv1i16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv1i16.nxv2i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv1i16.nxv2i64(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i64>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv1i16.nxv2i64(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg5_nxv1i16_nxv2i64(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv1i16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg5ei64.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv1i16.nxv2i64(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv1i16_nxv2i64(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv1i16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg5ei64.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv1i16.nxv2i64(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv1i16.nxv16i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i16>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv1i16.nxv16i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg6_nxv1i16_nxv16i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv1i16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv1i16.nxv16i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv1i16_nxv16i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv1i16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv1i16.nxv16i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv1i16.nxv32i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 32 x i16>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv1i16.nxv32i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 32 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg6_nxv1i16_nxv32i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv1i16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv1i16.nxv32i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv1i16_nxv32i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv1i16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv1i16.nxv32i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv1i16.nxv4i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i32>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv1i16.nxv4i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg6_nxv1i16_nxv4i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv1i16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg6ei32.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv1i16.nxv4i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv1i16_nxv4i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv1i16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg6ei32.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv1i16.nxv4i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv1i16.nxv16i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i8>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv1i16.nxv16i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg6_nxv1i16_nxv16i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv1i16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv1i16.nxv16i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv1i16_nxv16i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv1i16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv1i16.nxv16i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv1i16.nxv1i64(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv1i16.nxv1i64(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg6_nxv1i16_nxv1i64(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv1i16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg6ei64.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv1i16.nxv1i64(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv1i16_nxv1i64(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv1i16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg6ei64.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv1i16.nxv1i64(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv1i16.nxv1i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv1i16.nxv1i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg6_nxv1i16_nxv1i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv1i16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg6ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv1i16.nxv1i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv1i16_nxv1i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv1i16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg6ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv1i16.nxv1i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv1i16.nxv8i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i16>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv1i16.nxv8i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg6_nxv1i16_nxv8i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv1i16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv1i16.nxv8i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv1i16_nxv8i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv1i16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv1i16.nxv8i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv1i16.nxv4i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i8>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv1i16.nxv4i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg6_nxv1i16_nxv4i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv1i16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv1i16.nxv4i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv1i16_nxv4i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv1i16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv1i16.nxv4i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv1i16.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv1i16.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg6_nxv1i16_nxv1i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv1i16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv1i16.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv1i16_nxv1i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv1i16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv1i16.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv1i16.nxv2i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i32>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv1i16.nxv2i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg6_nxv1i16_nxv2i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv1i16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg6ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv1i16.nxv2i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv1i16_nxv2i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv1i16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg6ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv1i16.nxv2i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv1i16.nxv8i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i8>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv1i16.nxv8i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg6_nxv1i16_nxv8i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv1i16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv1i16.nxv8i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv1i16_nxv8i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv1i16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv1i16.nxv8i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv1i16.nxv4i64(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i64>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv1i16.nxv4i64(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg6_nxv1i16_nxv4i64(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv1i16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg6ei64.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv1i16.nxv4i64(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv1i16_nxv4i64(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv1i16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg6ei64.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv1i16.nxv4i64(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv1i16.nxv64i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 64 x i8>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv1i16.nxv64i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 64 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg6_nxv1i16_nxv64i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv1i16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv1i16.nxv64i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv1i16_nxv64i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv1i16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv1i16.nxv64i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv1i16.nxv4i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i16>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv1i16.nxv4i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg6_nxv1i16_nxv4i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv1i16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv1i16.nxv4i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv1i16_nxv4i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv1i16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv1i16.nxv4i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv1i16.nxv8i64(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i64>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv1i16.nxv8i64(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg6_nxv1i16_nxv8i64(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv1i16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg6ei64.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv1i16.nxv8i64(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv1i16_nxv8i64(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv1i16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg6ei64.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv1i16.nxv8i64(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv1i16.nxv1i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv1i16.nxv1i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg6_nxv1i16_nxv1i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv1i16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv1i16.nxv1i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv1i16_nxv1i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv1i16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv1i16.nxv1i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv1i16.nxv2i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i8>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv1i16.nxv2i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg6_nxv1i16_nxv2i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv1i16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv1i16.nxv2i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv1i16_nxv2i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv1i16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv1i16.nxv2i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv1i16.nxv8i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i32>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv1i16.nxv8i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg6_nxv1i16_nxv8i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv1i16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg6ei32.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv1i16.nxv8i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv1i16_nxv8i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv1i16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg6ei32.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv1i16.nxv8i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv1i16.nxv32i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 32 x i8>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv1i16.nxv32i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 32 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg6_nxv1i16_nxv32i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv1i16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv1i16.nxv32i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv1i16_nxv32i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv1i16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv1i16.nxv32i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv1i16.nxv16i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i32>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv1i16.nxv16i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg6_nxv1i16_nxv16i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv1i16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg6ei32.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv1i16.nxv16i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv1i16_nxv16i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv1i16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg6ei32.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv1i16.nxv16i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv1i16.nxv2i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i16>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv1i16.nxv2i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg6_nxv1i16_nxv2i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv1i16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv1i16.nxv2i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv1i16_nxv2i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv1i16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv1i16.nxv2i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv1i16.nxv2i64(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i64>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv1i16.nxv2i64(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg6_nxv1i16_nxv2i64(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv1i16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg6ei64.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv1i16.nxv2i64(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv1i16_nxv2i64(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv1i16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg6ei64.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv1i16.nxv2i64(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv1i16.nxv16i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i16>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv1i16.nxv16i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg7_nxv1i16_nxv16i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv1i16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv1i16.nxv16i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv1i16_nxv16i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv1i16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv1i16.nxv16i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv1i16.nxv32i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 32 x i16>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv1i16.nxv32i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 32 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg7_nxv1i16_nxv32i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv1i16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv1i16.nxv32i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv1i16_nxv32i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv1i16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv1i16.nxv32i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv1i16.nxv4i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i32>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv1i16.nxv4i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg7_nxv1i16_nxv4i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv1i16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg7ei32.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv1i16.nxv4i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv1i16_nxv4i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv1i16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg7ei32.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv1i16.nxv4i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv1i16.nxv16i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i8>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv1i16.nxv16i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg7_nxv1i16_nxv16i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv1i16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv1i16.nxv16i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv1i16_nxv16i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv1i16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv1i16.nxv16i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv1i16.nxv1i64(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv1i16.nxv1i64(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg7_nxv1i16_nxv1i64(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv1i16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg7ei64.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv1i16.nxv1i64(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv1i16_nxv1i64(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv1i16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg7ei64.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv1i16.nxv1i64(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv1i16.nxv1i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv1i16.nxv1i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg7_nxv1i16_nxv1i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv1i16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg7ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv1i16.nxv1i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv1i16_nxv1i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv1i16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg7ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv1i16.nxv1i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv1i16.nxv8i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i16>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv1i16.nxv8i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg7_nxv1i16_nxv8i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv1i16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv1i16.nxv8i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv1i16_nxv8i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv1i16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv1i16.nxv8i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv1i16.nxv4i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i8>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv1i16.nxv4i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg7_nxv1i16_nxv4i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv1i16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv1i16.nxv4i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv1i16_nxv4i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv1i16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv1i16.nxv4i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv1i16.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv1i16.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg7_nxv1i16_nxv1i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv1i16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv1i16.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv1i16_nxv1i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv1i16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv1i16.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv1i16.nxv2i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i32>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv1i16.nxv2i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg7_nxv1i16_nxv2i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv1i16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg7ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv1i16.nxv2i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv1i16_nxv2i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv1i16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg7ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv1i16.nxv2i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv1i16.nxv8i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i8>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv1i16.nxv8i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg7_nxv1i16_nxv8i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv1i16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv1i16.nxv8i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv1i16_nxv8i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv1i16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv1i16.nxv8i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv1i16.nxv4i64(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i64>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv1i16.nxv4i64(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg7_nxv1i16_nxv4i64(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv1i16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg7ei64.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv1i16.nxv4i64(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv1i16_nxv4i64(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv1i16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg7ei64.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv1i16.nxv4i64(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv1i16.nxv64i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 64 x i8>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv1i16.nxv64i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 64 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg7_nxv1i16_nxv64i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv1i16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv1i16.nxv64i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv1i16_nxv64i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv1i16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv1i16.nxv64i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv1i16.nxv4i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i16>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv1i16.nxv4i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg7_nxv1i16_nxv4i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv1i16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv1i16.nxv4i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv1i16_nxv4i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv1i16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv1i16.nxv4i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv1i16.nxv8i64(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i64>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv1i16.nxv8i64(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg7_nxv1i16_nxv8i64(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv1i16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg7ei64.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv1i16.nxv8i64(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv1i16_nxv8i64(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv1i16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg7ei64.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv1i16.nxv8i64(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv1i16.nxv1i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv1i16.nxv1i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg7_nxv1i16_nxv1i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv1i16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv1i16.nxv1i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv1i16_nxv1i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv1i16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv1i16.nxv1i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv1i16.nxv2i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i8>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv1i16.nxv2i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg7_nxv1i16_nxv2i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv1i16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv1i16.nxv2i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv1i16_nxv2i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv1i16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv1i16.nxv2i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv1i16.nxv8i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i32>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv1i16.nxv8i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg7_nxv1i16_nxv8i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv1i16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg7ei32.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv1i16.nxv8i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv1i16_nxv8i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv1i16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg7ei32.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv1i16.nxv8i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv1i16.nxv32i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 32 x i8>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv1i16.nxv32i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 32 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg7_nxv1i16_nxv32i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv1i16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv1i16.nxv32i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv1i16_nxv32i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv1i16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv1i16.nxv32i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv1i16.nxv16i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i32>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv1i16.nxv16i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg7_nxv1i16_nxv16i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv1i16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg7ei32.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv1i16.nxv16i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv1i16_nxv16i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv1i16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg7ei32.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv1i16.nxv16i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv1i16.nxv2i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i16>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv1i16.nxv2i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg7_nxv1i16_nxv2i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv1i16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv1i16.nxv2i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv1i16_nxv2i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv1i16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv1i16.nxv2i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv1i16.nxv2i64(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i64>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv1i16.nxv2i64(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg7_nxv1i16_nxv2i64(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv1i16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg7ei64.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv1i16.nxv2i64(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv1i16_nxv2i64(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv1i16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg7ei64.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv1i16.nxv2i64(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv1i16.nxv16i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i16>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv1i16.nxv16i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg8_nxv1i16_nxv16i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv1i16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv1i16.nxv16i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv1i16_nxv16i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv1i16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv1i16.nxv16i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv1i16.nxv32i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 32 x i16>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv1i16.nxv32i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 32 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg8_nxv1i16_nxv32i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv1i16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vmv1r.v v23, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv1i16.nxv32i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv1i16_nxv32i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv1i16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vmv1r.v v23, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv1i16.nxv32i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv1i16.nxv4i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i32>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv1i16.nxv4i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg8_nxv1i16_nxv4i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv1i16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg8ei32.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv1i16.nxv4i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv1i16_nxv4i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv1i16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg8ei32.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv1i16.nxv4i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv1i16.nxv16i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i8>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv1i16.nxv16i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg8_nxv1i16_nxv16i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv1i16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv1i16.nxv16i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv1i16_nxv16i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv1i16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv1i16.nxv16i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv1i16.nxv1i64(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv1i16.nxv1i64(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg8_nxv1i16_nxv1i64(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv1i16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg8ei64.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv1i16.nxv1i64(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv1i16_nxv1i64(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv1i16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg8ei64.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv1i16.nxv1i64(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv1i16.nxv1i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv1i16.nxv1i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg8_nxv1i16_nxv1i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv1i16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg8ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv1i16.nxv1i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv1i16_nxv1i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv1i16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg8ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv1i16.nxv1i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv1i16.nxv8i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i16>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv1i16.nxv8i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg8_nxv1i16_nxv8i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv1i16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv1i16.nxv8i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv1i16_nxv8i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv1i16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv1i16.nxv8i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv1i16.nxv4i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i8>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv1i16.nxv4i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg8_nxv1i16_nxv4i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv1i16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv1i16.nxv4i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv1i16_nxv4i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv1i16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv1i16.nxv4i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv1i16.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv1i16.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg8_nxv1i16_nxv1i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv1i16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv1i16.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv1i16_nxv1i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv1i16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv1i16.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv1i16.nxv2i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i32>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv1i16.nxv2i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg8_nxv1i16_nxv2i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv1i16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg8ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv1i16.nxv2i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv1i16_nxv2i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv1i16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg8ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv1i16.nxv2i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv1i16.nxv8i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i8>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv1i16.nxv8i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg8_nxv1i16_nxv8i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv1i16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv1i16.nxv8i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv1i16_nxv8i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv1i16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv1i16.nxv8i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv1i16.nxv4i64(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i64>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv1i16.nxv4i64(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg8_nxv1i16_nxv4i64(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv1i16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg8ei64.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv1i16.nxv4i64(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv1i16_nxv4i64(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv1i16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg8ei64.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv1i16.nxv4i64(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv1i16.nxv64i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 64 x i8>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv1i16.nxv64i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 64 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg8_nxv1i16_nxv64i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv1i16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vmv1r.v v23, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv1i16.nxv64i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv1i16_nxv64i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv1i16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vmv1r.v v23, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv1i16.nxv64i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv1i16.nxv4i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i16>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv1i16.nxv4i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 4 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg8_nxv1i16_nxv4i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv1i16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv1i16.nxv4i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv1i16_nxv4i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv1i16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv1i16.nxv4i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv1i16.nxv8i64(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i64>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv1i16.nxv8i64(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg8_nxv1i16_nxv8i64(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv1i16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vmv1r.v v23, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg8ei64.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv1i16.nxv8i64(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv1i16_nxv8i64(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv1i16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vmv1r.v v23, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg8ei64.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv1i16.nxv8i64(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv1i16.nxv1i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv1i16.nxv1i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg8_nxv1i16_nxv1i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv1i16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv1i16.nxv1i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv1i16_nxv1i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv1i16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv1i16.nxv1i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv1i16.nxv2i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i8>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv1i16.nxv2i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg8_nxv1i16_nxv2i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv1i16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv1i16.nxv2i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv1i16_nxv2i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv1i16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv1i16.nxv2i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv1i16.nxv8i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i32>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv1i16.nxv8i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 8 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg8_nxv1i16_nxv8i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv1i16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg8ei32.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv1i16.nxv8i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv1i16_nxv8i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv1i16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg8ei32.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv1i16.nxv8i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv1i16.nxv32i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 32 x i8>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv1i16.nxv32i8(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 32 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg8_nxv1i16_nxv32i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv1i16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv1i16.nxv32i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv1i16_nxv32i8(<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv1i16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv1i16.nxv32i8(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv1i16.nxv16i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i32>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv1i16.nxv16i32(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 16 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg8_nxv1i16_nxv16i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv1i16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vmv1r.v v23, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg8ei32.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv1i16.nxv16i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv1i16_nxv16i32(<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv1i16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vmv1r.v v23, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg8ei32.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv1i16.nxv16i32(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv1i16.nxv2i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i16>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv1i16.nxv2i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg8_nxv1i16_nxv2i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv1i16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv1i16.nxv2i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv1i16_nxv2i16(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv1i16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv1i16.nxv2i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv1i16.nxv2i64(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i64>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv1i16.nxv2i64(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 2 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg8_nxv1i16_nxv2i64(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv1i16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg8ei64.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv1i16.nxv2i64(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv1i16_nxv2i64(<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv1i16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg8ei64.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv1i16.nxv2i64(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv2i32.nxv16i16(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i16>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv2i32.nxv16i16(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg2_nxv2i32_nxv16i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv2i32_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv2i32.nxv16i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv2i32_nxv16i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv2i32_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv2i32.nxv16i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv2i32.nxv32i16(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 32 x i16>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv2i32.nxv32i16(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 32 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg2_nxv2i32_nxv32i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv2i32_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv2i32.nxv32i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv2i32_nxv32i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv2i32_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv2i32.nxv32i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv2i32.nxv4i32(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i32>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv2i32.nxv4i32(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg2_nxv2i32_nxv4i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv2i32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv2i32.nxv4i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv2i32_nxv4i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv2i32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv2i32.nxv4i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv2i32.nxv16i8(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv2i32.nxv16i8(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg2_nxv2i32_nxv16i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv2i32_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv2i32.nxv16i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv2i32_nxv16i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv2i32_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv2i32.nxv16i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv2i32.nxv1i64(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv2i32.nxv1i64(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i64>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg2_nxv2i32_nxv1i64(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv2i32_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv2i32.nxv1i64(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv2i32_nxv1i64(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv2i32_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv2i32.nxv1i64(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv2i32.nxv1i32(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv2i32.nxv1i32(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg2_nxv2i32_nxv1i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv2i32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv2i32.nxv1i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv2i32_nxv1i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv2i32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv2i32.nxv1i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv2i32.nxv8i16(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i16>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv2i32.nxv8i16(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg2_nxv2i32_nxv8i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv2i32_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv2i32.nxv8i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv2i32_nxv8i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv2i32_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv2i32.nxv8i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv2i32.nxv4i8(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv2i32.nxv4i8(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg2_nxv2i32_nxv4i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv2i32_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv2i32.nxv4i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv2i32_nxv4i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv2i32_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv2i32.nxv4i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv2i32.nxv1i16(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv2i32.nxv1i16(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg2_nxv2i32_nxv1i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv2i32_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv2i32.nxv1i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv2i32_nxv1i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv2i32_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv2i32.nxv1i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv2i32.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i32>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv2i32.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg2_nxv2i32_nxv2i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv2i32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv2i32.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv2i32_nxv2i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv2i32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv2i32.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv2i32.nxv8i8(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv2i32.nxv8i8(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg2_nxv2i32_nxv8i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv2i32_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv2i32.nxv8i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv2i32_nxv8i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv2i32_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv2i32.nxv8i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv2i32.nxv4i64(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i64>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv2i32.nxv4i64(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i64>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg2_nxv2i32_nxv4i64(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv2i32_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv2i32.nxv4i64(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv2i32_nxv4i64(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv2i32_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv2i32.nxv4i64(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv2i32.nxv64i8(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 64 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv2i32.nxv64i8(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 64 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg2_nxv2i32_nxv64i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv2i32_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv2i32.nxv64i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 64 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv2i32_nxv64i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv2i32_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv2i32.nxv64i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv2i32.nxv4i16(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i16>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv2i32.nxv4i16(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg2_nxv2i32_nxv4i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv2i32_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv2i32.nxv4i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv2i32_nxv4i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv2i32_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv2i32.nxv4i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv2i32.nxv8i64(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i64>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv2i32.nxv8i64(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i64>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg2_nxv2i32_nxv8i64(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv2i32_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv2i32.nxv8i64(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv2i32_nxv8i64(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv2i32_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv2i32.nxv8i64(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv2i32.nxv1i8(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv2i32.nxv1i8(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg2_nxv2i32_nxv1i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv2i32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv2i32.nxv1i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv2i32_nxv1i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv2i32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv2i32.nxv1i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv2i32.nxv2i8(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv2i32.nxv2i8(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg2_nxv2i32_nxv2i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv2i32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv2i32.nxv2i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv2i32_nxv2i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv2i32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv2i32.nxv2i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv2i32.nxv8i32(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i32>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv2i32.nxv8i32(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg2_nxv2i32_nxv8i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv2i32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv2i32.nxv8i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv2i32_nxv8i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv2i32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv2i32.nxv8i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv2i32.nxv32i8(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 32 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv2i32.nxv32i8(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 32 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg2_nxv2i32_nxv32i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv2i32_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv2i32.nxv32i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv2i32_nxv32i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv2i32_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv2i32.nxv32i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv2i32.nxv16i32(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i32>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv2i32.nxv16i32(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg2_nxv2i32_nxv16i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv2i32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv2i32.nxv16i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv2i32_nxv16i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv2i32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv2i32.nxv16i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv2i32.nxv2i16(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i16>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv2i32.nxv2i16(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg2_nxv2i32_nxv2i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv2i32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv2i32.nxv2i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv2i32_nxv2i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv2i32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv2i32.nxv2i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv2i32.nxv2i64(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i64>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv2i32.nxv2i64(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg2_nxv2i32_nxv2i64(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv2i32_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv2i32.nxv2i64(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv2i32_nxv2i64(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv2i32_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv2i32.nxv2i64(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv2i32.nxv16i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i16>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv2i32.nxv16i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg3_nxv2i32_nxv16i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv2i32_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv2i32.nxv16i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv2i32_nxv16i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv2i32_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv2i32.nxv16i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv2i32.nxv32i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 32 x i16>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv2i32.nxv32i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 32 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg3_nxv2i32_nxv32i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv2i32_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv2i32.nxv32i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv2i32_nxv32i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv2i32_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv2i32.nxv32i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv2i32.nxv4i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i32>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv2i32.nxv4i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg3_nxv2i32_nxv4i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv2i32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv2i32.nxv4i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv2i32_nxv4i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv2i32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv2i32.nxv4i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv2i32.nxv16i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i8>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv2i32.nxv16i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg3_nxv2i32_nxv16i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv2i32_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv2i32.nxv16i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv2i32_nxv16i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv2i32_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv2i32.nxv16i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv2i32.nxv1i64(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv2i32.nxv1i64(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i64>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg3_nxv2i32_nxv1i64(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv2i32_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei64.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv2i32.nxv1i64(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv2i32_nxv1i64(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv2i32_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei64.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv2i32.nxv1i64(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv2i32.nxv1i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv2i32.nxv1i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg3_nxv2i32_nxv1i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv2i32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv2i32.nxv1i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv2i32_nxv1i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv2i32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv2i32.nxv1i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv2i32.nxv8i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i16>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv2i32.nxv8i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg3_nxv2i32_nxv8i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv2i32_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv2i32.nxv8i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv2i32_nxv8i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv2i32_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv2i32.nxv8i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv2i32.nxv4i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i8>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv2i32.nxv4i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg3_nxv2i32_nxv4i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv2i32_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv2i32.nxv4i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv2i32_nxv4i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv2i32_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv2i32.nxv4i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv2i32.nxv1i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv2i32.nxv1i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg3_nxv2i32_nxv1i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv2i32_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv2i32.nxv1i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv2i32_nxv1i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv2i32_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv2i32.nxv1i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv2i32.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i32>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv2i32.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg3_nxv2i32_nxv2i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv2i32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv2i32.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv2i32_nxv2i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv2i32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv2i32.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv2i32.nxv8i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i8>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv2i32.nxv8i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg3_nxv2i32_nxv8i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv2i32_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv2i32.nxv8i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv2i32_nxv8i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv2i32_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv2i32.nxv8i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv2i32.nxv4i64(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i64>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv2i32.nxv4i64(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i64>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg3_nxv2i32_nxv4i64(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv2i32_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei64.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv2i32.nxv4i64(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv2i32_nxv4i64(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv2i32_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei64.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv2i32.nxv4i64(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv2i32.nxv64i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 64 x i8>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv2i32.nxv64i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 64 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg3_nxv2i32_nxv64i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv2i32_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv2i32.nxv64i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 64 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv2i32_nxv64i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv2i32_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv2i32.nxv64i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv2i32.nxv4i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i16>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv2i32.nxv4i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg3_nxv2i32_nxv4i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv2i32_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv2i32.nxv4i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv2i32_nxv4i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv2i32_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv2i32.nxv4i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv2i32.nxv8i64(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i64>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv2i32.nxv8i64(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i64>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg3_nxv2i32_nxv8i64(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv2i32_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei64.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv2i32.nxv8i64(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv2i32_nxv8i64(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv2i32_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei64.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv2i32.nxv8i64(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv2i32.nxv1i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv2i32.nxv1i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg3_nxv2i32_nxv1i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv2i32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv2i32.nxv1i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv2i32_nxv1i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv2i32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv2i32.nxv1i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv2i32.nxv2i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i8>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv2i32.nxv2i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg3_nxv2i32_nxv2i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv2i32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv2i32.nxv2i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv2i32_nxv2i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv2i32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv2i32.nxv2i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv2i32.nxv8i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i32>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv2i32.nxv8i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg3_nxv2i32_nxv8i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv2i32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv2i32.nxv8i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv2i32_nxv8i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv2i32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv2i32.nxv8i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv2i32.nxv32i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 32 x i8>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv2i32.nxv32i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 32 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg3_nxv2i32_nxv32i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv2i32_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv2i32.nxv32i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv2i32_nxv32i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv2i32_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv2i32.nxv32i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv2i32.nxv16i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i32>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv2i32.nxv16i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg3_nxv2i32_nxv16i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv2i32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv2i32.nxv16i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv2i32_nxv16i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv2i32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv2i32.nxv16i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv2i32.nxv2i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i16>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv2i32.nxv2i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg3_nxv2i32_nxv2i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv2i32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv2i32.nxv2i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv2i32_nxv2i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv2i32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv2i32.nxv2i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv2i32.nxv2i64(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i64>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv2i32.nxv2i64(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg3_nxv2i32_nxv2i64(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv2i32_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei64.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv2i32.nxv2i64(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv2i32_nxv2i64(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv2i32_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei64.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv2i32.nxv2i64(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv2i32.nxv16i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i16>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv2i32.nxv16i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg4_nxv2i32_nxv16i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv2i32_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv2i32.nxv16i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv2i32_nxv16i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv2i32_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv2i32.nxv16i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv2i32.nxv32i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 32 x i16>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv2i32.nxv32i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 32 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg4_nxv2i32_nxv32i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv2i32_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv2i32.nxv32i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv2i32_nxv32i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv2i32_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv2i32.nxv32i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv2i32.nxv4i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i32>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv2i32.nxv4i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg4_nxv2i32_nxv4i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv2i32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv2i32.nxv4i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv2i32_nxv4i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv2i32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv2i32.nxv4i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv2i32.nxv16i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i8>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv2i32.nxv16i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg4_nxv2i32_nxv16i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv2i32_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv2i32.nxv16i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv2i32_nxv16i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv2i32_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv2i32.nxv16i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv2i32.nxv1i64(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv2i32.nxv1i64(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i64>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg4_nxv2i32_nxv1i64(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv2i32_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei64.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv2i32.nxv1i64(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv2i32_nxv1i64(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv2i32_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei64.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv2i32.nxv1i64(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv2i32.nxv1i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv2i32.nxv1i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg4_nxv2i32_nxv1i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv2i32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv2i32.nxv1i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv2i32_nxv1i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv2i32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv2i32.nxv1i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv2i32.nxv8i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i16>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv2i32.nxv8i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg4_nxv2i32_nxv8i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv2i32_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv2i32.nxv8i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv2i32_nxv8i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv2i32_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv2i32.nxv8i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv2i32.nxv4i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i8>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv2i32.nxv4i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg4_nxv2i32_nxv4i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv2i32_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv2i32.nxv4i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv2i32_nxv4i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv2i32_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv2i32.nxv4i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv2i32.nxv1i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv2i32.nxv1i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg4_nxv2i32_nxv1i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv2i32_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv2i32.nxv1i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv2i32_nxv1i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv2i32_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv2i32.nxv1i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv2i32.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i32>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv2i32.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg4_nxv2i32_nxv2i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv2i32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv2i32.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv2i32_nxv2i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv2i32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv2i32.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv2i32.nxv8i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i8>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv2i32.nxv8i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg4_nxv2i32_nxv8i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv2i32_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv2i32.nxv8i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv2i32_nxv8i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv2i32_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv2i32.nxv8i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv2i32.nxv4i64(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i64>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv2i32.nxv4i64(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i64>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg4_nxv2i32_nxv4i64(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv2i32_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei64.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv2i32.nxv4i64(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv2i32_nxv4i64(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv2i32_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei64.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv2i32.nxv4i64(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv2i32.nxv64i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 64 x i8>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv2i32.nxv64i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 64 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg4_nxv2i32_nxv64i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv2i32_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv2i32.nxv64i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 64 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv2i32_nxv64i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv2i32_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv2i32.nxv64i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv2i32.nxv4i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i16>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv2i32.nxv4i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg4_nxv2i32_nxv4i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv2i32_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv2i32.nxv4i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv2i32_nxv4i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv2i32_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv2i32.nxv4i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv2i32.nxv8i64(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i64>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv2i32.nxv8i64(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i64>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg4_nxv2i32_nxv8i64(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv2i32_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei64.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv2i32.nxv8i64(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv2i32_nxv8i64(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv2i32_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei64.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv2i32.nxv8i64(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv2i32.nxv1i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv2i32.nxv1i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg4_nxv2i32_nxv1i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv2i32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv2i32.nxv1i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv2i32_nxv1i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv2i32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv2i32.nxv1i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv2i32.nxv2i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i8>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv2i32.nxv2i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg4_nxv2i32_nxv2i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv2i32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv2i32.nxv2i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv2i32_nxv2i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv2i32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv2i32.nxv2i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv2i32.nxv8i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i32>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv2i32.nxv8i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg4_nxv2i32_nxv8i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv2i32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv2i32.nxv8i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv2i32_nxv8i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv2i32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv2i32.nxv8i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv2i32.nxv32i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 32 x i8>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv2i32.nxv32i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 32 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg4_nxv2i32_nxv32i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv2i32_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv2i32.nxv32i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv2i32_nxv32i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv2i32_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv2i32.nxv32i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv2i32.nxv16i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i32>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv2i32.nxv16i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg4_nxv2i32_nxv16i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv2i32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv2i32.nxv16i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv2i32_nxv16i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv2i32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv2i32.nxv16i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv2i32.nxv2i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i16>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv2i32.nxv2i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg4_nxv2i32_nxv2i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv2i32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv2i32.nxv2i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv2i32_nxv2i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv2i32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv2i32.nxv2i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv2i32.nxv2i64(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i64>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv2i32.nxv2i64(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg4_nxv2i32_nxv2i64(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv2i32_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei64.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv2i32.nxv2i64(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv2i32_nxv2i64(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv2i32_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei64.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv2i32.nxv2i64(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv2i32.nxv16i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i16>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv2i32.nxv16i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg5_nxv2i32_nxv16i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv2i32_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv2i32.nxv16i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv2i32_nxv16i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv2i32_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv2i32.nxv16i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv2i32.nxv32i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 32 x i16>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv2i32.nxv32i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 32 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg5_nxv2i32_nxv32i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv2i32_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv2i32.nxv32i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv2i32_nxv32i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv2i32_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv2i32.nxv32i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv2i32.nxv4i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i32>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv2i32.nxv4i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg5_nxv2i32_nxv4i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv2i32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei32.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv2i32.nxv4i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv2i32_nxv4i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv2i32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei32.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv2i32.nxv4i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv2i32.nxv16i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i8>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv2i32.nxv16i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg5_nxv2i32_nxv16i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv2i32_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv2i32.nxv16i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv2i32_nxv16i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv2i32_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv2i32.nxv16i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv2i32.nxv1i64(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv2i32.nxv1i64(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i64>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg5_nxv2i32_nxv1i64(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv2i32_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei64.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv2i32.nxv1i64(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv2i32_nxv1i64(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv2i32_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei64.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv2i32.nxv1i64(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv2i32.nxv1i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv2i32.nxv1i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg5_nxv2i32_nxv1i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv2i32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv2i32.nxv1i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv2i32_nxv1i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv2i32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv2i32.nxv1i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv2i32.nxv8i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i16>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv2i32.nxv8i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg5_nxv2i32_nxv8i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv2i32_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv2i32.nxv8i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv2i32_nxv8i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv2i32_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv2i32.nxv8i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv2i32.nxv4i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i8>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv2i32.nxv4i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg5_nxv2i32_nxv4i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv2i32_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv2i32.nxv4i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv2i32_nxv4i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv2i32_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv2i32.nxv4i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv2i32.nxv1i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv2i32.nxv1i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg5_nxv2i32_nxv1i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv2i32_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv2i32.nxv1i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv2i32_nxv1i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv2i32_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv2i32.nxv1i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv2i32.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i32>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv2i32.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg5_nxv2i32_nxv2i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv2i32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv2i32.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv2i32_nxv2i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv2i32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv2i32.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv2i32.nxv8i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i8>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv2i32.nxv8i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg5_nxv2i32_nxv8i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv2i32_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv2i32.nxv8i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv2i32_nxv8i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv2i32_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv2i32.nxv8i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv2i32.nxv4i64(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i64>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv2i32.nxv4i64(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i64>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg5_nxv2i32_nxv4i64(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv2i32_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei64.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv2i32.nxv4i64(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv2i32_nxv4i64(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv2i32_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei64.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv2i32.nxv4i64(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv2i32.nxv64i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 64 x i8>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv2i32.nxv64i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 64 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg5_nxv2i32_nxv64i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv2i32_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv2i32.nxv64i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 64 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv2i32_nxv64i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv2i32_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv2i32.nxv64i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv2i32.nxv4i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i16>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv2i32.nxv4i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg5_nxv2i32_nxv4i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv2i32_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv2i32.nxv4i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv2i32_nxv4i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv2i32_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv2i32.nxv4i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv2i32.nxv8i64(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i64>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv2i32.nxv8i64(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i64>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg5_nxv2i32_nxv8i64(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv2i32_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei64.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv2i32.nxv8i64(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv2i32_nxv8i64(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv2i32_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei64.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv2i32.nxv8i64(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv2i32.nxv1i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv2i32.nxv1i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg5_nxv2i32_nxv1i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv2i32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv2i32.nxv1i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv2i32_nxv1i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv2i32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv2i32.nxv1i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv2i32.nxv2i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i8>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv2i32.nxv2i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg5_nxv2i32_nxv2i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv2i32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv2i32.nxv2i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv2i32_nxv2i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv2i32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv2i32.nxv2i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv2i32.nxv8i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i32>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv2i32.nxv8i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg5_nxv2i32_nxv8i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv2i32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei32.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv2i32.nxv8i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv2i32_nxv8i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv2i32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei32.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv2i32.nxv8i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv2i32.nxv32i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 32 x i8>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv2i32.nxv32i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 32 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg5_nxv2i32_nxv32i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv2i32_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv2i32.nxv32i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv2i32_nxv32i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv2i32_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv2i32.nxv32i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv2i32.nxv16i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i32>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv2i32.nxv16i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg5_nxv2i32_nxv16i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv2i32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei32.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv2i32.nxv16i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv2i32_nxv16i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv2i32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei32.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv2i32.nxv16i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv2i32.nxv2i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i16>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv2i32.nxv2i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg5_nxv2i32_nxv2i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv2i32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv2i32.nxv2i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv2i32_nxv2i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv2i32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv2i32.nxv2i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv2i32.nxv2i64(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i64>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv2i32.nxv2i64(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg5_nxv2i32_nxv2i64(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv2i32_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei64.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv2i32.nxv2i64(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv2i32_nxv2i64(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv2i32_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei64.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv2i32.nxv2i64(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv2i32.nxv16i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i16>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv2i32.nxv16i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg6_nxv2i32_nxv16i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv2i32_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv2i32.nxv16i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv2i32_nxv16i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv2i32_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv2i32.nxv16i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv2i32.nxv32i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 32 x i16>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv2i32.nxv32i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 32 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg6_nxv2i32_nxv32i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv2i32_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv2i32.nxv32i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv2i32_nxv32i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv2i32_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv2i32.nxv32i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv2i32.nxv4i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i32>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv2i32.nxv4i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg6_nxv2i32_nxv4i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv2i32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei32.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv2i32.nxv4i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv2i32_nxv4i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv2i32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei32.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv2i32.nxv4i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv2i32.nxv16i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i8>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv2i32.nxv16i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg6_nxv2i32_nxv16i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv2i32_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv2i32.nxv16i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv2i32_nxv16i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv2i32_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv2i32.nxv16i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv2i32.nxv1i64(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv2i32.nxv1i64(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i64>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg6_nxv2i32_nxv1i64(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv2i32_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei64.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv2i32.nxv1i64(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv2i32_nxv1i64(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv2i32_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei64.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv2i32.nxv1i64(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv2i32.nxv1i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv2i32.nxv1i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg6_nxv2i32_nxv1i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv2i32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv2i32.nxv1i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv2i32_nxv1i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv2i32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv2i32.nxv1i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv2i32.nxv8i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i16>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv2i32.nxv8i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg6_nxv2i32_nxv8i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv2i32_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv2i32.nxv8i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv2i32_nxv8i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv2i32_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv2i32.nxv8i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv2i32.nxv4i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i8>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv2i32.nxv4i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg6_nxv2i32_nxv4i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv2i32_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv2i32.nxv4i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv2i32_nxv4i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv2i32_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv2i32.nxv4i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv2i32.nxv1i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv2i32.nxv1i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg6_nxv2i32_nxv1i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv2i32_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv2i32.nxv1i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv2i32_nxv1i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv2i32_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv2i32.nxv1i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv2i32.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i32>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv2i32.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg6_nxv2i32_nxv2i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv2i32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv2i32.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv2i32_nxv2i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv2i32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv2i32.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv2i32.nxv8i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i8>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv2i32.nxv8i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg6_nxv2i32_nxv8i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv2i32_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv2i32.nxv8i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv2i32_nxv8i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv2i32_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv2i32.nxv8i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv2i32.nxv4i64(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i64>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv2i32.nxv4i64(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i64>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg6_nxv2i32_nxv4i64(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv2i32_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei64.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv2i32.nxv4i64(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv2i32_nxv4i64(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv2i32_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei64.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv2i32.nxv4i64(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv2i32.nxv64i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 64 x i8>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv2i32.nxv64i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 64 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg6_nxv2i32_nxv64i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv2i32_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv2i32.nxv64i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 64 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv2i32_nxv64i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv2i32_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv2i32.nxv64i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv2i32.nxv4i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i16>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv2i32.nxv4i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg6_nxv2i32_nxv4i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv2i32_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv2i32.nxv4i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv2i32_nxv4i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv2i32_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv2i32.nxv4i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv2i32.nxv8i64(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i64>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv2i32.nxv8i64(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i64>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg6_nxv2i32_nxv8i64(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv2i32_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei64.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv2i32.nxv8i64(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv2i32_nxv8i64(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv2i32_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei64.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv2i32.nxv8i64(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv2i32.nxv1i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv2i32.nxv1i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg6_nxv2i32_nxv1i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv2i32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv2i32.nxv1i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv2i32_nxv1i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv2i32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv2i32.nxv1i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv2i32.nxv2i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i8>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv2i32.nxv2i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg6_nxv2i32_nxv2i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv2i32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv2i32.nxv2i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv2i32_nxv2i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv2i32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv2i32.nxv2i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv2i32.nxv8i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i32>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv2i32.nxv8i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg6_nxv2i32_nxv8i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv2i32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei32.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv2i32.nxv8i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv2i32_nxv8i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv2i32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei32.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv2i32.nxv8i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv2i32.nxv32i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 32 x i8>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv2i32.nxv32i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 32 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg6_nxv2i32_nxv32i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv2i32_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv2i32.nxv32i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv2i32_nxv32i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv2i32_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv2i32.nxv32i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv2i32.nxv16i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i32>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv2i32.nxv16i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg6_nxv2i32_nxv16i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv2i32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei32.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv2i32.nxv16i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv2i32_nxv16i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv2i32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei32.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv2i32.nxv16i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv2i32.nxv2i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i16>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv2i32.nxv2i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg6_nxv2i32_nxv2i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv2i32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv2i32.nxv2i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv2i32_nxv2i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv2i32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv2i32.nxv2i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv2i32.nxv2i64(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i64>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv2i32.nxv2i64(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg6_nxv2i32_nxv2i64(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv2i32_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei64.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv2i32.nxv2i64(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv2i32_nxv2i64(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv2i32_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei64.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv2i32.nxv2i64(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv2i32.nxv16i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i16>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv2i32.nxv16i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg7_nxv2i32_nxv16i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv2i32_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv2i32.nxv16i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv2i32_nxv16i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv2i32_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv2i32.nxv16i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv2i32.nxv32i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 32 x i16>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv2i32.nxv32i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 32 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg7_nxv2i32_nxv32i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv2i32_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv2i32.nxv32i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv2i32_nxv32i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv2i32_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv2i32.nxv32i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv2i32.nxv4i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i32>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv2i32.nxv4i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg7_nxv2i32_nxv4i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv2i32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei32.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv2i32.nxv4i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv2i32_nxv4i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv2i32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei32.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv2i32.nxv4i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv2i32.nxv16i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i8>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv2i32.nxv16i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg7_nxv2i32_nxv16i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv2i32_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv2i32.nxv16i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv2i32_nxv16i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv2i32_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv2i32.nxv16i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv2i32.nxv1i64(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv2i32.nxv1i64(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i64>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg7_nxv2i32_nxv1i64(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv2i32_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei64.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv2i32.nxv1i64(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv2i32_nxv1i64(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv2i32_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei64.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv2i32.nxv1i64(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv2i32.nxv1i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv2i32.nxv1i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg7_nxv2i32_nxv1i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv2i32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv2i32.nxv1i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv2i32_nxv1i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv2i32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv2i32.nxv1i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv2i32.nxv8i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i16>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv2i32.nxv8i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg7_nxv2i32_nxv8i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv2i32_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv2i32.nxv8i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv2i32_nxv8i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv2i32_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv2i32.nxv8i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv2i32.nxv4i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i8>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv2i32.nxv4i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg7_nxv2i32_nxv4i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv2i32_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv2i32.nxv4i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv2i32_nxv4i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv2i32_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv2i32.nxv4i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv2i32.nxv1i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv2i32.nxv1i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg7_nxv2i32_nxv1i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv2i32_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv2i32.nxv1i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv2i32_nxv1i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv2i32_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv2i32.nxv1i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv2i32.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i32>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv2i32.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg7_nxv2i32_nxv2i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv2i32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv2i32.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv2i32_nxv2i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv2i32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv2i32.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv2i32.nxv8i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i8>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv2i32.nxv8i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg7_nxv2i32_nxv8i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv2i32_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv2i32.nxv8i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv2i32_nxv8i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv2i32_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv2i32.nxv8i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv2i32.nxv4i64(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i64>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv2i32.nxv4i64(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i64>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg7_nxv2i32_nxv4i64(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv2i32_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei64.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv2i32.nxv4i64(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv2i32_nxv4i64(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv2i32_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei64.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv2i32.nxv4i64(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv2i32.nxv64i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 64 x i8>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv2i32.nxv64i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 64 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg7_nxv2i32_nxv64i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv2i32_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv2i32.nxv64i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 64 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv2i32_nxv64i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv2i32_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv2i32.nxv64i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv2i32.nxv4i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i16>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv2i32.nxv4i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg7_nxv2i32_nxv4i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv2i32_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv2i32.nxv4i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv2i32_nxv4i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv2i32_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv2i32.nxv4i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv2i32.nxv8i64(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i64>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv2i32.nxv8i64(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i64>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg7_nxv2i32_nxv8i64(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv2i32_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei64.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv2i32.nxv8i64(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv2i32_nxv8i64(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv2i32_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei64.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv2i32.nxv8i64(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv2i32.nxv1i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv2i32.nxv1i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg7_nxv2i32_nxv1i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv2i32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv2i32.nxv1i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv2i32_nxv1i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv2i32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv2i32.nxv1i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv2i32.nxv2i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i8>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv2i32.nxv2i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg7_nxv2i32_nxv2i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv2i32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv2i32.nxv2i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv2i32_nxv2i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv2i32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv2i32.nxv2i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv2i32.nxv8i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i32>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv2i32.nxv8i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg7_nxv2i32_nxv8i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv2i32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei32.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv2i32.nxv8i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv2i32_nxv8i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv2i32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei32.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv2i32.nxv8i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv2i32.nxv32i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 32 x i8>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv2i32.nxv32i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 32 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg7_nxv2i32_nxv32i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv2i32_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv2i32.nxv32i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv2i32_nxv32i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv2i32_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv2i32.nxv32i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv2i32.nxv16i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i32>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv2i32.nxv16i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg7_nxv2i32_nxv16i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv2i32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei32.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv2i32.nxv16i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv2i32_nxv16i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv2i32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei32.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv2i32.nxv16i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv2i32.nxv2i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i16>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv2i32.nxv2i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg7_nxv2i32_nxv2i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv2i32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv2i32.nxv2i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv2i32_nxv2i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv2i32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv2i32.nxv2i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv2i32.nxv2i64(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i64>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv2i32.nxv2i64(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg7_nxv2i32_nxv2i64(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv2i32_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei64.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv2i32.nxv2i64(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv2i32_nxv2i64(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv2i32_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei64.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv2i32.nxv2i64(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv2i32.nxv16i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i16>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv2i32.nxv16i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg8_nxv2i32_nxv16i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv2i32_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv2i32.nxv16i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv2i32_nxv16i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv2i32_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv2i32.nxv16i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv2i32.nxv32i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 32 x i16>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv2i32.nxv32i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 32 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg8_nxv2i32_nxv32i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv2i32_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vmv1r.v v23, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv2i32.nxv32i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv2i32_nxv32i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv2i32_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vmv1r.v v23, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv2i32.nxv32i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv2i32.nxv4i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i32>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv2i32.nxv4i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg8_nxv2i32_nxv4i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv2i32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei32.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv2i32.nxv4i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv2i32_nxv4i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv2i32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei32.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv2i32.nxv4i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv2i32.nxv16i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i8>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv2i32.nxv16i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg8_nxv2i32_nxv16i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv2i32_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv2i32.nxv16i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv2i32_nxv16i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv2i32_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv2i32.nxv16i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv2i32.nxv1i64(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv2i32.nxv1i64(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i64>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg8_nxv2i32_nxv1i64(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv2i32_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei64.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv2i32.nxv1i64(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv2i32_nxv1i64(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv2i32_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei64.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv2i32.nxv1i64(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv2i32.nxv1i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv2i32.nxv1i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg8_nxv2i32_nxv1i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv2i32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv2i32.nxv1i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv2i32_nxv1i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv2i32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv2i32.nxv1i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv2i32.nxv8i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i16>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv2i32.nxv8i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg8_nxv2i32_nxv8i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv2i32_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv2i32.nxv8i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv2i32_nxv8i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv2i32_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv2i32.nxv8i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv2i32.nxv4i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i8>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv2i32.nxv4i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg8_nxv2i32_nxv4i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv2i32_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv2i32.nxv4i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv2i32_nxv4i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv2i32_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv2i32.nxv4i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv2i32.nxv1i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv2i32.nxv1i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg8_nxv2i32_nxv1i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv2i32_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv2i32.nxv1i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv2i32_nxv1i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv2i32_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv2i32.nxv1i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv2i32.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i32>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv2i32.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg8_nxv2i32_nxv2i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv2i32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv2i32.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv2i32_nxv2i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv2i32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv2i32.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv2i32.nxv8i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i8>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv2i32.nxv8i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg8_nxv2i32_nxv8i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv2i32_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv2i32.nxv8i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv2i32_nxv8i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv2i32_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv2i32.nxv8i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv2i32.nxv4i64(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i64>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv2i32.nxv4i64(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i64>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg8_nxv2i32_nxv4i64(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv2i32_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei64.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv2i32.nxv4i64(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv2i32_nxv4i64(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv2i32_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei64.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv2i32.nxv4i64(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv2i32.nxv64i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 64 x i8>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv2i32.nxv64i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 64 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg8_nxv2i32_nxv64i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv2i32_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vmv1r.v v23, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv2i32.nxv64i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 64 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv2i32_nxv64i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv2i32_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vmv1r.v v23, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv2i32.nxv64i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv2i32.nxv4i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i16>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv2i32.nxv4i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 4 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg8_nxv2i32_nxv4i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv2i32_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv2i32.nxv4i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv2i32_nxv4i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv2i32_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv2i32.nxv4i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv2i32.nxv8i64(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i64>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv2i32.nxv8i64(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i64>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg8_nxv2i32_nxv8i64(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv2i32_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vmv1r.v v23, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei64.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv2i32.nxv8i64(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv2i32_nxv8i64(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv2i32_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vmv1r.v v23, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei64.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv2i32.nxv8i64(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv2i32.nxv1i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv2i32.nxv1i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 1 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg8_nxv2i32_nxv1i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv2i32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv2i32.nxv1i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv2i32_nxv1i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv2i32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv2i32.nxv1i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv2i32.nxv2i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i8>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv2i32.nxv2i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg8_nxv2i32_nxv2i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv2i32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv2i32.nxv2i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv2i32_nxv2i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv2i32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv2i32.nxv2i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv2i32.nxv8i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i32>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv2i32.nxv8i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 8 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg8_nxv2i32_nxv8i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv2i32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei32.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv2i32.nxv8i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv2i32_nxv8i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv2i32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei32.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv2i32.nxv8i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv2i32.nxv32i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 32 x i8>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv2i32.nxv32i8(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 32 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg8_nxv2i32_nxv32i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv2i32_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv2i32.nxv32i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv2i32_nxv32i8(<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv2i32_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv2i32.nxv32i8(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv2i32.nxv16i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i32>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv2i32.nxv16i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 16 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg8_nxv2i32_nxv16i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv2i32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vmv1r.v v23, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei32.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv2i32.nxv16i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv2i32_nxv16i32(<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv2i32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vmv1r.v v23, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei32.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv2i32.nxv16i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv2i32.nxv2i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i16>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv2i32.nxv2i16(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg8_nxv2i32_nxv2i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv2i32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv2i32.nxv2i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv2i32_nxv2i16(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv2i32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv2i32.nxv2i16(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv2i32.nxv2i64(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i64>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv2i32.nxv2i64(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg8_nxv2i32_nxv2i64(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv2i32_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei64.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv2i32.nxv2i64(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv2i32_nxv2i64(<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv2i32_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei64.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv2i32.nxv2i64(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv8i8.nxv16i16(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i16>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv8i8.nxv16i16(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i16>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg2_nxv8i8_nxv16i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv8i8_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv8i8.nxv16i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv8i8_nxv16i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv8i8_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv8i8.nxv16i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv8i8.nxv32i16(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 32 x i16>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv8i8.nxv32i16(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 32 x i16>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg2_nxv8i8_nxv32i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv8i8_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv8i8.nxv32i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv8i8_nxv32i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv8i8_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv8i8.nxv32i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv8i8.nxv4i32(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i32>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv8i8.nxv4i32(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i32>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg2_nxv8i8_nxv4i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv8i8_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv8i8.nxv4i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv8i8_nxv4i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv8i8_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv8i8.nxv4i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv8i8.nxv16i8(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv8i8.nxv16i8(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i8>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg2_nxv8i8_nxv16i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv8i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv8i8.nxv16i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv8i8_nxv16i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv8i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv8i8.nxv16i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv8i8.nxv1i64(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv8i8.nxv1i64(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i64>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg2_nxv8i8_nxv1i64(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv8i8_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv8i8.nxv1i64(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv8i8_nxv1i64(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv8i8_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv8i8.nxv1i64(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv8i8.nxv1i32(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv8i8.nxv1i32(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i32>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg2_nxv8i8_nxv1i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv8i8_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv8i8.nxv1i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv8i8_nxv1i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv8i8_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv8i8.nxv1i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv8i8.nxv8i16(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i16>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv8i8.nxv8i16(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i16>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg2_nxv8i8_nxv8i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv8i8_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv8i8.nxv8i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv8i8_nxv8i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv8i8_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv8i8.nxv8i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv8i8.nxv4i8(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv8i8.nxv4i8(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i8>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg2_nxv8i8_nxv4i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv8i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv8i8.nxv4i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv8i8_nxv4i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv8i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv8i8.nxv4i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv8i8.nxv1i16(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv8i8.nxv1i16(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i16>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg2_nxv8i8_nxv1i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv8i8_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv8i8.nxv1i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv8i8_nxv1i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv8i8_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv8i8.nxv1i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv8i8.nxv2i32(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i32>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv8i8.nxv2i32(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i32>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg2_nxv8i8_nxv2i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv8i8_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv8i8.nxv2i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv8i8_nxv2i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv8i8_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv8i8.nxv2i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv8i8.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv8i8.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i8>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg2_nxv8i8_nxv8i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv8i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv8i8.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv8i8_nxv8i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv8i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv8i8.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv8i8.nxv4i64(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i64>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv8i8.nxv4i64(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i64>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg2_nxv8i8_nxv4i64(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv8i8_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv8i8.nxv4i64(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv8i8_nxv4i64(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv8i8_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv8i8.nxv4i64(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv8i8.nxv64i8(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 64 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv8i8.nxv64i8(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 64 x i8>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg2_nxv8i8_nxv64i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv8i8_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv8i8.nxv64i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv8i8_nxv64i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv8i8_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv8i8.nxv64i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv8i8.nxv4i16(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i16>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv8i8.nxv4i16(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i16>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg2_nxv8i8_nxv4i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv8i8_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv8i8.nxv4i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv8i8_nxv4i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv8i8_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv8i8.nxv4i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv8i8.nxv8i64(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i64>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv8i8.nxv8i64(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i64>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg2_nxv8i8_nxv8i64(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv8i8_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv8i8.nxv8i64(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv8i8_nxv8i64(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv8i8_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv8i8.nxv8i64(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv8i8.nxv1i8(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv8i8.nxv1i8(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i8>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg2_nxv8i8_nxv1i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv8i8_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv8i8.nxv1i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv8i8_nxv1i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv8i8_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv8i8.nxv1i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv8i8.nxv2i8(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv8i8.nxv2i8(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i8>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg2_nxv8i8_nxv2i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv8i8_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv8i8.nxv2i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv8i8_nxv2i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv8i8_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv8i8.nxv2i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv8i8.nxv8i32(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i32>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv8i8.nxv8i32(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i32>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg2_nxv8i8_nxv8i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv8i8_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv8i8.nxv8i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv8i8_nxv8i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv8i8_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv8i8.nxv8i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv8i8.nxv32i8(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 32 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv8i8.nxv32i8(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 32 x i8>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg2_nxv8i8_nxv32i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv8i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv8i8.nxv32i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv8i8_nxv32i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv8i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv8i8.nxv32i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv8i8.nxv16i32(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i32>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv8i8.nxv16i32(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i32>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg2_nxv8i8_nxv16i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv8i8_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv8i8.nxv16i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv8i8_nxv16i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv8i8_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv8i8.nxv16i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv8i8.nxv2i16(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i16>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv8i8.nxv2i16(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i16>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg2_nxv8i8_nxv2i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv8i8_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv8i8.nxv2i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv8i8_nxv2i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv8i8_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv8i8.nxv2i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv8i8.nxv2i64(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i64>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv8i8.nxv2i64(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i64>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg2_nxv8i8_nxv2i64(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv8i8_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv8i8.nxv2i64(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv8i8_nxv2i64(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv8i8_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv8i8.nxv2i64(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv8i8.nxv16i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i16>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv8i8.nxv16i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i16>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg3_nxv8i8_nxv16i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv8i8_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv8i8.nxv16i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv8i8_nxv16i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv8i8_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv8i8.nxv16i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv8i8.nxv32i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 32 x i16>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv8i8.nxv32i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 32 x i16>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg3_nxv8i8_nxv32i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv8i8_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv8i8.nxv32i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv8i8_nxv32i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv8i8_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv8i8.nxv32i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv8i8.nxv4i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i32>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv8i8.nxv4i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i32>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg3_nxv8i8_nxv4i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv8i8_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv8i8.nxv4i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv8i8_nxv4i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv8i8_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv8i8.nxv4i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv8i8.nxv16i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i8>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv8i8.nxv16i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i8>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg3_nxv8i8_nxv16i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv8i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv8i8.nxv16i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv8i8_nxv16i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv8i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv8i8.nxv16i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv8i8.nxv1i64(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv8i8.nxv1i64(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i64>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg3_nxv8i8_nxv1i64(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv8i8_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei64.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv8i8.nxv1i64(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv8i8_nxv1i64(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv8i8_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei64.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv8i8.nxv1i64(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv8i8.nxv1i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv8i8.nxv1i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i32>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg3_nxv8i8_nxv1i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv8i8_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv8i8.nxv1i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv8i8_nxv1i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv8i8_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv8i8.nxv1i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv8i8.nxv8i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i16>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv8i8.nxv8i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i16>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg3_nxv8i8_nxv8i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv8i8_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv8i8.nxv8i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv8i8_nxv8i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv8i8_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv8i8.nxv8i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv8i8.nxv4i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i8>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv8i8.nxv4i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i8>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg3_nxv8i8_nxv4i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv8i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv8i8.nxv4i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv8i8_nxv4i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv8i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv8i8.nxv4i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv8i8.nxv1i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv8i8.nxv1i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i16>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg3_nxv8i8_nxv1i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv8i8_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv8i8.nxv1i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv8i8_nxv1i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv8i8_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv8i8.nxv1i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv8i8.nxv2i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i32>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv8i8.nxv2i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i32>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg3_nxv8i8_nxv2i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv8i8_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv8i8.nxv2i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv8i8_nxv2i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv8i8_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv8i8.nxv2i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv8i8.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i8>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv8i8.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i8>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg3_nxv8i8_nxv8i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv8i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv8i8.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv8i8_nxv8i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv8i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv8i8.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv8i8.nxv4i64(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i64>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv8i8.nxv4i64(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i64>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg3_nxv8i8_nxv4i64(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv8i8_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei64.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv8i8.nxv4i64(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv8i8_nxv4i64(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv8i8_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei64.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv8i8.nxv4i64(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv8i8.nxv64i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 64 x i8>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv8i8.nxv64i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 64 x i8>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg3_nxv8i8_nxv64i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv8i8_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv8i8.nxv64i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv8i8_nxv64i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv8i8_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv8i8.nxv64i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv8i8.nxv4i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i16>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv8i8.nxv4i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i16>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg3_nxv8i8_nxv4i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv8i8_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv8i8.nxv4i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv8i8_nxv4i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv8i8_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv8i8.nxv4i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv8i8.nxv8i64(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i64>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv8i8.nxv8i64(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i64>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg3_nxv8i8_nxv8i64(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv8i8_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei64.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv8i8.nxv8i64(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv8i8_nxv8i64(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv8i8_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei64.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv8i8.nxv8i64(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv8i8.nxv1i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv8i8.nxv1i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i8>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg3_nxv8i8_nxv1i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv8i8_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv8i8.nxv1i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv8i8_nxv1i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv8i8_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv8i8.nxv1i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv8i8.nxv2i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i8>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv8i8.nxv2i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i8>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg3_nxv8i8_nxv2i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv8i8_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv8i8.nxv2i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv8i8_nxv2i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv8i8_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv8i8.nxv2i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv8i8.nxv8i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i32>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv8i8.nxv8i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i32>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg3_nxv8i8_nxv8i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv8i8_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv8i8.nxv8i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv8i8_nxv8i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv8i8_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv8i8.nxv8i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv8i8.nxv32i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 32 x i8>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv8i8.nxv32i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 32 x i8>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg3_nxv8i8_nxv32i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv8i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv8i8.nxv32i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv8i8_nxv32i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv8i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv8i8.nxv32i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv8i8.nxv16i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i32>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv8i8.nxv16i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i32>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg3_nxv8i8_nxv16i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv8i8_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv8i8.nxv16i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv8i8_nxv16i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv8i8_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv8i8.nxv16i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv8i8.nxv2i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i16>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv8i8.nxv2i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i16>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg3_nxv8i8_nxv2i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv8i8_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv8i8.nxv2i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv8i8_nxv2i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv8i8_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv8i8.nxv2i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv8i8.nxv2i64(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i64>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv8i8.nxv2i64(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i64>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg3_nxv8i8_nxv2i64(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv8i8_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei64.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv8i8.nxv2i64(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv8i8_nxv2i64(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv8i8_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei64.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv8i8.nxv2i64(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv8i8.nxv16i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i16>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv8i8.nxv16i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i16>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg4_nxv8i8_nxv16i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv8i8_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv8i8.nxv16i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv8i8_nxv16i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv8i8_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv8i8.nxv16i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv8i8.nxv32i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 32 x i16>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv8i8.nxv32i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 32 x i16>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg4_nxv8i8_nxv32i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv8i8_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv8i8.nxv32i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv8i8_nxv32i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv8i8_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv8i8.nxv32i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv8i8.nxv4i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i32>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv8i8.nxv4i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i32>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg4_nxv8i8_nxv4i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv8i8_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv8i8.nxv4i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv8i8_nxv4i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv8i8_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv8i8.nxv4i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv8i8.nxv16i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i8>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv8i8.nxv16i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i8>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg4_nxv8i8_nxv16i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv8i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv8i8.nxv16i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv8i8_nxv16i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv8i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv8i8.nxv16i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv8i8.nxv1i64(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv8i8.nxv1i64(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i64>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg4_nxv8i8_nxv1i64(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv8i8_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei64.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv8i8.nxv1i64(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv8i8_nxv1i64(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv8i8_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei64.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv8i8.nxv1i64(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv8i8.nxv1i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv8i8.nxv1i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i32>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg4_nxv8i8_nxv1i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv8i8_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv8i8.nxv1i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv8i8_nxv1i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv8i8_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv8i8.nxv1i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv8i8.nxv8i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i16>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv8i8.nxv8i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i16>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg4_nxv8i8_nxv8i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv8i8_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv8i8.nxv8i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv8i8_nxv8i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv8i8_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv8i8.nxv8i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv8i8.nxv4i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i8>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv8i8.nxv4i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i8>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg4_nxv8i8_nxv4i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv8i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv8i8.nxv4i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv8i8_nxv4i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv8i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv8i8.nxv4i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv8i8.nxv1i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv8i8.nxv1i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i16>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg4_nxv8i8_nxv1i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv8i8_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv8i8.nxv1i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv8i8_nxv1i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv8i8_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv8i8.nxv1i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv8i8.nxv2i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i32>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv8i8.nxv2i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i32>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg4_nxv8i8_nxv2i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv8i8_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv8i8.nxv2i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv8i8_nxv2i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv8i8_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv8i8.nxv2i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv8i8.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i8>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv8i8.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i8>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg4_nxv8i8_nxv8i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv8i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv8i8.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv8i8_nxv8i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv8i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv8i8.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv8i8.nxv4i64(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i64>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv8i8.nxv4i64(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i64>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg4_nxv8i8_nxv4i64(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv8i8_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei64.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv8i8.nxv4i64(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv8i8_nxv4i64(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv8i8_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei64.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv8i8.nxv4i64(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv8i8.nxv64i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 64 x i8>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv8i8.nxv64i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 64 x i8>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg4_nxv8i8_nxv64i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv8i8_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv8i8.nxv64i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv8i8_nxv64i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv8i8_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv8i8.nxv64i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv8i8.nxv4i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i16>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv8i8.nxv4i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i16>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg4_nxv8i8_nxv4i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv8i8_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv8i8.nxv4i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv8i8_nxv4i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv8i8_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv8i8.nxv4i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv8i8.nxv8i64(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i64>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv8i8.nxv8i64(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i64>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg4_nxv8i8_nxv8i64(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv8i8_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei64.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv8i8.nxv8i64(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv8i8_nxv8i64(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv8i8_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei64.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv8i8.nxv8i64(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv8i8.nxv1i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv8i8.nxv1i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i8>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg4_nxv8i8_nxv1i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv8i8_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv8i8.nxv1i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv8i8_nxv1i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv8i8_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv8i8.nxv1i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv8i8.nxv2i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i8>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv8i8.nxv2i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i8>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg4_nxv8i8_nxv2i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv8i8_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv8i8.nxv2i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv8i8_nxv2i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv8i8_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv8i8.nxv2i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv8i8.nxv8i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i32>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv8i8.nxv8i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i32>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg4_nxv8i8_nxv8i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv8i8_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv8i8.nxv8i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv8i8_nxv8i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv8i8_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv8i8.nxv8i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv8i8.nxv32i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 32 x i8>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv8i8.nxv32i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 32 x i8>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg4_nxv8i8_nxv32i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv8i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv8i8.nxv32i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv8i8_nxv32i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv8i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv8i8.nxv32i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv8i8.nxv16i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i32>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv8i8.nxv16i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i32>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg4_nxv8i8_nxv16i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv8i8_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv8i8.nxv16i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv8i8_nxv16i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv8i8_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv8i8.nxv16i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv8i8.nxv2i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i16>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv8i8.nxv2i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i16>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg4_nxv8i8_nxv2i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv8i8_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv8i8.nxv2i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv8i8_nxv2i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv8i8_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv8i8.nxv2i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv8i8.nxv2i64(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i64>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv8i8.nxv2i64(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i64>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg4_nxv8i8_nxv2i64(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv8i8_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei64.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv8i8.nxv2i64(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv8i8_nxv2i64(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv8i8_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei64.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv8i8.nxv2i64(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv8i8.nxv16i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i16>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv8i8.nxv16i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i16>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg5_nxv8i8_nxv16i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv8i8_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv8i8.nxv16i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv8i8_nxv16i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv8i8_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv8i8.nxv16i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv8i8.nxv32i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 32 x i16>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv8i8.nxv32i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 32 x i16>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg5_nxv8i8_nxv32i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv8i8_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv8i8.nxv32i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv8i8_nxv32i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv8i8_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv8i8.nxv32i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv8i8.nxv4i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i32>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv8i8.nxv4i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i32>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg5_nxv8i8_nxv4i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv8i8_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei32.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv8i8.nxv4i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv8i8_nxv4i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv8i8_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei32.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv8i8.nxv4i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv8i8.nxv16i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i8>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv8i8.nxv16i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i8>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg5_nxv8i8_nxv16i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv8i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv8i8.nxv16i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv8i8_nxv16i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv8i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv8i8.nxv16i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv8i8.nxv1i64(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv8i8.nxv1i64(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i64>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg5_nxv8i8_nxv1i64(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv8i8_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei64.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv8i8.nxv1i64(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv8i8_nxv1i64(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv8i8_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei64.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv8i8.nxv1i64(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv8i8.nxv1i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv8i8.nxv1i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i32>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg5_nxv8i8_nxv1i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv8i8_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv8i8.nxv1i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv8i8_nxv1i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv8i8_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv8i8.nxv1i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv8i8.nxv8i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i16>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv8i8.nxv8i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i16>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg5_nxv8i8_nxv8i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv8i8_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv8i8.nxv8i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv8i8_nxv8i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv8i8_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv8i8.nxv8i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv8i8.nxv4i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i8>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv8i8.nxv4i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i8>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg5_nxv8i8_nxv4i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv8i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv8i8.nxv4i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv8i8_nxv4i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv8i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv8i8.nxv4i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv8i8.nxv1i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv8i8.nxv1i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i16>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg5_nxv8i8_nxv1i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv8i8_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv8i8.nxv1i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv8i8_nxv1i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv8i8_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv8i8.nxv1i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv8i8.nxv2i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i32>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv8i8.nxv2i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i32>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg5_nxv8i8_nxv2i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv8i8_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv8i8.nxv2i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv8i8_nxv2i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv8i8_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv8i8.nxv2i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv8i8.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i8>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv8i8.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i8>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg5_nxv8i8_nxv8i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv8i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv8i8.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv8i8_nxv8i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv8i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv8i8.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv8i8.nxv4i64(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i64>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv8i8.nxv4i64(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i64>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg5_nxv8i8_nxv4i64(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv8i8_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei64.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv8i8.nxv4i64(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv8i8_nxv4i64(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv8i8_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei64.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv8i8.nxv4i64(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv8i8.nxv64i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 64 x i8>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv8i8.nxv64i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 64 x i8>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg5_nxv8i8_nxv64i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv8i8_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv8i8.nxv64i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv8i8_nxv64i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv8i8_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv8i8.nxv64i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv8i8.nxv4i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i16>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv8i8.nxv4i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i16>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg5_nxv8i8_nxv4i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv8i8_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv8i8.nxv4i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv8i8_nxv4i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv8i8_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv8i8.nxv4i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv8i8.nxv8i64(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i64>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv8i8.nxv8i64(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i64>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg5_nxv8i8_nxv8i64(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv8i8_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei64.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv8i8.nxv8i64(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv8i8_nxv8i64(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv8i8_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei64.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv8i8.nxv8i64(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv8i8.nxv1i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv8i8.nxv1i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i8>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg5_nxv8i8_nxv1i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv8i8_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv8i8.nxv1i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv8i8_nxv1i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv8i8_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv8i8.nxv1i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv8i8.nxv2i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i8>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv8i8.nxv2i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i8>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg5_nxv8i8_nxv2i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv8i8_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv8i8.nxv2i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv8i8_nxv2i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv8i8_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv8i8.nxv2i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv8i8.nxv8i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i32>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv8i8.nxv8i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i32>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg5_nxv8i8_nxv8i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv8i8_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei32.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv8i8.nxv8i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv8i8_nxv8i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv8i8_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei32.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv8i8.nxv8i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv8i8.nxv32i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 32 x i8>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv8i8.nxv32i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 32 x i8>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg5_nxv8i8_nxv32i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv8i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv8i8.nxv32i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv8i8_nxv32i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv8i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv8i8.nxv32i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv8i8.nxv16i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i32>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv8i8.nxv16i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i32>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg5_nxv8i8_nxv16i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv8i8_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei32.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv8i8.nxv16i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv8i8_nxv16i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv8i8_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei32.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv8i8.nxv16i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv8i8.nxv2i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i16>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv8i8.nxv2i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i16>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg5_nxv8i8_nxv2i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv8i8_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv8i8.nxv2i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv8i8_nxv2i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv8i8_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv8i8.nxv2i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv8i8.nxv2i64(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i64>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv8i8.nxv2i64(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i64>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg5_nxv8i8_nxv2i64(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv8i8_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei64.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv8i8.nxv2i64(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv8i8_nxv2i64(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv8i8_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei64.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv8i8.nxv2i64(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv8i8.nxv16i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i16>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv8i8.nxv16i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i16>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg6_nxv8i8_nxv16i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv8i8_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv8i8.nxv16i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv8i8_nxv16i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv8i8_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv8i8.nxv16i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv8i8.nxv32i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 32 x i16>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv8i8.nxv32i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 32 x i16>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg6_nxv8i8_nxv32i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv8i8_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv8i8.nxv32i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv8i8_nxv32i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv8i8_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv8i8.nxv32i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv8i8.nxv4i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i32>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv8i8.nxv4i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i32>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg6_nxv8i8_nxv4i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv8i8_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei32.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv8i8.nxv4i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv8i8_nxv4i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv8i8_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei32.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv8i8.nxv4i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv8i8.nxv16i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i8>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv8i8.nxv16i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i8>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg6_nxv8i8_nxv16i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv8i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv8i8.nxv16i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv8i8_nxv16i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv8i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv8i8.nxv16i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv8i8.nxv1i64(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv8i8.nxv1i64(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i64>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg6_nxv8i8_nxv1i64(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv8i8_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei64.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv8i8.nxv1i64(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv8i8_nxv1i64(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv8i8_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei64.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv8i8.nxv1i64(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv8i8.nxv1i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv8i8.nxv1i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i32>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg6_nxv8i8_nxv1i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv8i8_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv8i8.nxv1i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv8i8_nxv1i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv8i8_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv8i8.nxv1i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv8i8.nxv8i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i16>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv8i8.nxv8i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i16>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg6_nxv8i8_nxv8i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv8i8_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv8i8.nxv8i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv8i8_nxv8i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv8i8_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv8i8.nxv8i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv8i8.nxv4i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i8>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv8i8.nxv4i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i8>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg6_nxv8i8_nxv4i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv8i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv8i8.nxv4i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv8i8_nxv4i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv8i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv8i8.nxv4i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv8i8.nxv1i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv8i8.nxv1i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i16>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg6_nxv8i8_nxv1i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv8i8_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv8i8.nxv1i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv8i8_nxv1i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv8i8_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv8i8.nxv1i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv8i8.nxv2i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i32>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv8i8.nxv2i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i32>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg6_nxv8i8_nxv2i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv8i8_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv8i8.nxv2i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv8i8_nxv2i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv8i8_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv8i8.nxv2i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv8i8.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i8>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv8i8.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i8>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg6_nxv8i8_nxv8i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv8i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv8i8.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv8i8_nxv8i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv8i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv8i8.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv8i8.nxv4i64(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i64>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv8i8.nxv4i64(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i64>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg6_nxv8i8_nxv4i64(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv8i8_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei64.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv8i8.nxv4i64(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv8i8_nxv4i64(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv8i8_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei64.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv8i8.nxv4i64(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv8i8.nxv64i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 64 x i8>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv8i8.nxv64i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 64 x i8>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg6_nxv8i8_nxv64i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv8i8_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv8i8.nxv64i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv8i8_nxv64i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv8i8_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv8i8.nxv64i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv8i8.nxv4i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i16>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv8i8.nxv4i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i16>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg6_nxv8i8_nxv4i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv8i8_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv8i8.nxv4i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv8i8_nxv4i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv8i8_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv8i8.nxv4i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv8i8.nxv8i64(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i64>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv8i8.nxv8i64(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i64>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg6_nxv8i8_nxv8i64(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv8i8_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei64.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv8i8.nxv8i64(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv8i8_nxv8i64(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv8i8_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei64.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv8i8.nxv8i64(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv8i8.nxv1i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv8i8.nxv1i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i8>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg6_nxv8i8_nxv1i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv8i8_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv8i8.nxv1i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv8i8_nxv1i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv8i8_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv8i8.nxv1i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv8i8.nxv2i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i8>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv8i8.nxv2i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i8>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg6_nxv8i8_nxv2i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv8i8_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv8i8.nxv2i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv8i8_nxv2i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv8i8_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv8i8.nxv2i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv8i8.nxv8i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i32>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv8i8.nxv8i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i32>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg6_nxv8i8_nxv8i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv8i8_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei32.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv8i8.nxv8i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv8i8_nxv8i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv8i8_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei32.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv8i8.nxv8i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv8i8.nxv32i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 32 x i8>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv8i8.nxv32i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 32 x i8>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg6_nxv8i8_nxv32i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv8i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv8i8.nxv32i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv8i8_nxv32i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv8i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv8i8.nxv32i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv8i8.nxv16i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i32>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv8i8.nxv16i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i32>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg6_nxv8i8_nxv16i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv8i8_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei32.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv8i8.nxv16i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv8i8_nxv16i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv8i8_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei32.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv8i8.nxv16i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv8i8.nxv2i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i16>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv8i8.nxv2i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i16>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg6_nxv8i8_nxv2i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv8i8_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv8i8.nxv2i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv8i8_nxv2i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv8i8_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv8i8.nxv2i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv8i8.nxv2i64(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i64>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv8i8.nxv2i64(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i64>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg6_nxv8i8_nxv2i64(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv8i8_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei64.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv8i8.nxv2i64(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv8i8_nxv2i64(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv8i8_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei64.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv8i8.nxv2i64(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv8i8.nxv16i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i16>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv8i8.nxv16i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i16>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg7_nxv8i8_nxv16i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv8i8_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv8i8.nxv16i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv8i8_nxv16i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv8i8_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv8i8.nxv16i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv8i8.nxv32i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 32 x i16>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv8i8.nxv32i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 32 x i16>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg7_nxv8i8_nxv32i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv8i8_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv8i8.nxv32i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv8i8_nxv32i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv8i8_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv8i8.nxv32i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv8i8.nxv4i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i32>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv8i8.nxv4i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i32>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg7_nxv8i8_nxv4i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv8i8_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei32.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv8i8.nxv4i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv8i8_nxv4i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv8i8_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei32.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv8i8.nxv4i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv8i8.nxv16i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i8>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv8i8.nxv16i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i8>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg7_nxv8i8_nxv16i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv8i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv8i8.nxv16i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv8i8_nxv16i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv8i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv8i8.nxv16i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv8i8.nxv1i64(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv8i8.nxv1i64(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i64>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg7_nxv8i8_nxv1i64(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv8i8_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei64.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv8i8.nxv1i64(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv8i8_nxv1i64(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv8i8_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei64.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv8i8.nxv1i64(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv8i8.nxv1i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv8i8.nxv1i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i32>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg7_nxv8i8_nxv1i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv8i8_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv8i8.nxv1i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv8i8_nxv1i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv8i8_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv8i8.nxv1i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv8i8.nxv8i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i16>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv8i8.nxv8i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i16>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg7_nxv8i8_nxv8i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv8i8_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv8i8.nxv8i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv8i8_nxv8i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv8i8_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv8i8.nxv8i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv8i8.nxv4i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i8>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv8i8.nxv4i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i8>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg7_nxv8i8_nxv4i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv8i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv8i8.nxv4i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv8i8_nxv4i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv8i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv8i8.nxv4i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv8i8.nxv1i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv8i8.nxv1i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i16>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg7_nxv8i8_nxv1i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv8i8_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv8i8.nxv1i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv8i8_nxv1i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv8i8_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv8i8.nxv1i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv8i8.nxv2i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i32>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv8i8.nxv2i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i32>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg7_nxv8i8_nxv2i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv8i8_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv8i8.nxv2i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv8i8_nxv2i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv8i8_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv8i8.nxv2i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv8i8.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i8>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv8i8.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i8>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg7_nxv8i8_nxv8i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv8i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv8i8.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv8i8_nxv8i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv8i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv8i8.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv8i8.nxv4i64(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i64>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv8i8.nxv4i64(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i64>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg7_nxv8i8_nxv4i64(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv8i8_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei64.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv8i8.nxv4i64(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv8i8_nxv4i64(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv8i8_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei64.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv8i8.nxv4i64(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv8i8.nxv64i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 64 x i8>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv8i8.nxv64i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 64 x i8>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg7_nxv8i8_nxv64i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv8i8_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv8i8.nxv64i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv8i8_nxv64i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv8i8_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv8i8.nxv64i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv8i8.nxv4i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i16>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv8i8.nxv4i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i16>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg7_nxv8i8_nxv4i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv8i8_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv8i8.nxv4i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv8i8_nxv4i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv8i8_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv8i8.nxv4i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv8i8.nxv8i64(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i64>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv8i8.nxv8i64(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i64>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg7_nxv8i8_nxv8i64(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv8i8_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei64.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv8i8.nxv8i64(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv8i8_nxv8i64(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv8i8_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei64.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv8i8.nxv8i64(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv8i8.nxv1i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv8i8.nxv1i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i8>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg7_nxv8i8_nxv1i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv8i8_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv8i8.nxv1i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv8i8_nxv1i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv8i8_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv8i8.nxv1i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv8i8.nxv2i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i8>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv8i8.nxv2i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i8>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg7_nxv8i8_nxv2i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv8i8_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv8i8.nxv2i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv8i8_nxv2i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv8i8_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv8i8.nxv2i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv8i8.nxv8i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i32>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv8i8.nxv8i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i32>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg7_nxv8i8_nxv8i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv8i8_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei32.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv8i8.nxv8i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv8i8_nxv8i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv8i8_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei32.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv8i8.nxv8i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv8i8.nxv32i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 32 x i8>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv8i8.nxv32i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 32 x i8>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg7_nxv8i8_nxv32i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv8i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv8i8.nxv32i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv8i8_nxv32i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv8i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv8i8.nxv32i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv8i8.nxv16i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i32>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv8i8.nxv16i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i32>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg7_nxv8i8_nxv16i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv8i8_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei32.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv8i8.nxv16i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv8i8_nxv16i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv8i8_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei32.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv8i8.nxv16i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv8i8.nxv2i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i16>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv8i8.nxv2i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i16>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg7_nxv8i8_nxv2i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv8i8_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv8i8.nxv2i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv8i8_nxv2i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv8i8_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv8i8.nxv2i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv8i8.nxv2i64(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i64>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv8i8.nxv2i64(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i64>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg7_nxv8i8_nxv2i64(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv8i8_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei64.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv8i8.nxv2i64(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv8i8_nxv2i64(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv8i8_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei64.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv8i8.nxv2i64(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv8i8.nxv16i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i16>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv8i8.nxv16i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i16>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg8_nxv8i8_nxv16i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv8i8_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv8i8.nxv16i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv8i8_nxv16i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv8i8_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv8i8.nxv16i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv8i8.nxv32i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 32 x i16>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv8i8.nxv32i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 32 x i16>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg8_nxv8i8_nxv32i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv8i8_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vmv1r.v v23, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv8i8.nxv32i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv8i8_nxv32i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv8i8_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vmv1r.v v23, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv8i8.nxv32i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv8i8.nxv4i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i32>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv8i8.nxv4i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i32>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg8_nxv8i8_nxv4i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv8i8_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei32.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv8i8.nxv4i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv8i8_nxv4i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv8i8_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei32.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv8i8.nxv4i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv8i8.nxv16i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i8>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv8i8.nxv16i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i8>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg8_nxv8i8_nxv16i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv8i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv8i8.nxv16i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv8i8_nxv16i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv8i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv8i8.nxv16i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv8i8.nxv1i64(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv8i8.nxv1i64(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i64>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg8_nxv8i8_nxv1i64(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv8i8_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei64.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv8i8.nxv1i64(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv8i8_nxv1i64(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv8i8_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei64.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv8i8.nxv1i64(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv8i8.nxv1i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv8i8.nxv1i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i32>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg8_nxv8i8_nxv1i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv8i8_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv8i8.nxv1i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv8i8_nxv1i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv8i8_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv8i8.nxv1i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv8i8.nxv8i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i16>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv8i8.nxv8i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i16>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg8_nxv8i8_nxv8i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv8i8_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv8i8.nxv8i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv8i8_nxv8i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv8i8_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv8i8.nxv8i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv8i8.nxv4i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i8>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv8i8.nxv4i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i8>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg8_nxv8i8_nxv4i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv8i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv8i8.nxv4i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv8i8_nxv4i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv8i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv8i8.nxv4i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv8i8.nxv1i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv8i8.nxv1i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i16>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg8_nxv8i8_nxv1i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv8i8_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv8i8.nxv1i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv8i8_nxv1i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv8i8_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv8i8.nxv1i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv8i8.nxv2i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i32>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv8i8.nxv2i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i32>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg8_nxv8i8_nxv2i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv8i8_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv8i8.nxv2i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv8i8_nxv2i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv8i8_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv8i8.nxv2i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv8i8.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i8>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv8i8.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i8>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg8_nxv8i8_nxv8i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv8i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv8i8.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv8i8_nxv8i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv8i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv8i8.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv8i8.nxv4i64(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i64>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv8i8.nxv4i64(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i64>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg8_nxv8i8_nxv4i64(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv8i8_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei64.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv8i8.nxv4i64(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv8i8_nxv4i64(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv8i8_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei64.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv8i8.nxv4i64(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv8i8.nxv64i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 64 x i8>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv8i8.nxv64i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 64 x i8>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg8_nxv8i8_nxv64i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv8i8_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vmv1r.v v23, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv8i8.nxv64i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv8i8_nxv64i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv8i8_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vmv1r.v v23, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv8i8.nxv64i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv8i8.nxv4i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i16>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv8i8.nxv4i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 4 x i16>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg8_nxv8i8_nxv4i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv8i8_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv8i8.nxv4i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv8i8_nxv4i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv8i8_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv8i8.nxv4i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv8i8.nxv8i64(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i64>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv8i8.nxv8i64(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i64>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg8_nxv8i8_nxv8i64(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv8i8_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vmv1r.v v23, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei64.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv8i8.nxv8i64(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv8i8_nxv8i64(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv8i8_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vmv1r.v v23, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei64.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv8i8.nxv8i64(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv8i8.nxv1i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv8i8.nxv1i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 1 x i8>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg8_nxv8i8_nxv1i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv8i8_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv8i8.nxv1i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv8i8_nxv1i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv8i8_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv8i8.nxv1i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv8i8.nxv2i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i8>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv8i8.nxv2i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i8>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg8_nxv8i8_nxv2i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv8i8_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv8i8.nxv2i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv8i8_nxv2i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv8i8_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv8i8.nxv2i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv8i8.nxv8i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i32>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv8i8.nxv8i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i32>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg8_nxv8i8_nxv8i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv8i8_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei32.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv8i8.nxv8i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv8i8_nxv8i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv8i8_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei32.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv8i8.nxv8i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv8i8.nxv32i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 32 x i8>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv8i8.nxv32i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 32 x i8>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg8_nxv8i8_nxv32i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv8i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv8i8.nxv32i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv8i8_nxv32i8(<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv8i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv8i8.nxv32i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv8i8.nxv16i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i32>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv8i8.nxv16i32(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 16 x i32>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg8_nxv8i8_nxv16i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv8i8_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vmv1r.v v23, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei32.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv8i8.nxv16i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv8i8_nxv16i32(<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv8i8_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vmv1r.v v23, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei32.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv8i8.nxv16i32(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv8i8.nxv2i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i16>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv8i8.nxv2i16(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i16>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg8_nxv8i8_nxv2i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv8i8_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv8i8.nxv2i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv8i8_nxv2i16(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv8i8_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv8i8.nxv2i16(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv8i8.nxv2i64(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i64>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv8i8.nxv2i64(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 2 x i64>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg8_nxv8i8_nxv2i64(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv8i8_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei64.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv8i8.nxv2i64(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv8i8_nxv2i64(<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv8i8_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei64.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv8i8.nxv2i64(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 2 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv4i64.nxv16i16(<vscale x 4 x i64>,<vscale x 4 x i64>, i64*, <vscale x 16 x i16>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv4i64.nxv16i16(<vscale x 4 x i64>,<vscale x 4 x i64>, i64*, <vscale x 16 x i16>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg2_nxv4i64_nxv16i16(<vscale x 4 x i64> %val, i64* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv4i64_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv4r.v v28, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v28
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv4i64.nxv16i16(<vscale x 4 x i64> %val,<vscale x 4 x i64> %val, i64* %base, <vscale x 16 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv4i64_nxv16i16(<vscale x 4 x i64> %val, i64* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv4i64_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv4r.v v28, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v28, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv4i64.nxv16i16(<vscale x 4 x i64> %val,<vscale x 4 x i64> %val, i64* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv4i64.nxv32i16(<vscale x 4 x i64>,<vscale x 4 x i64>, i64*, <vscale x 32 x i16>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv4i64.nxv32i16(<vscale x 4 x i64>,<vscale x 4 x i64>, i64*, <vscale x 32 x i16>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg2_nxv4i64_nxv32i16(<vscale x 4 x i64> %val, i64* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv4i64_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e64,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv4i64.nxv32i16(<vscale x 4 x i64> %val,<vscale x 4 x i64> %val, i64* %base, <vscale x 32 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv4i64_nxv32i16(<vscale x 4 x i64> %val, i64* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv4i64_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e64,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv4i64.nxv32i16(<vscale x 4 x i64> %val,<vscale x 4 x i64> %val, i64* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv4i64.nxv4i32(<vscale x 4 x i64>,<vscale x 4 x i64>, i64*, <vscale x 4 x i32>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv4i64.nxv4i32(<vscale x 4 x i64>,<vscale x 4 x i64>, i64*, <vscale x 4 x i32>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg2_nxv4i64_nxv4i32(<vscale x 4 x i64> %val, i64* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv4i64_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv2r.v v26, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v26
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv4i64.nxv4i32(<vscale x 4 x i64> %val,<vscale x 4 x i64> %val, i64* %base, <vscale x 4 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv4i64_nxv4i32(<vscale x 4 x i64> %val, i64* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv4i64_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv2r.v v26, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v26, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv4i64.nxv4i32(<vscale x 4 x i64> %val,<vscale x 4 x i64> %val, i64* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv4i64.nxv16i8(<vscale x 4 x i64>,<vscale x 4 x i64>, i64*, <vscale x 16 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv4i64.nxv16i8(<vscale x 4 x i64>,<vscale x 4 x i64>, i64*, <vscale x 16 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg2_nxv4i64_nxv16i8(<vscale x 4 x i64> %val, i64* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv4i64_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv2r.v v26, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v26
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv4i64.nxv16i8(<vscale x 4 x i64> %val,<vscale x 4 x i64> %val, i64* %base, <vscale x 16 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv4i64_nxv16i8(<vscale x 4 x i64> %val, i64* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv4i64_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv2r.v v26, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v26, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv4i64.nxv16i8(<vscale x 4 x i64> %val,<vscale x 4 x i64> %val, i64* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv4i64.nxv1i64(<vscale x 4 x i64>,<vscale x 4 x i64>, i64*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv4i64.nxv1i64(<vscale x 4 x i64>,<vscale x 4 x i64>, i64*, <vscale x 1 x i64>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg2_nxv4i64_nxv1i64(<vscale x 4 x i64> %val, i64* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv4i64_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv1r.v v25, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv4i64.nxv1i64(<vscale x 4 x i64> %val,<vscale x 4 x i64> %val, i64* %base, <vscale x 1 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv4i64_nxv1i64(<vscale x 4 x i64> %val, i64* %base, <vscale x 1 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv4i64_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv1r.v v25, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv4i64.nxv1i64(<vscale x 4 x i64> %val,<vscale x 4 x i64> %val, i64* %base, <vscale x 1 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv4i64.nxv1i32(<vscale x 4 x i64>,<vscale x 4 x i64>, i64*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv4i64.nxv1i32(<vscale x 4 x i64>,<vscale x 4 x i64>, i64*, <vscale x 1 x i32>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg2_nxv4i64_nxv1i32(<vscale x 4 x i64> %val, i64* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv4i64_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv1r.v v25, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv4i64.nxv1i32(<vscale x 4 x i64> %val,<vscale x 4 x i64> %val, i64* %base, <vscale x 1 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv4i64_nxv1i32(<vscale x 4 x i64> %val, i64* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv4i64_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv1r.v v25, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv4i64.nxv1i32(<vscale x 4 x i64> %val,<vscale x 4 x i64> %val, i64* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv4i64.nxv8i16(<vscale x 4 x i64>,<vscale x 4 x i64>, i64*, <vscale x 8 x i16>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv4i64.nxv8i16(<vscale x 4 x i64>,<vscale x 4 x i64>, i64*, <vscale x 8 x i16>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg2_nxv4i64_nxv8i16(<vscale x 4 x i64> %val, i64* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv4i64_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv2r.v v26, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v26
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv4i64.nxv8i16(<vscale x 4 x i64> %val,<vscale x 4 x i64> %val, i64* %base, <vscale x 8 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv4i64_nxv8i16(<vscale x 4 x i64> %val, i64* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv4i64_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv2r.v v26, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v26, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv4i64.nxv8i16(<vscale x 4 x i64> %val,<vscale x 4 x i64> %val, i64* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv4i64.nxv4i8(<vscale x 4 x i64>,<vscale x 4 x i64>, i64*, <vscale x 4 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv4i64.nxv4i8(<vscale x 4 x i64>,<vscale x 4 x i64>, i64*, <vscale x 4 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg2_nxv4i64_nxv4i8(<vscale x 4 x i64> %val, i64* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv4i64_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv1r.v v25, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv4i64.nxv4i8(<vscale x 4 x i64> %val,<vscale x 4 x i64> %val, i64* %base, <vscale x 4 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv4i64_nxv4i8(<vscale x 4 x i64> %val, i64* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv4i64_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv1r.v v25, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv4i64.nxv4i8(<vscale x 4 x i64> %val,<vscale x 4 x i64> %val, i64* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv4i64.nxv1i16(<vscale x 4 x i64>,<vscale x 4 x i64>, i64*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv4i64.nxv1i16(<vscale x 4 x i64>,<vscale x 4 x i64>, i64*, <vscale x 1 x i16>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg2_nxv4i64_nxv1i16(<vscale x 4 x i64> %val, i64* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv4i64_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv1r.v v25, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv4i64.nxv1i16(<vscale x 4 x i64> %val,<vscale x 4 x i64> %val, i64* %base, <vscale x 1 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv4i64_nxv1i16(<vscale x 4 x i64> %val, i64* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv4i64_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv1r.v v25, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv4i64.nxv1i16(<vscale x 4 x i64> %val,<vscale x 4 x i64> %val, i64* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv4i64.nxv2i32(<vscale x 4 x i64>,<vscale x 4 x i64>, i64*, <vscale x 2 x i32>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv4i64.nxv2i32(<vscale x 4 x i64>,<vscale x 4 x i64>, i64*, <vscale x 2 x i32>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg2_nxv4i64_nxv2i32(<vscale x 4 x i64> %val, i64* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv4i64_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv1r.v v25, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv4i64.nxv2i32(<vscale x 4 x i64> %val,<vscale x 4 x i64> %val, i64* %base, <vscale x 2 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv4i64_nxv2i32(<vscale x 4 x i64> %val, i64* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv4i64_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv1r.v v25, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv4i64.nxv2i32(<vscale x 4 x i64> %val,<vscale x 4 x i64> %val, i64* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv4i64.nxv8i8(<vscale x 4 x i64>,<vscale x 4 x i64>, i64*, <vscale x 8 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv4i64.nxv8i8(<vscale x 4 x i64>,<vscale x 4 x i64>, i64*, <vscale x 8 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg2_nxv4i64_nxv8i8(<vscale x 4 x i64> %val, i64* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv4i64_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv1r.v v25, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv4i64.nxv8i8(<vscale x 4 x i64> %val,<vscale x 4 x i64> %val, i64* %base, <vscale x 8 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv4i64_nxv8i8(<vscale x 4 x i64> %val, i64* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv4i64_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv1r.v v25, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv4i64.nxv8i8(<vscale x 4 x i64> %val,<vscale x 4 x i64> %val, i64* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv4i64.nxv4i64(<vscale x 4 x i64>,<vscale x 4 x i64>, i64*, <vscale x 4 x i64>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv4i64.nxv4i64(<vscale x 4 x i64>,<vscale x 4 x i64>, i64*, <vscale x 4 x i64>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg2_nxv4i64_nxv4i64(<vscale x 4 x i64> %val, i64* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv4i64_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv4r.v v28, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v28
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv4i64.nxv4i64(<vscale x 4 x i64> %val,<vscale x 4 x i64> %val, i64* %base, <vscale x 4 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv4i64_nxv4i64(<vscale x 4 x i64> %val, i64* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv4i64_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv4r.v v28, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v28, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv4i64.nxv4i64(<vscale x 4 x i64> %val,<vscale x 4 x i64> %val, i64* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv4i64.nxv64i8(<vscale x 4 x i64>,<vscale x 4 x i64>, i64*, <vscale x 64 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv4i64.nxv64i8(<vscale x 4 x i64>,<vscale x 4 x i64>, i64*, <vscale x 64 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg2_nxv4i64_nxv64i8(<vscale x 4 x i64> %val, i64* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv4i64_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e64,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv4i64.nxv64i8(<vscale x 4 x i64> %val,<vscale x 4 x i64> %val, i64* %base, <vscale x 64 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv4i64_nxv64i8(<vscale x 4 x i64> %val, i64* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv4i64_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e64,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv4i64.nxv64i8(<vscale x 4 x i64> %val,<vscale x 4 x i64> %val, i64* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv4i64.nxv4i16(<vscale x 4 x i64>,<vscale x 4 x i64>, i64*, <vscale x 4 x i16>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv4i64.nxv4i16(<vscale x 4 x i64>,<vscale x 4 x i64>, i64*, <vscale x 4 x i16>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg2_nxv4i64_nxv4i16(<vscale x 4 x i64> %val, i64* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv4i64_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv1r.v v25, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv4i64.nxv4i16(<vscale x 4 x i64> %val,<vscale x 4 x i64> %val, i64* %base, <vscale x 4 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv4i64_nxv4i16(<vscale x 4 x i64> %val, i64* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv4i64_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv1r.v v25, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv4i64.nxv4i16(<vscale x 4 x i64> %val,<vscale x 4 x i64> %val, i64* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv4i64.nxv8i64(<vscale x 4 x i64>,<vscale x 4 x i64>, i64*, <vscale x 8 x i64>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv4i64.nxv8i64(<vscale x 4 x i64>,<vscale x 4 x i64>, i64*, <vscale x 8 x i64>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg2_nxv4i64_nxv8i64(<vscale x 4 x i64> %val, i64* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv4i64_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e64,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv4i64.nxv8i64(<vscale x 4 x i64> %val,<vscale x 4 x i64> %val, i64* %base, <vscale x 8 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv4i64_nxv8i64(<vscale x 4 x i64> %val, i64* %base, <vscale x 8 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv4i64_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e64,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv4i64.nxv8i64(<vscale x 4 x i64> %val,<vscale x 4 x i64> %val, i64* %base, <vscale x 8 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv4i64.nxv1i8(<vscale x 4 x i64>,<vscale x 4 x i64>, i64*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv4i64.nxv1i8(<vscale x 4 x i64>,<vscale x 4 x i64>, i64*, <vscale x 1 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg2_nxv4i64_nxv1i8(<vscale x 4 x i64> %val, i64* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv4i64_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv1r.v v25, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv4i64.nxv1i8(<vscale x 4 x i64> %val,<vscale x 4 x i64> %val, i64* %base, <vscale x 1 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv4i64_nxv1i8(<vscale x 4 x i64> %val, i64* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv4i64_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv1r.v v25, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv4i64.nxv1i8(<vscale x 4 x i64> %val,<vscale x 4 x i64> %val, i64* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv4i64.nxv2i8(<vscale x 4 x i64>,<vscale x 4 x i64>, i64*, <vscale x 2 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv4i64.nxv2i8(<vscale x 4 x i64>,<vscale x 4 x i64>, i64*, <vscale x 2 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg2_nxv4i64_nxv2i8(<vscale x 4 x i64> %val, i64* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv4i64_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv1r.v v25, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv4i64.nxv2i8(<vscale x 4 x i64> %val,<vscale x 4 x i64> %val, i64* %base, <vscale x 2 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv4i64_nxv2i8(<vscale x 4 x i64> %val, i64* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv4i64_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv1r.v v25, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv4i64.nxv2i8(<vscale x 4 x i64> %val,<vscale x 4 x i64> %val, i64* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv4i64.nxv8i32(<vscale x 4 x i64>,<vscale x 4 x i64>, i64*, <vscale x 8 x i32>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv4i64.nxv8i32(<vscale x 4 x i64>,<vscale x 4 x i64>, i64*, <vscale x 8 x i32>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg2_nxv4i64_nxv8i32(<vscale x 4 x i64> %val, i64* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv4i64_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv4r.v v28, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v28
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv4i64.nxv8i32(<vscale x 4 x i64> %val,<vscale x 4 x i64> %val, i64* %base, <vscale x 8 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv4i64_nxv8i32(<vscale x 4 x i64> %val, i64* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv4i64_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv4r.v v28, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v28, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv4i64.nxv8i32(<vscale x 4 x i64> %val,<vscale x 4 x i64> %val, i64* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv4i64.nxv32i8(<vscale x 4 x i64>,<vscale x 4 x i64>, i64*, <vscale x 32 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv4i64.nxv32i8(<vscale x 4 x i64>,<vscale x 4 x i64>, i64*, <vscale x 32 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg2_nxv4i64_nxv32i8(<vscale x 4 x i64> %val, i64* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv4i64_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv4r.v v28, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v28
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv4i64.nxv32i8(<vscale x 4 x i64> %val,<vscale x 4 x i64> %val, i64* %base, <vscale x 32 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv4i64_nxv32i8(<vscale x 4 x i64> %val, i64* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv4i64_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv4r.v v28, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v28, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv4i64.nxv32i8(<vscale x 4 x i64> %val,<vscale x 4 x i64> %val, i64* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv4i64.nxv16i32(<vscale x 4 x i64>,<vscale x 4 x i64>, i64*, <vscale x 16 x i32>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv4i64.nxv16i32(<vscale x 4 x i64>,<vscale x 4 x i64>, i64*, <vscale x 16 x i32>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg2_nxv4i64_nxv16i32(<vscale x 4 x i64> %val, i64* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv4i64_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e64,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv4i64.nxv16i32(<vscale x 4 x i64> %val,<vscale x 4 x i64> %val, i64* %base, <vscale x 16 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv4i64_nxv16i32(<vscale x 4 x i64> %val, i64* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv4i64_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e64,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv4i64.nxv16i32(<vscale x 4 x i64> %val,<vscale x 4 x i64> %val, i64* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv4i64.nxv2i16(<vscale x 4 x i64>,<vscale x 4 x i64>, i64*, <vscale x 2 x i16>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv4i64.nxv2i16(<vscale x 4 x i64>,<vscale x 4 x i64>, i64*, <vscale x 2 x i16>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg2_nxv4i64_nxv2i16(<vscale x 4 x i64> %val, i64* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv4i64_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv1r.v v25, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv4i64.nxv2i16(<vscale x 4 x i64> %val,<vscale x 4 x i64> %val, i64* %base, <vscale x 2 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv4i64_nxv2i16(<vscale x 4 x i64> %val, i64* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv4i64_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv1r.v v25, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv4i64.nxv2i16(<vscale x 4 x i64> %val,<vscale x 4 x i64> %val, i64* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv4i64.nxv2i64(<vscale x 4 x i64>,<vscale x 4 x i64>, i64*, <vscale x 2 x i64>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv4i64.nxv2i64(<vscale x 4 x i64>,<vscale x 4 x i64>, i64*, <vscale x 2 x i64>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg2_nxv4i64_nxv2i64(<vscale x 4 x i64> %val, i64* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv4i64_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv2r.v v26, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v26
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv4i64.nxv2i64(<vscale x 4 x i64> %val,<vscale x 4 x i64> %val, i64* %base, <vscale x 2 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv4i64_nxv2i64(<vscale x 4 x i64> %val, i64* %base, <vscale x 2 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv4i64_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv2r.v v26, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v26, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv4i64.nxv2i64(<vscale x 4 x i64> %val,<vscale x 4 x i64> %val, i64* %base, <vscale x 2 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv4i16.nxv16i16(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i16>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv4i16.nxv16i16(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i16>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg2_nxv4i16_nxv16i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv4i16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv4i16.nxv16i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv4i16_nxv16i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv4i16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv4i16.nxv16i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv4i16.nxv32i16(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 32 x i16>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv4i16.nxv32i16(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 32 x i16>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg2_nxv4i16_nxv32i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv4i16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv4i16.nxv32i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv4i16_nxv32i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv4i16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv4i16.nxv32i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv4i16.nxv4i32(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i32>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv4i16.nxv4i32(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i32>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg2_nxv4i16_nxv4i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv4i16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv4i16.nxv4i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv4i16_nxv4i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv4i16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv4i16.nxv4i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv4i16.nxv16i8(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv4i16.nxv16i8(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg2_nxv4i16_nxv16i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv4i16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv4i16.nxv16i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv4i16_nxv16i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv4i16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv4i16.nxv16i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv4i16.nxv1i64(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv4i16.nxv1i64(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i64>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg2_nxv4i16_nxv1i64(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv4i16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv4i16.nxv1i64(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv4i16_nxv1i64(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv4i16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv4i16.nxv1i64(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv4i16.nxv1i32(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv4i16.nxv1i32(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i32>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg2_nxv4i16_nxv1i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv4i16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv4i16.nxv1i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv4i16_nxv1i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv4i16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv4i16.nxv1i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv4i16.nxv8i16(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i16>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv4i16.nxv8i16(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i16>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg2_nxv4i16_nxv8i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv4i16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv4i16.nxv8i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv4i16_nxv8i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv4i16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv4i16.nxv8i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv4i16.nxv4i8(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv4i16.nxv4i8(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg2_nxv4i16_nxv4i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv4i16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv4i16.nxv4i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv4i16_nxv4i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv4i16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv4i16.nxv4i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv4i16.nxv1i16(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv4i16.nxv1i16(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i16>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg2_nxv4i16_nxv1i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv4i16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv4i16.nxv1i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv4i16_nxv1i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv4i16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv4i16.nxv1i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv4i16.nxv2i32(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i32>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv4i16.nxv2i32(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i32>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg2_nxv4i16_nxv2i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv4i16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv4i16.nxv2i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv4i16_nxv2i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv4i16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv4i16.nxv2i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv4i16.nxv8i8(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv4i16.nxv8i8(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg2_nxv4i16_nxv8i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv4i16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv4i16.nxv8i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv4i16_nxv8i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv4i16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv4i16.nxv8i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv4i16.nxv4i64(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i64>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv4i16.nxv4i64(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i64>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg2_nxv4i16_nxv4i64(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv4i16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv4i16.nxv4i64(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv4i16_nxv4i64(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv4i16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv4i16.nxv4i64(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv4i16.nxv64i8(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 64 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv4i16.nxv64i8(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 64 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg2_nxv4i16_nxv64i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv4i16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv4i16.nxv64i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv4i16_nxv64i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv4i16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv4i16.nxv64i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv4i16.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i16>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv4i16.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i16>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg2_nxv4i16_nxv4i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv4i16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv4i16.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv4i16_nxv4i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv4i16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv4i16.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv4i16.nxv8i64(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i64>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv4i16.nxv8i64(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i64>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg2_nxv4i16_nxv8i64(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv4i16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv4i16.nxv8i64(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv4i16_nxv8i64(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv4i16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv4i16.nxv8i64(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv4i16.nxv1i8(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv4i16.nxv1i8(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg2_nxv4i16_nxv1i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv4i16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv4i16.nxv1i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv4i16_nxv1i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv4i16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv4i16.nxv1i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv4i16.nxv2i8(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv4i16.nxv2i8(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg2_nxv4i16_nxv2i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv4i16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv4i16.nxv2i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv4i16_nxv2i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv4i16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv4i16.nxv2i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv4i16.nxv8i32(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i32>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv4i16.nxv8i32(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i32>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg2_nxv4i16_nxv8i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv4i16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv4i16.nxv8i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv4i16_nxv8i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv4i16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv4i16.nxv8i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv4i16.nxv32i8(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 32 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv4i16.nxv32i8(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 32 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg2_nxv4i16_nxv32i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv4i16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv4i16.nxv32i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv4i16_nxv32i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv4i16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv4i16.nxv32i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv4i16.nxv16i32(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i32>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv4i16.nxv16i32(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i32>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg2_nxv4i16_nxv16i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv4i16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv4i16.nxv16i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv4i16_nxv16i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv4i16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv4i16.nxv16i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv4i16.nxv2i16(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i16>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv4i16.nxv2i16(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i16>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg2_nxv4i16_nxv2i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv4i16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv4i16.nxv2i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv4i16_nxv2i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv4i16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv4i16.nxv2i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv4i16.nxv2i64(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i64>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv4i16.nxv2i64(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i64>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg2_nxv4i16_nxv2i64(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv4i16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv4i16.nxv2i64(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv4i16_nxv2i64(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv4i16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv4i16.nxv2i64(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv4i16.nxv16i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i16>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv4i16.nxv16i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i16>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg3_nxv4i16_nxv16i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv4i16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv4i16.nxv16i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv4i16_nxv16i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv4i16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv4i16.nxv16i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv4i16.nxv32i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 32 x i16>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv4i16.nxv32i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 32 x i16>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg3_nxv4i16_nxv32i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv4i16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv4i16.nxv32i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv4i16_nxv32i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv4i16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv4i16.nxv32i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv4i16.nxv4i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i32>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv4i16.nxv4i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i32>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg3_nxv4i16_nxv4i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv4i16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv4i16.nxv4i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv4i16_nxv4i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv4i16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv4i16.nxv4i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv4i16.nxv16i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i8>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv4i16.nxv16i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg3_nxv4i16_nxv16i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv4i16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv4i16.nxv16i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv4i16_nxv16i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv4i16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv4i16.nxv16i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv4i16.nxv1i64(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv4i16.nxv1i64(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i64>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg3_nxv4i16_nxv1i64(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv4i16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei64.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv4i16.nxv1i64(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv4i16_nxv1i64(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv4i16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei64.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv4i16.nxv1i64(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv4i16.nxv1i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv4i16.nxv1i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i32>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg3_nxv4i16_nxv1i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv4i16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv4i16.nxv1i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv4i16_nxv1i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv4i16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv4i16.nxv1i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv4i16.nxv8i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i16>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv4i16.nxv8i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i16>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg3_nxv4i16_nxv8i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv4i16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv4i16.nxv8i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv4i16_nxv8i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv4i16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv4i16.nxv8i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv4i16.nxv4i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i8>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv4i16.nxv4i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg3_nxv4i16_nxv4i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv4i16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv4i16.nxv4i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv4i16_nxv4i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv4i16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv4i16.nxv4i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv4i16.nxv1i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv4i16.nxv1i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i16>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg3_nxv4i16_nxv1i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv4i16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv4i16.nxv1i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv4i16_nxv1i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv4i16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv4i16.nxv1i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv4i16.nxv2i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i32>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv4i16.nxv2i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i32>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg3_nxv4i16_nxv2i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv4i16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv4i16.nxv2i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv4i16_nxv2i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv4i16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv4i16.nxv2i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv4i16.nxv8i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i8>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv4i16.nxv8i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg3_nxv4i16_nxv8i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv4i16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv4i16.nxv8i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv4i16_nxv8i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv4i16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv4i16.nxv8i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv4i16.nxv4i64(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i64>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv4i16.nxv4i64(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i64>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg3_nxv4i16_nxv4i64(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv4i16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei64.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv4i16.nxv4i64(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv4i16_nxv4i64(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv4i16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei64.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv4i16.nxv4i64(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv4i16.nxv64i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 64 x i8>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv4i16.nxv64i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 64 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg3_nxv4i16_nxv64i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv4i16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv4i16.nxv64i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv4i16_nxv64i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv4i16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv4i16.nxv64i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv4i16.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i16>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv4i16.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i16>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg3_nxv4i16_nxv4i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv4i16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv4i16.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv4i16_nxv4i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv4i16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv4i16.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv4i16.nxv8i64(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i64>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv4i16.nxv8i64(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i64>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg3_nxv4i16_nxv8i64(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv4i16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei64.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv4i16.nxv8i64(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv4i16_nxv8i64(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv4i16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei64.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv4i16.nxv8i64(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv4i16.nxv1i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv4i16.nxv1i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg3_nxv4i16_nxv1i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv4i16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv4i16.nxv1i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv4i16_nxv1i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv4i16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv4i16.nxv1i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv4i16.nxv2i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i8>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv4i16.nxv2i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg3_nxv4i16_nxv2i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv4i16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv4i16.nxv2i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv4i16_nxv2i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv4i16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv4i16.nxv2i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv4i16.nxv8i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i32>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv4i16.nxv8i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i32>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg3_nxv4i16_nxv8i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv4i16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv4i16.nxv8i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv4i16_nxv8i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv4i16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv4i16.nxv8i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv4i16.nxv32i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 32 x i8>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv4i16.nxv32i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 32 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg3_nxv4i16_nxv32i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv4i16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv4i16.nxv32i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv4i16_nxv32i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv4i16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv4i16.nxv32i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv4i16.nxv16i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i32>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv4i16.nxv16i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i32>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg3_nxv4i16_nxv16i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv4i16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv4i16.nxv16i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv4i16_nxv16i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv4i16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv4i16.nxv16i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv4i16.nxv2i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i16>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv4i16.nxv2i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i16>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg3_nxv4i16_nxv2i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv4i16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv4i16.nxv2i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv4i16_nxv2i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv4i16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv4i16.nxv2i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv4i16.nxv2i64(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i64>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv4i16.nxv2i64(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i64>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg3_nxv4i16_nxv2i64(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv4i16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei64.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv4i16.nxv2i64(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv4i16_nxv2i64(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv4i16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei64.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv4i16.nxv2i64(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv4i16.nxv16i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i16>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv4i16.nxv16i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i16>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg4_nxv4i16_nxv16i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv4i16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv4i16.nxv16i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv4i16_nxv16i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv4i16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv4i16.nxv16i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv4i16.nxv32i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 32 x i16>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv4i16.nxv32i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 32 x i16>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg4_nxv4i16_nxv32i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv4i16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv4i16.nxv32i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv4i16_nxv32i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv4i16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv4i16.nxv32i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv4i16.nxv4i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i32>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv4i16.nxv4i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i32>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg4_nxv4i16_nxv4i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv4i16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv4i16.nxv4i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv4i16_nxv4i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv4i16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv4i16.nxv4i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv4i16.nxv16i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i8>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv4i16.nxv16i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg4_nxv4i16_nxv16i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv4i16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv4i16.nxv16i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv4i16_nxv16i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv4i16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv4i16.nxv16i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv4i16.nxv1i64(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv4i16.nxv1i64(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i64>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg4_nxv4i16_nxv1i64(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv4i16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei64.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv4i16.nxv1i64(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv4i16_nxv1i64(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv4i16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei64.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv4i16.nxv1i64(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv4i16.nxv1i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv4i16.nxv1i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i32>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg4_nxv4i16_nxv1i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv4i16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv4i16.nxv1i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv4i16_nxv1i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv4i16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv4i16.nxv1i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv4i16.nxv8i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i16>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv4i16.nxv8i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i16>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg4_nxv4i16_nxv8i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv4i16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv4i16.nxv8i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv4i16_nxv8i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv4i16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv4i16.nxv8i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv4i16.nxv4i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i8>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv4i16.nxv4i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg4_nxv4i16_nxv4i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv4i16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv4i16.nxv4i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv4i16_nxv4i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv4i16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv4i16.nxv4i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv4i16.nxv1i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv4i16.nxv1i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i16>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg4_nxv4i16_nxv1i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv4i16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv4i16.nxv1i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv4i16_nxv1i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv4i16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv4i16.nxv1i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv4i16.nxv2i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i32>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv4i16.nxv2i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i32>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg4_nxv4i16_nxv2i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv4i16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv4i16.nxv2i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv4i16_nxv2i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv4i16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv4i16.nxv2i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv4i16.nxv8i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i8>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv4i16.nxv8i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg4_nxv4i16_nxv8i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv4i16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv4i16.nxv8i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv4i16_nxv8i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv4i16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv4i16.nxv8i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv4i16.nxv4i64(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i64>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv4i16.nxv4i64(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i64>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg4_nxv4i16_nxv4i64(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv4i16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei64.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv4i16.nxv4i64(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv4i16_nxv4i64(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv4i16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei64.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv4i16.nxv4i64(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv4i16.nxv64i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 64 x i8>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv4i16.nxv64i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 64 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg4_nxv4i16_nxv64i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv4i16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv4i16.nxv64i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv4i16_nxv64i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv4i16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv4i16.nxv64i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv4i16.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i16>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv4i16.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i16>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg4_nxv4i16_nxv4i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv4i16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv4i16.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv4i16_nxv4i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv4i16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv4i16.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv4i16.nxv8i64(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i64>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv4i16.nxv8i64(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i64>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg4_nxv4i16_nxv8i64(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv4i16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei64.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv4i16.nxv8i64(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv4i16_nxv8i64(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv4i16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei64.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv4i16.nxv8i64(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv4i16.nxv1i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv4i16.nxv1i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg4_nxv4i16_nxv1i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv4i16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv4i16.nxv1i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv4i16_nxv1i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv4i16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv4i16.nxv1i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv4i16.nxv2i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i8>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv4i16.nxv2i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg4_nxv4i16_nxv2i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv4i16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv4i16.nxv2i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv4i16_nxv2i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv4i16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv4i16.nxv2i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv4i16.nxv8i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i32>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv4i16.nxv8i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i32>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg4_nxv4i16_nxv8i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv4i16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv4i16.nxv8i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv4i16_nxv8i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv4i16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv4i16.nxv8i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv4i16.nxv32i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 32 x i8>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv4i16.nxv32i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 32 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg4_nxv4i16_nxv32i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv4i16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv4i16.nxv32i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv4i16_nxv32i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv4i16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv4i16.nxv32i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv4i16.nxv16i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i32>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv4i16.nxv16i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i32>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg4_nxv4i16_nxv16i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv4i16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv4i16.nxv16i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv4i16_nxv16i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv4i16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv4i16.nxv16i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv4i16.nxv2i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i16>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv4i16.nxv2i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i16>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg4_nxv4i16_nxv2i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv4i16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv4i16.nxv2i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv4i16_nxv2i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv4i16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv4i16.nxv2i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv4i16.nxv2i64(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i64>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv4i16.nxv2i64(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i64>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg4_nxv4i16_nxv2i64(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv4i16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei64.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv4i16.nxv2i64(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv4i16_nxv2i64(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv4i16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei64.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv4i16.nxv2i64(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv4i16.nxv16i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i16>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv4i16.nxv16i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i16>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg5_nxv4i16_nxv16i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv4i16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv4i16.nxv16i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv4i16_nxv16i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv4i16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv4i16.nxv16i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv4i16.nxv32i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 32 x i16>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv4i16.nxv32i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 32 x i16>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg5_nxv4i16_nxv32i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv4i16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv4i16.nxv32i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv4i16_nxv32i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv4i16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv4i16.nxv32i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv4i16.nxv4i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i32>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv4i16.nxv4i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i32>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg5_nxv4i16_nxv4i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv4i16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei32.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv4i16.nxv4i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv4i16_nxv4i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv4i16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei32.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv4i16.nxv4i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv4i16.nxv16i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i8>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv4i16.nxv16i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg5_nxv4i16_nxv16i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv4i16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv4i16.nxv16i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv4i16_nxv16i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv4i16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv4i16.nxv16i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv4i16.nxv1i64(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv4i16.nxv1i64(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i64>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg5_nxv4i16_nxv1i64(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv4i16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei64.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv4i16.nxv1i64(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv4i16_nxv1i64(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv4i16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei64.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv4i16.nxv1i64(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv4i16.nxv1i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv4i16.nxv1i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i32>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg5_nxv4i16_nxv1i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv4i16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv4i16.nxv1i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv4i16_nxv1i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv4i16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv4i16.nxv1i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv4i16.nxv8i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i16>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv4i16.nxv8i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i16>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg5_nxv4i16_nxv8i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv4i16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv4i16.nxv8i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv4i16_nxv8i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv4i16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv4i16.nxv8i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv4i16.nxv4i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i8>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv4i16.nxv4i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg5_nxv4i16_nxv4i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv4i16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv4i16.nxv4i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv4i16_nxv4i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv4i16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv4i16.nxv4i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv4i16.nxv1i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv4i16.nxv1i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i16>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg5_nxv4i16_nxv1i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv4i16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv4i16.nxv1i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv4i16_nxv1i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv4i16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv4i16.nxv1i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv4i16.nxv2i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i32>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv4i16.nxv2i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i32>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg5_nxv4i16_nxv2i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv4i16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv4i16.nxv2i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv4i16_nxv2i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv4i16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv4i16.nxv2i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv4i16.nxv8i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i8>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv4i16.nxv8i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg5_nxv4i16_nxv8i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv4i16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv4i16.nxv8i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv4i16_nxv8i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv4i16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv4i16.nxv8i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv4i16.nxv4i64(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i64>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv4i16.nxv4i64(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i64>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg5_nxv4i16_nxv4i64(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv4i16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei64.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv4i16.nxv4i64(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv4i16_nxv4i64(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv4i16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei64.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv4i16.nxv4i64(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv4i16.nxv64i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 64 x i8>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv4i16.nxv64i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 64 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg5_nxv4i16_nxv64i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv4i16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv4i16.nxv64i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv4i16_nxv64i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv4i16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv4i16.nxv64i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv4i16.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i16>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv4i16.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i16>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg5_nxv4i16_nxv4i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv4i16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv4i16.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv4i16_nxv4i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv4i16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv4i16.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv4i16.nxv8i64(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i64>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv4i16.nxv8i64(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i64>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg5_nxv4i16_nxv8i64(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv4i16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei64.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv4i16.nxv8i64(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv4i16_nxv8i64(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv4i16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei64.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv4i16.nxv8i64(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv4i16.nxv1i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv4i16.nxv1i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg5_nxv4i16_nxv1i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv4i16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv4i16.nxv1i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv4i16_nxv1i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv4i16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv4i16.nxv1i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv4i16.nxv2i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i8>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv4i16.nxv2i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg5_nxv4i16_nxv2i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv4i16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv4i16.nxv2i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv4i16_nxv2i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv4i16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv4i16.nxv2i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv4i16.nxv8i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i32>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv4i16.nxv8i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i32>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg5_nxv4i16_nxv8i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv4i16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei32.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv4i16.nxv8i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv4i16_nxv8i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv4i16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei32.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv4i16.nxv8i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv4i16.nxv32i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 32 x i8>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv4i16.nxv32i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 32 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg5_nxv4i16_nxv32i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv4i16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv4i16.nxv32i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv4i16_nxv32i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv4i16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv4i16.nxv32i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv4i16.nxv16i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i32>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv4i16.nxv16i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i32>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg5_nxv4i16_nxv16i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv4i16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei32.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv4i16.nxv16i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv4i16_nxv16i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv4i16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei32.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv4i16.nxv16i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv4i16.nxv2i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i16>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv4i16.nxv2i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i16>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg5_nxv4i16_nxv2i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv4i16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv4i16.nxv2i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv4i16_nxv2i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv4i16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv4i16.nxv2i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv4i16.nxv2i64(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i64>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv4i16.nxv2i64(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i64>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg5_nxv4i16_nxv2i64(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv4i16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei64.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv4i16.nxv2i64(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv4i16_nxv2i64(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv4i16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei64.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv4i16.nxv2i64(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv4i16.nxv16i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i16>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv4i16.nxv16i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i16>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg6_nxv4i16_nxv16i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv4i16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv4i16.nxv16i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv4i16_nxv16i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv4i16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv4i16.nxv16i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv4i16.nxv32i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 32 x i16>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv4i16.nxv32i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 32 x i16>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg6_nxv4i16_nxv32i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv4i16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv4i16.nxv32i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv4i16_nxv32i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv4i16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv4i16.nxv32i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv4i16.nxv4i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i32>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv4i16.nxv4i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i32>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg6_nxv4i16_nxv4i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv4i16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei32.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv4i16.nxv4i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv4i16_nxv4i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv4i16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei32.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv4i16.nxv4i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv4i16.nxv16i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i8>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv4i16.nxv16i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg6_nxv4i16_nxv16i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv4i16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv4i16.nxv16i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv4i16_nxv16i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv4i16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv4i16.nxv16i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv4i16.nxv1i64(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv4i16.nxv1i64(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i64>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg6_nxv4i16_nxv1i64(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv4i16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei64.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv4i16.nxv1i64(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv4i16_nxv1i64(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv4i16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei64.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv4i16.nxv1i64(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv4i16.nxv1i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv4i16.nxv1i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i32>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg6_nxv4i16_nxv1i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv4i16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv4i16.nxv1i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv4i16_nxv1i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv4i16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv4i16.nxv1i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv4i16.nxv8i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i16>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv4i16.nxv8i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i16>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg6_nxv4i16_nxv8i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv4i16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv4i16.nxv8i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv4i16_nxv8i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv4i16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv4i16.nxv8i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv4i16.nxv4i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i8>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv4i16.nxv4i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg6_nxv4i16_nxv4i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv4i16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv4i16.nxv4i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv4i16_nxv4i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv4i16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv4i16.nxv4i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv4i16.nxv1i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv4i16.nxv1i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i16>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg6_nxv4i16_nxv1i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv4i16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv4i16.nxv1i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv4i16_nxv1i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv4i16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv4i16.nxv1i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv4i16.nxv2i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i32>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv4i16.nxv2i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i32>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg6_nxv4i16_nxv2i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv4i16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv4i16.nxv2i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv4i16_nxv2i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv4i16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv4i16.nxv2i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv4i16.nxv8i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i8>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv4i16.nxv8i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg6_nxv4i16_nxv8i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv4i16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv4i16.nxv8i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv4i16_nxv8i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv4i16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv4i16.nxv8i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv4i16.nxv4i64(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i64>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv4i16.nxv4i64(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i64>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg6_nxv4i16_nxv4i64(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv4i16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei64.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv4i16.nxv4i64(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv4i16_nxv4i64(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv4i16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei64.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv4i16.nxv4i64(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv4i16.nxv64i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 64 x i8>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv4i16.nxv64i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 64 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg6_nxv4i16_nxv64i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv4i16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv4i16.nxv64i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv4i16_nxv64i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv4i16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv4i16.nxv64i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv4i16.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i16>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv4i16.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i16>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg6_nxv4i16_nxv4i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv4i16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv4i16.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv4i16_nxv4i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv4i16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv4i16.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv4i16.nxv8i64(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i64>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv4i16.nxv8i64(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i64>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg6_nxv4i16_nxv8i64(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv4i16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei64.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv4i16.nxv8i64(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv4i16_nxv8i64(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv4i16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei64.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv4i16.nxv8i64(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv4i16.nxv1i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv4i16.nxv1i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg6_nxv4i16_nxv1i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv4i16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv4i16.nxv1i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv4i16_nxv1i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv4i16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv4i16.nxv1i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv4i16.nxv2i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i8>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv4i16.nxv2i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg6_nxv4i16_nxv2i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv4i16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv4i16.nxv2i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv4i16_nxv2i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv4i16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv4i16.nxv2i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv4i16.nxv8i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i32>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv4i16.nxv8i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i32>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg6_nxv4i16_nxv8i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv4i16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei32.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv4i16.nxv8i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv4i16_nxv8i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv4i16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei32.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv4i16.nxv8i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv4i16.nxv32i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 32 x i8>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv4i16.nxv32i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 32 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg6_nxv4i16_nxv32i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv4i16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv4i16.nxv32i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv4i16_nxv32i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv4i16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv4i16.nxv32i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv4i16.nxv16i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i32>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv4i16.nxv16i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i32>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg6_nxv4i16_nxv16i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv4i16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei32.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv4i16.nxv16i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv4i16_nxv16i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv4i16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei32.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv4i16.nxv16i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv4i16.nxv2i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i16>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv4i16.nxv2i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i16>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg6_nxv4i16_nxv2i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv4i16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv4i16.nxv2i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv4i16_nxv2i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv4i16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv4i16.nxv2i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv4i16.nxv2i64(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i64>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv4i16.nxv2i64(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i64>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg6_nxv4i16_nxv2i64(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv4i16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei64.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv4i16.nxv2i64(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv4i16_nxv2i64(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv4i16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei64.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv4i16.nxv2i64(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv4i16.nxv16i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i16>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv4i16.nxv16i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i16>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg7_nxv4i16_nxv16i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv4i16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv4i16.nxv16i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv4i16_nxv16i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv4i16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv4i16.nxv16i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv4i16.nxv32i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 32 x i16>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv4i16.nxv32i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 32 x i16>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg7_nxv4i16_nxv32i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv4i16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv4i16.nxv32i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv4i16_nxv32i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv4i16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv4i16.nxv32i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv4i16.nxv4i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i32>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv4i16.nxv4i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i32>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg7_nxv4i16_nxv4i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv4i16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei32.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv4i16.nxv4i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv4i16_nxv4i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv4i16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei32.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv4i16.nxv4i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv4i16.nxv16i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i8>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv4i16.nxv16i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg7_nxv4i16_nxv16i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv4i16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv4i16.nxv16i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv4i16_nxv16i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv4i16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv4i16.nxv16i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv4i16.nxv1i64(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv4i16.nxv1i64(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i64>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg7_nxv4i16_nxv1i64(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv4i16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei64.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv4i16.nxv1i64(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv4i16_nxv1i64(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv4i16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei64.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv4i16.nxv1i64(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv4i16.nxv1i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv4i16.nxv1i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i32>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg7_nxv4i16_nxv1i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv4i16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv4i16.nxv1i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv4i16_nxv1i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv4i16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv4i16.nxv1i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv4i16.nxv8i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i16>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv4i16.nxv8i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i16>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg7_nxv4i16_nxv8i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv4i16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv4i16.nxv8i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv4i16_nxv8i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv4i16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv4i16.nxv8i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv4i16.nxv4i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i8>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv4i16.nxv4i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg7_nxv4i16_nxv4i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv4i16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv4i16.nxv4i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv4i16_nxv4i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv4i16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv4i16.nxv4i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv4i16.nxv1i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv4i16.nxv1i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i16>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg7_nxv4i16_nxv1i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv4i16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv4i16.nxv1i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv4i16_nxv1i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv4i16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv4i16.nxv1i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv4i16.nxv2i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i32>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv4i16.nxv2i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i32>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg7_nxv4i16_nxv2i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv4i16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv4i16.nxv2i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv4i16_nxv2i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv4i16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv4i16.nxv2i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv4i16.nxv8i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i8>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv4i16.nxv8i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg7_nxv4i16_nxv8i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv4i16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv4i16.nxv8i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv4i16_nxv8i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv4i16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv4i16.nxv8i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv4i16.nxv4i64(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i64>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv4i16.nxv4i64(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i64>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg7_nxv4i16_nxv4i64(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv4i16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei64.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv4i16.nxv4i64(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv4i16_nxv4i64(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv4i16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei64.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv4i16.nxv4i64(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv4i16.nxv64i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 64 x i8>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv4i16.nxv64i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 64 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg7_nxv4i16_nxv64i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv4i16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv4i16.nxv64i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv4i16_nxv64i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv4i16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv4i16.nxv64i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv4i16.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i16>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv4i16.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i16>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg7_nxv4i16_nxv4i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv4i16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv4i16.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv4i16_nxv4i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv4i16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv4i16.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv4i16.nxv8i64(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i64>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv4i16.nxv8i64(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i64>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg7_nxv4i16_nxv8i64(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv4i16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei64.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv4i16.nxv8i64(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv4i16_nxv8i64(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv4i16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei64.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv4i16.nxv8i64(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv4i16.nxv1i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv4i16.nxv1i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg7_nxv4i16_nxv1i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv4i16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv4i16.nxv1i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv4i16_nxv1i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv4i16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv4i16.nxv1i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv4i16.nxv2i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i8>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv4i16.nxv2i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg7_nxv4i16_nxv2i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv4i16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv4i16.nxv2i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv4i16_nxv2i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv4i16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv4i16.nxv2i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv4i16.nxv8i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i32>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv4i16.nxv8i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i32>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg7_nxv4i16_nxv8i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv4i16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei32.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv4i16.nxv8i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv4i16_nxv8i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv4i16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei32.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv4i16.nxv8i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv4i16.nxv32i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 32 x i8>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv4i16.nxv32i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 32 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg7_nxv4i16_nxv32i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv4i16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv4i16.nxv32i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv4i16_nxv32i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv4i16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv4i16.nxv32i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv4i16.nxv16i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i32>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv4i16.nxv16i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i32>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg7_nxv4i16_nxv16i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv4i16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei32.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv4i16.nxv16i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv4i16_nxv16i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv4i16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei32.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv4i16.nxv16i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv4i16.nxv2i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i16>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv4i16.nxv2i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i16>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg7_nxv4i16_nxv2i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv4i16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv4i16.nxv2i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv4i16_nxv2i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv4i16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv4i16.nxv2i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv4i16.nxv2i64(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i64>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv4i16.nxv2i64(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i64>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg7_nxv4i16_nxv2i64(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv4i16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei64.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv4i16.nxv2i64(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv4i16_nxv2i64(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv4i16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei64.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv4i16.nxv2i64(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv4i16.nxv16i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i16>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv4i16.nxv16i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i16>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg8_nxv4i16_nxv16i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv4i16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv4i16.nxv16i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv4i16_nxv16i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv4i16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv4i16.nxv16i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv4i16.nxv32i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 32 x i16>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv4i16.nxv32i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 32 x i16>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg8_nxv4i16_nxv32i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv4i16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vmv1r.v v23, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv4i16.nxv32i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv4i16_nxv32i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv4i16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vmv1r.v v23, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv4i16.nxv32i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv4i16.nxv4i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i32>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv4i16.nxv4i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i32>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg8_nxv4i16_nxv4i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv4i16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei32.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv4i16.nxv4i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv4i16_nxv4i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv4i16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei32.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv4i16.nxv4i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv4i16.nxv16i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i8>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv4i16.nxv16i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg8_nxv4i16_nxv16i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv4i16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv4i16.nxv16i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv4i16_nxv16i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv4i16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv4i16.nxv16i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv4i16.nxv1i64(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv4i16.nxv1i64(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i64>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg8_nxv4i16_nxv1i64(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv4i16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei64.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv4i16.nxv1i64(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv4i16_nxv1i64(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv4i16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei64.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv4i16.nxv1i64(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv4i16.nxv1i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv4i16.nxv1i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i32>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg8_nxv4i16_nxv1i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv4i16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv4i16.nxv1i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv4i16_nxv1i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv4i16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv4i16.nxv1i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv4i16.nxv8i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i16>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv4i16.nxv8i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i16>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg8_nxv4i16_nxv8i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv4i16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv4i16.nxv8i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv4i16_nxv8i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv4i16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv4i16.nxv8i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv4i16.nxv4i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i8>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv4i16.nxv4i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg8_nxv4i16_nxv4i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv4i16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv4i16.nxv4i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv4i16_nxv4i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv4i16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv4i16.nxv4i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv4i16.nxv1i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv4i16.nxv1i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i16>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg8_nxv4i16_nxv1i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv4i16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv4i16.nxv1i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv4i16_nxv1i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv4i16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv4i16.nxv1i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv4i16.nxv2i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i32>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv4i16.nxv2i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i32>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg8_nxv4i16_nxv2i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv4i16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv4i16.nxv2i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv4i16_nxv2i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv4i16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv4i16.nxv2i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv4i16.nxv8i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i8>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv4i16.nxv8i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg8_nxv4i16_nxv8i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv4i16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv4i16.nxv8i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv4i16_nxv8i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv4i16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv4i16.nxv8i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv4i16.nxv4i64(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i64>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv4i16.nxv4i64(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i64>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg8_nxv4i16_nxv4i64(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv4i16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei64.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv4i16.nxv4i64(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv4i16_nxv4i64(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv4i16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei64.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv4i16.nxv4i64(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv4i16.nxv64i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 64 x i8>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv4i16.nxv64i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 64 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg8_nxv4i16_nxv64i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv4i16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vmv1r.v v23, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv4i16.nxv64i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv4i16_nxv64i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv4i16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vmv1r.v v23, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv4i16.nxv64i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv4i16.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i16>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv4i16.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i16>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg8_nxv4i16_nxv4i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv4i16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv4i16.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv4i16_nxv4i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv4i16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv4i16.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv4i16.nxv8i64(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i64>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv4i16.nxv8i64(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i64>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg8_nxv4i16_nxv8i64(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv4i16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vmv1r.v v23, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei64.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv4i16.nxv8i64(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv4i16_nxv8i64(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv4i16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vmv1r.v v23, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei64.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv4i16.nxv8i64(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv4i16.nxv1i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv4i16.nxv1i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 1 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg8_nxv4i16_nxv1i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv4i16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv4i16.nxv1i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv4i16_nxv1i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv4i16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv4i16.nxv1i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv4i16.nxv2i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i8>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv4i16.nxv2i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg8_nxv4i16_nxv2i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv4i16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv4i16.nxv2i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv4i16_nxv2i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv4i16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv4i16.nxv2i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv4i16.nxv8i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i32>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv4i16.nxv8i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 8 x i32>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg8_nxv4i16_nxv8i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv4i16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei32.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv4i16.nxv8i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv4i16_nxv8i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv4i16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei32.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv4i16.nxv8i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv4i16.nxv32i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 32 x i8>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv4i16.nxv32i8(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 32 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg8_nxv4i16_nxv32i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv4i16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv4i16.nxv32i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv4i16_nxv32i8(<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv4i16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv4i16.nxv32i8(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv4i16.nxv16i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i32>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv4i16.nxv16i32(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 16 x i32>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg8_nxv4i16_nxv16i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv4i16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vmv1r.v v23, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei32.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv4i16.nxv16i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv4i16_nxv16i32(<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv4i16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vmv1r.v v23, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei32.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv4i16.nxv16i32(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv4i16.nxv2i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i16>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv4i16.nxv2i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i16>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg8_nxv4i16_nxv2i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv4i16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv4i16.nxv2i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv4i16_nxv2i16(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv4i16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv4i16.nxv2i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv4i16.nxv2i64(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i64>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv4i16.nxv2i64(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 2 x i64>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg8_nxv4i16_nxv2i64(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv4i16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei64.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv4i16.nxv2i64(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv4i16_nxv2i64(<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv4i16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei64.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv4i16.nxv2i64(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 2 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv1i8.nxv16i16(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i16>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv1i8.nxv16i16(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg2_nxv1i8_nxv16i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv1i8_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv1i8.nxv16i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv1i8_nxv16i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv1i8_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv1i8.nxv16i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv1i8.nxv32i16(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 32 x i16>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv1i8.nxv32i16(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 32 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg2_nxv1i8_nxv32i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv1i8_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv1i8.nxv32i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv1i8_nxv32i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv1i8_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv1i8.nxv32i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv1i8.nxv4i32(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i32>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv1i8.nxv4i32(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg2_nxv1i8_nxv4i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv1i8_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv1i8.nxv4i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv1i8_nxv4i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv1i8_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv1i8.nxv4i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv1i8.nxv16i8(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv1i8.nxv16i8(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg2_nxv1i8_nxv16i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv1i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv1i8.nxv16i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv1i8_nxv16i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv1i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv1i8.nxv16i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv1i8.nxv1i64(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv1i8.nxv1i64(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg2_nxv1i8_nxv1i64(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv1i8_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv1i8.nxv1i64(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv1i8_nxv1i64(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv1i8_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv1i8.nxv1i64(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv1i8.nxv1i32(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv1i8.nxv1i32(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg2_nxv1i8_nxv1i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv1i8_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv1i8.nxv1i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv1i8_nxv1i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv1i8_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv1i8.nxv1i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv1i8.nxv8i16(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i16>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv1i8.nxv8i16(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg2_nxv1i8_nxv8i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv1i8_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv1i8.nxv8i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv1i8_nxv8i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv1i8_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv1i8.nxv8i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv1i8.nxv4i8(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv1i8.nxv4i8(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg2_nxv1i8_nxv4i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv1i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv1i8.nxv4i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv1i8_nxv4i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv1i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv1i8.nxv4i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv1i8.nxv1i16(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv1i8.nxv1i16(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg2_nxv1i8_nxv1i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv1i8_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv1i8.nxv1i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv1i8_nxv1i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv1i8_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv1i8.nxv1i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv1i8.nxv2i32(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i32>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv1i8.nxv2i32(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg2_nxv1i8_nxv2i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv1i8_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv1i8.nxv2i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv1i8_nxv2i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv1i8_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv1i8.nxv2i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv1i8.nxv8i8(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv1i8.nxv8i8(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg2_nxv1i8_nxv8i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv1i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv1i8.nxv8i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv1i8_nxv8i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv1i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv1i8.nxv8i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv1i8.nxv4i64(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i64>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv1i8.nxv4i64(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg2_nxv1i8_nxv4i64(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv1i8_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv1i8.nxv4i64(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv1i8_nxv4i64(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv1i8_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv1i8.nxv4i64(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv1i8.nxv64i8(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 64 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv1i8.nxv64i8(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 64 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg2_nxv1i8_nxv64i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv1i8_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv1i8.nxv64i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv1i8_nxv64i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv1i8_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv1i8.nxv64i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv1i8.nxv4i16(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i16>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv1i8.nxv4i16(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg2_nxv1i8_nxv4i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv1i8_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv1i8.nxv4i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv1i8_nxv4i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv1i8_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv1i8.nxv4i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv1i8.nxv8i64(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i64>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv1i8.nxv8i64(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg2_nxv1i8_nxv8i64(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv1i8_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv1i8.nxv8i64(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv1i8_nxv8i64(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv1i8_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv1i8.nxv8i64(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv1i8.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv1i8.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg2_nxv1i8_nxv1i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv1i8_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv1i8.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv1i8_nxv1i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv1i8_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv1i8.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv1i8.nxv2i8(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv1i8.nxv2i8(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg2_nxv1i8_nxv2i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv1i8_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv1i8.nxv2i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv1i8_nxv2i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv1i8_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv1i8.nxv2i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv1i8.nxv8i32(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i32>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv1i8.nxv8i32(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg2_nxv1i8_nxv8i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv1i8_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv1i8.nxv8i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv1i8_nxv8i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv1i8_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv1i8.nxv8i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv1i8.nxv32i8(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 32 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv1i8.nxv32i8(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 32 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg2_nxv1i8_nxv32i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv1i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv1i8.nxv32i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv1i8_nxv32i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv1i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv1i8.nxv32i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv1i8.nxv16i32(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i32>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv1i8.nxv16i32(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg2_nxv1i8_nxv16i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv1i8_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv1i8.nxv16i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv1i8_nxv16i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv1i8_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv1i8.nxv16i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv1i8.nxv2i16(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i16>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv1i8.nxv2i16(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg2_nxv1i8_nxv2i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv1i8_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv1i8.nxv2i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv1i8_nxv2i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv1i8_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv1i8.nxv2i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv1i8.nxv2i64(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i64>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv1i8.nxv2i64(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg2_nxv1i8_nxv2i64(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv1i8_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv1i8.nxv2i64(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv1i8_nxv2i64(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv1i8_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv1i8.nxv2i64(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv1i8.nxv16i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i16>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv1i8.nxv16i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg3_nxv1i8_nxv16i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv1i8_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv1i8.nxv16i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv1i8_nxv16i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv1i8_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv1i8.nxv16i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv1i8.nxv32i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 32 x i16>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv1i8.nxv32i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 32 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg3_nxv1i8_nxv32i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv1i8_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv1i8.nxv32i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv1i8_nxv32i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv1i8_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv1i8.nxv32i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv1i8.nxv4i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i32>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv1i8.nxv4i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg3_nxv1i8_nxv4i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv1i8_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv1i8.nxv4i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv1i8_nxv4i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv1i8_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv1i8.nxv4i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv1i8.nxv16i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i8>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv1i8.nxv16i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg3_nxv1i8_nxv16i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv1i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv1i8.nxv16i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv1i8_nxv16i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv1i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv1i8.nxv16i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv1i8.nxv1i64(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv1i8.nxv1i64(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg3_nxv1i8_nxv1i64(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv1i8_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg3ei64.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv1i8.nxv1i64(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv1i8_nxv1i64(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv1i8_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg3ei64.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv1i8.nxv1i64(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv1i8.nxv1i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv1i8.nxv1i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg3_nxv1i8_nxv1i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv1i8_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv1i8.nxv1i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv1i8_nxv1i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv1i8_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv1i8.nxv1i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv1i8.nxv8i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i16>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv1i8.nxv8i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg3_nxv1i8_nxv8i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv1i8_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv1i8.nxv8i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv1i8_nxv8i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv1i8_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv1i8.nxv8i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv1i8.nxv4i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i8>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv1i8.nxv4i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg3_nxv1i8_nxv4i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv1i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv1i8.nxv4i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv1i8_nxv4i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv1i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv1i8.nxv4i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv1i8.nxv1i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv1i8.nxv1i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg3_nxv1i8_nxv1i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv1i8_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv1i8.nxv1i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv1i8_nxv1i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv1i8_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv1i8.nxv1i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv1i8.nxv2i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i32>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv1i8.nxv2i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg3_nxv1i8_nxv2i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv1i8_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv1i8.nxv2i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv1i8_nxv2i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv1i8_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv1i8.nxv2i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv1i8.nxv8i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i8>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv1i8.nxv8i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg3_nxv1i8_nxv8i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv1i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv1i8.nxv8i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv1i8_nxv8i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv1i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv1i8.nxv8i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv1i8.nxv4i64(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i64>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv1i8.nxv4i64(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg3_nxv1i8_nxv4i64(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv1i8_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg3ei64.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv1i8.nxv4i64(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv1i8_nxv4i64(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv1i8_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg3ei64.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv1i8.nxv4i64(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv1i8.nxv64i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 64 x i8>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv1i8.nxv64i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 64 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg3_nxv1i8_nxv64i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv1i8_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv1i8.nxv64i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv1i8_nxv64i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv1i8_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv1i8.nxv64i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv1i8.nxv4i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i16>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv1i8.nxv4i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg3_nxv1i8_nxv4i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv1i8_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv1i8.nxv4i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv1i8_nxv4i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv1i8_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv1i8.nxv4i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv1i8.nxv8i64(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i64>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv1i8.nxv8i64(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg3_nxv1i8_nxv8i64(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv1i8_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg3ei64.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv1i8.nxv8i64(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv1i8_nxv8i64(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv1i8_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg3ei64.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv1i8.nxv8i64(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv1i8.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv1i8.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg3_nxv1i8_nxv1i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv1i8_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv1i8.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv1i8_nxv1i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv1i8_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv1i8.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv1i8.nxv2i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i8>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv1i8.nxv2i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg3_nxv1i8_nxv2i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv1i8_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv1i8.nxv2i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv1i8_nxv2i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv1i8_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv1i8.nxv2i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv1i8.nxv8i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i32>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv1i8.nxv8i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg3_nxv1i8_nxv8i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv1i8_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv1i8.nxv8i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv1i8_nxv8i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv1i8_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv1i8.nxv8i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv1i8.nxv32i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 32 x i8>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv1i8.nxv32i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 32 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg3_nxv1i8_nxv32i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv1i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv1i8.nxv32i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv1i8_nxv32i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv1i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv1i8.nxv32i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv1i8.nxv16i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i32>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv1i8.nxv16i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg3_nxv1i8_nxv16i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv1i8_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv1i8.nxv16i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv1i8_nxv16i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv1i8_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv1i8.nxv16i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv1i8.nxv2i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i16>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv1i8.nxv2i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg3_nxv1i8_nxv2i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv1i8_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv1i8.nxv2i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv1i8_nxv2i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv1i8_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv1i8.nxv2i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv1i8.nxv2i64(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i64>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv1i8.nxv2i64(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg3_nxv1i8_nxv2i64(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv1i8_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg3ei64.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv1i8.nxv2i64(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv1i8_nxv2i64(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv1i8_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg3ei64.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv1i8.nxv2i64(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv1i8.nxv16i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i16>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv1i8.nxv16i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg4_nxv1i8_nxv16i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv1i8_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv1i8.nxv16i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv1i8_nxv16i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv1i8_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv1i8.nxv16i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv1i8.nxv32i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 32 x i16>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv1i8.nxv32i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 32 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg4_nxv1i8_nxv32i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv1i8_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv1i8.nxv32i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv1i8_nxv32i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv1i8_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv1i8.nxv32i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv1i8.nxv4i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i32>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv1i8.nxv4i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg4_nxv1i8_nxv4i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv1i8_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv1i8.nxv4i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv1i8_nxv4i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv1i8_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv1i8.nxv4i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv1i8.nxv16i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i8>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv1i8.nxv16i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg4_nxv1i8_nxv16i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv1i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv1i8.nxv16i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv1i8_nxv16i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv1i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv1i8.nxv16i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv1i8.nxv1i64(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv1i8.nxv1i64(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg4_nxv1i8_nxv1i64(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv1i8_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg4ei64.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv1i8.nxv1i64(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv1i8_nxv1i64(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv1i8_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg4ei64.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv1i8.nxv1i64(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv1i8.nxv1i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv1i8.nxv1i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg4_nxv1i8_nxv1i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv1i8_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv1i8.nxv1i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv1i8_nxv1i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv1i8_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv1i8.nxv1i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv1i8.nxv8i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i16>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv1i8.nxv8i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg4_nxv1i8_nxv8i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv1i8_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv1i8.nxv8i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv1i8_nxv8i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv1i8_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv1i8.nxv8i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv1i8.nxv4i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i8>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv1i8.nxv4i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg4_nxv1i8_nxv4i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv1i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv1i8.nxv4i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv1i8_nxv4i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv1i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv1i8.nxv4i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv1i8.nxv1i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv1i8.nxv1i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg4_nxv1i8_nxv1i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv1i8_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv1i8.nxv1i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv1i8_nxv1i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv1i8_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv1i8.nxv1i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv1i8.nxv2i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i32>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv1i8.nxv2i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg4_nxv1i8_nxv2i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv1i8_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv1i8.nxv2i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv1i8_nxv2i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv1i8_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv1i8.nxv2i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv1i8.nxv8i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i8>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv1i8.nxv8i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg4_nxv1i8_nxv8i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv1i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv1i8.nxv8i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv1i8_nxv8i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv1i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv1i8.nxv8i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv1i8.nxv4i64(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i64>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv1i8.nxv4i64(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg4_nxv1i8_nxv4i64(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv1i8_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg4ei64.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv1i8.nxv4i64(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv1i8_nxv4i64(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv1i8_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg4ei64.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv1i8.nxv4i64(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv1i8.nxv64i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 64 x i8>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv1i8.nxv64i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 64 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg4_nxv1i8_nxv64i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv1i8_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv1i8.nxv64i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv1i8_nxv64i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv1i8_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv1i8.nxv64i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv1i8.nxv4i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i16>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv1i8.nxv4i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg4_nxv1i8_nxv4i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv1i8_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv1i8.nxv4i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv1i8_nxv4i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv1i8_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv1i8.nxv4i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv1i8.nxv8i64(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i64>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv1i8.nxv8i64(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg4_nxv1i8_nxv8i64(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv1i8_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg4ei64.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv1i8.nxv8i64(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv1i8_nxv8i64(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv1i8_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg4ei64.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv1i8.nxv8i64(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv1i8.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv1i8.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg4_nxv1i8_nxv1i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv1i8_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv1i8.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv1i8_nxv1i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv1i8_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv1i8.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv1i8.nxv2i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i8>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv1i8.nxv2i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg4_nxv1i8_nxv2i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv1i8_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv1i8.nxv2i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv1i8_nxv2i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv1i8_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv1i8.nxv2i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv1i8.nxv8i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i32>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv1i8.nxv8i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg4_nxv1i8_nxv8i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv1i8_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv1i8.nxv8i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv1i8_nxv8i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv1i8_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv1i8.nxv8i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv1i8.nxv32i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 32 x i8>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv1i8.nxv32i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 32 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg4_nxv1i8_nxv32i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv1i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv1i8.nxv32i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv1i8_nxv32i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv1i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv1i8.nxv32i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv1i8.nxv16i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i32>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv1i8.nxv16i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg4_nxv1i8_nxv16i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv1i8_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv1i8.nxv16i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv1i8_nxv16i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv1i8_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv1i8.nxv16i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv1i8.nxv2i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i16>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv1i8.nxv2i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg4_nxv1i8_nxv2i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv1i8_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv1i8.nxv2i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv1i8_nxv2i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv1i8_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv1i8.nxv2i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv1i8.nxv2i64(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i64>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv1i8.nxv2i64(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg4_nxv1i8_nxv2i64(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv1i8_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg4ei64.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv1i8.nxv2i64(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv1i8_nxv2i64(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv1i8_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg4ei64.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv1i8.nxv2i64(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv1i8.nxv16i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i16>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv1i8.nxv16i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg5_nxv1i8_nxv16i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv1i8_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv1i8.nxv16i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv1i8_nxv16i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv1i8_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv1i8.nxv16i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv1i8.nxv32i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 32 x i16>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv1i8.nxv32i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 32 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg5_nxv1i8_nxv32i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv1i8_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv1i8.nxv32i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv1i8_nxv32i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv1i8_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv1i8.nxv32i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv1i8.nxv4i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i32>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv1i8.nxv4i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg5_nxv1i8_nxv4i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv1i8_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg5ei32.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv1i8.nxv4i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv1i8_nxv4i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv1i8_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg5ei32.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv1i8.nxv4i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv1i8.nxv16i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i8>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv1i8.nxv16i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg5_nxv1i8_nxv16i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv1i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv1i8.nxv16i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv1i8_nxv16i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv1i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv1i8.nxv16i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv1i8.nxv1i64(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv1i8.nxv1i64(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg5_nxv1i8_nxv1i64(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv1i8_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg5ei64.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv1i8.nxv1i64(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv1i8_nxv1i64(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv1i8_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg5ei64.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv1i8.nxv1i64(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv1i8.nxv1i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv1i8.nxv1i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg5_nxv1i8_nxv1i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv1i8_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg5ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv1i8.nxv1i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv1i8_nxv1i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv1i8_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg5ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv1i8.nxv1i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv1i8.nxv8i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i16>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv1i8.nxv8i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg5_nxv1i8_nxv8i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv1i8_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv1i8.nxv8i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv1i8_nxv8i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv1i8_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv1i8.nxv8i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv1i8.nxv4i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i8>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv1i8.nxv4i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg5_nxv1i8_nxv4i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv1i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv1i8.nxv4i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv1i8_nxv4i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv1i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv1i8.nxv4i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv1i8.nxv1i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv1i8.nxv1i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg5_nxv1i8_nxv1i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv1i8_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv1i8.nxv1i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv1i8_nxv1i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv1i8_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv1i8.nxv1i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv1i8.nxv2i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i32>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv1i8.nxv2i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg5_nxv1i8_nxv2i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv1i8_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg5ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv1i8.nxv2i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv1i8_nxv2i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv1i8_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg5ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv1i8.nxv2i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv1i8.nxv8i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i8>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv1i8.nxv8i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg5_nxv1i8_nxv8i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv1i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv1i8.nxv8i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv1i8_nxv8i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv1i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv1i8.nxv8i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv1i8.nxv4i64(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i64>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv1i8.nxv4i64(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg5_nxv1i8_nxv4i64(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv1i8_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg5ei64.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv1i8.nxv4i64(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv1i8_nxv4i64(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv1i8_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg5ei64.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv1i8.nxv4i64(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv1i8.nxv64i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 64 x i8>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv1i8.nxv64i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 64 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg5_nxv1i8_nxv64i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv1i8_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv1i8.nxv64i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv1i8_nxv64i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv1i8_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv1i8.nxv64i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv1i8.nxv4i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i16>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv1i8.nxv4i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg5_nxv1i8_nxv4i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv1i8_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv1i8.nxv4i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv1i8_nxv4i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv1i8_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv1i8.nxv4i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv1i8.nxv8i64(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i64>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv1i8.nxv8i64(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg5_nxv1i8_nxv8i64(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv1i8_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg5ei64.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv1i8.nxv8i64(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv1i8_nxv8i64(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv1i8_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg5ei64.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv1i8.nxv8i64(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv1i8.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv1i8.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg5_nxv1i8_nxv1i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv1i8_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv1i8.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv1i8_nxv1i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv1i8_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv1i8.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv1i8.nxv2i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i8>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv1i8.nxv2i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg5_nxv1i8_nxv2i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv1i8_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv1i8.nxv2i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv1i8_nxv2i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv1i8_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv1i8.nxv2i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv1i8.nxv8i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i32>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv1i8.nxv8i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg5_nxv1i8_nxv8i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv1i8_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg5ei32.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv1i8.nxv8i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv1i8_nxv8i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv1i8_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg5ei32.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv1i8.nxv8i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv1i8.nxv32i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 32 x i8>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv1i8.nxv32i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 32 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg5_nxv1i8_nxv32i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv1i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv1i8.nxv32i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv1i8_nxv32i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv1i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv1i8.nxv32i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv1i8.nxv16i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i32>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv1i8.nxv16i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg5_nxv1i8_nxv16i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv1i8_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg5ei32.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv1i8.nxv16i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv1i8_nxv16i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv1i8_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg5ei32.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv1i8.nxv16i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv1i8.nxv2i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i16>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv1i8.nxv2i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg5_nxv1i8_nxv2i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv1i8_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv1i8.nxv2i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv1i8_nxv2i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv1i8_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv1i8.nxv2i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv1i8.nxv2i64(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i64>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv1i8.nxv2i64(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg5_nxv1i8_nxv2i64(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv1i8_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg5ei64.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv1i8.nxv2i64(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv1i8_nxv2i64(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv1i8_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg5ei64.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv1i8.nxv2i64(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv1i8.nxv16i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i16>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv1i8.nxv16i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg6_nxv1i8_nxv16i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv1i8_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv1i8.nxv16i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv1i8_nxv16i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv1i8_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv1i8.nxv16i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv1i8.nxv32i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 32 x i16>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv1i8.nxv32i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 32 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg6_nxv1i8_nxv32i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv1i8_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv1i8.nxv32i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv1i8_nxv32i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv1i8_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv1i8.nxv32i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv1i8.nxv4i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i32>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv1i8.nxv4i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg6_nxv1i8_nxv4i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv1i8_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg6ei32.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv1i8.nxv4i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv1i8_nxv4i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv1i8_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg6ei32.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv1i8.nxv4i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv1i8.nxv16i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i8>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv1i8.nxv16i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg6_nxv1i8_nxv16i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv1i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv1i8.nxv16i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv1i8_nxv16i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv1i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv1i8.nxv16i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv1i8.nxv1i64(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv1i8.nxv1i64(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg6_nxv1i8_nxv1i64(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv1i8_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg6ei64.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv1i8.nxv1i64(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv1i8_nxv1i64(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv1i8_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg6ei64.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv1i8.nxv1i64(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv1i8.nxv1i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv1i8.nxv1i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg6_nxv1i8_nxv1i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv1i8_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg6ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv1i8.nxv1i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv1i8_nxv1i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv1i8_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg6ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv1i8.nxv1i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv1i8.nxv8i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i16>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv1i8.nxv8i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg6_nxv1i8_nxv8i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv1i8_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv1i8.nxv8i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv1i8_nxv8i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv1i8_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv1i8.nxv8i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv1i8.nxv4i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i8>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv1i8.nxv4i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg6_nxv1i8_nxv4i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv1i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv1i8.nxv4i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv1i8_nxv4i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv1i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv1i8.nxv4i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv1i8.nxv1i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv1i8.nxv1i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg6_nxv1i8_nxv1i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv1i8_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv1i8.nxv1i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv1i8_nxv1i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv1i8_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv1i8.nxv1i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv1i8.nxv2i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i32>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv1i8.nxv2i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg6_nxv1i8_nxv2i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv1i8_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg6ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv1i8.nxv2i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv1i8_nxv2i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv1i8_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg6ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv1i8.nxv2i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv1i8.nxv8i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i8>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv1i8.nxv8i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg6_nxv1i8_nxv8i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv1i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv1i8.nxv8i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv1i8_nxv8i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv1i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv1i8.nxv8i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv1i8.nxv4i64(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i64>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv1i8.nxv4i64(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg6_nxv1i8_nxv4i64(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv1i8_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg6ei64.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv1i8.nxv4i64(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv1i8_nxv4i64(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv1i8_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg6ei64.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv1i8.nxv4i64(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv1i8.nxv64i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 64 x i8>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv1i8.nxv64i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 64 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg6_nxv1i8_nxv64i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv1i8_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv1i8.nxv64i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv1i8_nxv64i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv1i8_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv1i8.nxv64i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv1i8.nxv4i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i16>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv1i8.nxv4i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg6_nxv1i8_nxv4i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv1i8_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv1i8.nxv4i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv1i8_nxv4i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv1i8_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv1i8.nxv4i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv1i8.nxv8i64(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i64>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv1i8.nxv8i64(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg6_nxv1i8_nxv8i64(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv1i8_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg6ei64.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv1i8.nxv8i64(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv1i8_nxv8i64(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv1i8_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg6ei64.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv1i8.nxv8i64(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv1i8.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv1i8.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg6_nxv1i8_nxv1i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv1i8_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv1i8.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv1i8_nxv1i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv1i8_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv1i8.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv1i8.nxv2i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i8>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv1i8.nxv2i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg6_nxv1i8_nxv2i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv1i8_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv1i8.nxv2i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv1i8_nxv2i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv1i8_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv1i8.nxv2i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv1i8.nxv8i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i32>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv1i8.nxv8i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg6_nxv1i8_nxv8i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv1i8_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg6ei32.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv1i8.nxv8i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv1i8_nxv8i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv1i8_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg6ei32.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv1i8.nxv8i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv1i8.nxv32i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 32 x i8>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv1i8.nxv32i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 32 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg6_nxv1i8_nxv32i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv1i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv1i8.nxv32i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv1i8_nxv32i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv1i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv1i8.nxv32i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv1i8.nxv16i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i32>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv1i8.nxv16i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg6_nxv1i8_nxv16i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv1i8_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg6ei32.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv1i8.nxv16i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv1i8_nxv16i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv1i8_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg6ei32.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv1i8.nxv16i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv1i8.nxv2i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i16>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv1i8.nxv2i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg6_nxv1i8_nxv2i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv1i8_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv1i8.nxv2i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv1i8_nxv2i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv1i8_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv1i8.nxv2i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv1i8.nxv2i64(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i64>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv1i8.nxv2i64(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg6_nxv1i8_nxv2i64(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv1i8_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg6ei64.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv1i8.nxv2i64(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv1i8_nxv2i64(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv1i8_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg6ei64.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv1i8.nxv2i64(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv1i8.nxv16i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i16>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv1i8.nxv16i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg7_nxv1i8_nxv16i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv1i8_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv1i8.nxv16i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv1i8_nxv16i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv1i8_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv1i8.nxv16i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv1i8.nxv32i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 32 x i16>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv1i8.nxv32i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 32 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg7_nxv1i8_nxv32i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv1i8_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv1i8.nxv32i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv1i8_nxv32i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv1i8_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv1i8.nxv32i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv1i8.nxv4i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i32>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv1i8.nxv4i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg7_nxv1i8_nxv4i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv1i8_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg7ei32.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv1i8.nxv4i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv1i8_nxv4i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv1i8_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg7ei32.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv1i8.nxv4i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv1i8.nxv16i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i8>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv1i8.nxv16i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg7_nxv1i8_nxv16i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv1i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv1i8.nxv16i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv1i8_nxv16i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv1i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv1i8.nxv16i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv1i8.nxv1i64(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv1i8.nxv1i64(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg7_nxv1i8_nxv1i64(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv1i8_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg7ei64.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv1i8.nxv1i64(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv1i8_nxv1i64(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv1i8_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg7ei64.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv1i8.nxv1i64(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv1i8.nxv1i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv1i8.nxv1i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg7_nxv1i8_nxv1i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv1i8_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg7ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv1i8.nxv1i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv1i8_nxv1i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv1i8_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg7ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv1i8.nxv1i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv1i8.nxv8i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i16>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv1i8.nxv8i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg7_nxv1i8_nxv8i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv1i8_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv1i8.nxv8i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv1i8_nxv8i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv1i8_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv1i8.nxv8i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv1i8.nxv4i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i8>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv1i8.nxv4i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg7_nxv1i8_nxv4i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv1i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv1i8.nxv4i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv1i8_nxv4i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv1i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv1i8.nxv4i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv1i8.nxv1i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv1i8.nxv1i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg7_nxv1i8_nxv1i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv1i8_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv1i8.nxv1i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv1i8_nxv1i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv1i8_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv1i8.nxv1i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv1i8.nxv2i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i32>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv1i8.nxv2i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg7_nxv1i8_nxv2i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv1i8_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg7ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv1i8.nxv2i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv1i8_nxv2i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv1i8_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg7ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv1i8.nxv2i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv1i8.nxv8i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i8>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv1i8.nxv8i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg7_nxv1i8_nxv8i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv1i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv1i8.nxv8i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv1i8_nxv8i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv1i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv1i8.nxv8i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv1i8.nxv4i64(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i64>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv1i8.nxv4i64(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg7_nxv1i8_nxv4i64(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv1i8_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg7ei64.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv1i8.nxv4i64(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv1i8_nxv4i64(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv1i8_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg7ei64.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv1i8.nxv4i64(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv1i8.nxv64i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 64 x i8>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv1i8.nxv64i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 64 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg7_nxv1i8_nxv64i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv1i8_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv1i8.nxv64i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv1i8_nxv64i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv1i8_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv1i8.nxv64i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv1i8.nxv4i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i16>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv1i8.nxv4i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg7_nxv1i8_nxv4i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv1i8_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv1i8.nxv4i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv1i8_nxv4i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv1i8_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv1i8.nxv4i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv1i8.nxv8i64(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i64>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv1i8.nxv8i64(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg7_nxv1i8_nxv8i64(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv1i8_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg7ei64.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv1i8.nxv8i64(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv1i8_nxv8i64(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv1i8_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg7ei64.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv1i8.nxv8i64(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv1i8.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv1i8.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg7_nxv1i8_nxv1i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv1i8_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv1i8.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv1i8_nxv1i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv1i8_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv1i8.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv1i8.nxv2i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i8>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv1i8.nxv2i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg7_nxv1i8_nxv2i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv1i8_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv1i8.nxv2i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv1i8_nxv2i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv1i8_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv1i8.nxv2i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv1i8.nxv8i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i32>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv1i8.nxv8i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg7_nxv1i8_nxv8i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv1i8_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg7ei32.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv1i8.nxv8i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv1i8_nxv8i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv1i8_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg7ei32.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv1i8.nxv8i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv1i8.nxv32i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 32 x i8>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv1i8.nxv32i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 32 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg7_nxv1i8_nxv32i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv1i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv1i8.nxv32i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv1i8_nxv32i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv1i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv1i8.nxv32i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv1i8.nxv16i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i32>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv1i8.nxv16i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg7_nxv1i8_nxv16i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv1i8_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg7ei32.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv1i8.nxv16i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv1i8_nxv16i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv1i8_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg7ei32.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv1i8.nxv16i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv1i8.nxv2i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i16>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv1i8.nxv2i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg7_nxv1i8_nxv2i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv1i8_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv1i8.nxv2i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv1i8_nxv2i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv1i8_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv1i8.nxv2i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv1i8.nxv2i64(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i64>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv1i8.nxv2i64(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg7_nxv1i8_nxv2i64(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv1i8_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg7ei64.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv1i8.nxv2i64(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv1i8_nxv2i64(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv1i8_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg7ei64.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv1i8.nxv2i64(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv1i8.nxv16i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i16>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv1i8.nxv16i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg8_nxv1i8_nxv16i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv1i8_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv1i8.nxv16i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv1i8_nxv16i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv1i8_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv1i8.nxv16i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv1i8.nxv32i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 32 x i16>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv1i8.nxv32i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 32 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg8_nxv1i8_nxv32i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv1i8_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vmv1r.v v23, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv1i8.nxv32i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv1i8_nxv32i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv1i8_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vmv1r.v v23, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv1i8.nxv32i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv1i8.nxv4i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i32>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv1i8.nxv4i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg8_nxv1i8_nxv4i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv1i8_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg8ei32.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv1i8.nxv4i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv1i8_nxv4i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv1i8_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg8ei32.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv1i8.nxv4i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv1i8.nxv16i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i8>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv1i8.nxv16i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg8_nxv1i8_nxv16i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv1i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv1i8.nxv16i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv1i8_nxv16i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv1i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv1i8.nxv16i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv1i8.nxv1i64(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv1i8.nxv1i64(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg8_nxv1i8_nxv1i64(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv1i8_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg8ei64.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv1i8.nxv1i64(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv1i8_nxv1i64(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv1i8_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg8ei64.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv1i8.nxv1i64(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv1i8.nxv1i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv1i8.nxv1i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg8_nxv1i8_nxv1i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv1i8_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg8ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv1i8.nxv1i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv1i8_nxv1i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv1i8_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg8ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv1i8.nxv1i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv1i8.nxv8i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i16>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv1i8.nxv8i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg8_nxv1i8_nxv8i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv1i8_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv1i8.nxv8i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv1i8_nxv8i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv1i8_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv1i8.nxv8i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv1i8.nxv4i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i8>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv1i8.nxv4i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg8_nxv1i8_nxv4i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv1i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv1i8.nxv4i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv1i8_nxv4i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv1i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv1i8.nxv4i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv1i8.nxv1i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv1i8.nxv1i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg8_nxv1i8_nxv1i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv1i8_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv1i8.nxv1i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv1i8_nxv1i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv1i8_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv1i8.nxv1i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv1i8.nxv2i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i32>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv1i8.nxv2i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg8_nxv1i8_nxv2i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv1i8_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg8ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv1i8.nxv2i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv1i8_nxv2i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv1i8_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg8ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv1i8.nxv2i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv1i8.nxv8i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i8>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv1i8.nxv8i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg8_nxv1i8_nxv8i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv1i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv1i8.nxv8i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv1i8_nxv8i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv1i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv1i8.nxv8i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv1i8.nxv4i64(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i64>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv1i8.nxv4i64(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg8_nxv1i8_nxv4i64(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv1i8_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg8ei64.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv1i8.nxv4i64(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv1i8_nxv4i64(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv1i8_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg8ei64.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv1i8.nxv4i64(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv1i8.nxv64i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 64 x i8>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv1i8.nxv64i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 64 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg8_nxv1i8_nxv64i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv1i8_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vmv1r.v v23, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv1i8.nxv64i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv1i8_nxv64i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv1i8_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vmv1r.v v23, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv1i8.nxv64i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv1i8.nxv4i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i16>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv1i8.nxv4i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 4 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg8_nxv1i8_nxv4i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv1i8_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv1i8.nxv4i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv1i8_nxv4i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv1i8_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv1i8.nxv4i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv1i8.nxv8i64(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i64>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv1i8.nxv8i64(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg8_nxv1i8_nxv8i64(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv1i8_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vmv1r.v v23, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg8ei64.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv1i8.nxv8i64(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv1i8_nxv8i64(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv1i8_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vmv1r.v v23, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg8ei64.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv1i8.nxv8i64(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv1i8.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv1i8.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg8_nxv1i8_nxv1i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv1i8_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv1i8.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv1i8_nxv1i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv1i8_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv1i8.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv1i8.nxv2i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i8>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv1i8.nxv2i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg8_nxv1i8_nxv2i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv1i8_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv1i8.nxv2i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv1i8_nxv2i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv1i8_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv1i8.nxv2i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv1i8.nxv8i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i32>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv1i8.nxv8i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 8 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg8_nxv1i8_nxv8i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv1i8_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg8ei32.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv1i8.nxv8i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv1i8_nxv8i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv1i8_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg8ei32.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv1i8.nxv8i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv1i8.nxv32i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 32 x i8>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv1i8.nxv32i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 32 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg8_nxv1i8_nxv32i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv1i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv1i8.nxv32i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv1i8_nxv32i8(<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv1i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv1i8.nxv32i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv1i8.nxv16i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i32>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv1i8.nxv16i32(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 16 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg8_nxv1i8_nxv16i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv1i8_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vmv1r.v v23, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg8ei32.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv1i8.nxv16i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv1i8_nxv16i32(<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv1i8_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vmv1r.v v23, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg8ei32.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv1i8.nxv16i32(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv1i8.nxv2i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i16>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv1i8.nxv2i16(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg8_nxv1i8_nxv2i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv1i8_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv1i8.nxv2i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv1i8_nxv2i16(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv1i8_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv1i8.nxv2i16(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv1i8.nxv2i64(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i64>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv1i8.nxv2i64(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 2 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg8_nxv1i8_nxv2i64(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv1i8_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg8ei64.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv1i8.nxv2i64(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv1i8_nxv2i64(<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv1i8_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vsxseg8ei64.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv1i8.nxv2i64(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv2i8.nxv16i16(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i16>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv2i8.nxv16i16(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg2_nxv2i8_nxv16i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv2i8_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv2i8.nxv16i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv2i8_nxv16i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv2i8_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv2i8.nxv16i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv2i8.nxv32i16(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 32 x i16>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv2i8.nxv32i16(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 32 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg2_nxv2i8_nxv32i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv2i8_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv2i8.nxv32i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv2i8_nxv32i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv2i8_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv2i8.nxv32i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv2i8.nxv4i32(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i32>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv2i8.nxv4i32(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg2_nxv2i8_nxv4i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv2i8_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv2i8.nxv4i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv2i8_nxv4i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv2i8_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv2i8.nxv4i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv2i8.nxv16i8(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv2i8.nxv16i8(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg2_nxv2i8_nxv16i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv2i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv2i8.nxv16i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv2i8_nxv16i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv2i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv2i8.nxv16i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv2i8.nxv1i64(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv2i8.nxv1i64(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i64>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg2_nxv2i8_nxv1i64(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv2i8_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv2i8.nxv1i64(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv2i8_nxv1i64(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv2i8_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv2i8.nxv1i64(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv2i8.nxv1i32(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv2i8.nxv1i32(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg2_nxv2i8_nxv1i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv2i8_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv2i8.nxv1i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv2i8_nxv1i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv2i8_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv2i8.nxv1i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv2i8.nxv8i16(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i16>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv2i8.nxv8i16(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg2_nxv2i8_nxv8i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv2i8_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv2i8.nxv8i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv2i8_nxv8i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv2i8_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv2i8.nxv8i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv2i8.nxv4i8(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv2i8.nxv4i8(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg2_nxv2i8_nxv4i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv2i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv2i8.nxv4i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv2i8_nxv4i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv2i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv2i8.nxv4i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv2i8.nxv1i16(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv2i8.nxv1i16(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg2_nxv2i8_nxv1i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv2i8_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv2i8.nxv1i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv2i8_nxv1i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv2i8_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv2i8.nxv1i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv2i8.nxv2i32(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i32>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv2i8.nxv2i32(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg2_nxv2i8_nxv2i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv2i8_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv2i8.nxv2i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv2i8_nxv2i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv2i8_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv2i8.nxv2i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv2i8.nxv8i8(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv2i8.nxv8i8(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg2_nxv2i8_nxv8i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv2i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv2i8.nxv8i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv2i8_nxv8i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv2i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv2i8.nxv8i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv2i8.nxv4i64(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i64>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv2i8.nxv4i64(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i64>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg2_nxv2i8_nxv4i64(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv2i8_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv2i8.nxv4i64(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv2i8_nxv4i64(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv2i8_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv2i8.nxv4i64(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv2i8.nxv64i8(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 64 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv2i8.nxv64i8(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 64 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg2_nxv2i8_nxv64i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv2i8_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv2i8.nxv64i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv2i8_nxv64i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv2i8_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv2i8.nxv64i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv2i8.nxv4i16(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i16>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv2i8.nxv4i16(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg2_nxv2i8_nxv4i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv2i8_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv2i8.nxv4i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv2i8_nxv4i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv2i8_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv2i8.nxv4i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv2i8.nxv8i64(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i64>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv2i8.nxv8i64(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i64>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg2_nxv2i8_nxv8i64(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv2i8_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv2i8.nxv8i64(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv2i8_nxv8i64(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv2i8_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv2i8.nxv8i64(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv2i8.nxv1i8(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv2i8.nxv1i8(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg2_nxv2i8_nxv1i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv2i8_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv2i8.nxv1i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv2i8_nxv1i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv2i8_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv2i8.nxv1i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv2i8.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv2i8.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg2_nxv2i8_nxv2i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv2i8_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv2i8.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv2i8_nxv2i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv2i8_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv2i8.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv2i8.nxv8i32(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i32>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv2i8.nxv8i32(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg2_nxv2i8_nxv8i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv2i8_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv2i8.nxv8i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv2i8_nxv8i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv2i8_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv2i8.nxv8i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv2i8.nxv32i8(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 32 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv2i8.nxv32i8(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 32 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg2_nxv2i8_nxv32i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv2i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv2i8.nxv32i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv2i8_nxv32i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv2i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv2i8.nxv32i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv2i8.nxv16i32(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i32>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv2i8.nxv16i32(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg2_nxv2i8_nxv16i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv2i8_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv2i8.nxv16i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv2i8_nxv16i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv2i8_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv2i8.nxv16i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv2i8.nxv2i16(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i16>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv2i8.nxv2i16(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg2_nxv2i8_nxv2i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv2i8_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv2i8.nxv2i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv2i8_nxv2i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv2i8_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv2i8.nxv2i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv2i8.nxv2i64(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i64>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv2i8.nxv2i64(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg2_nxv2i8_nxv2i64(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv2i8_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv2i8.nxv2i64(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv2i8_nxv2i64(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv2i8_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv2i8.nxv2i64(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv2i8.nxv16i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i16>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv2i8.nxv16i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg3_nxv2i8_nxv16i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv2i8_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv2i8.nxv16i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv2i8_nxv16i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv2i8_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv2i8.nxv16i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv2i8.nxv32i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 32 x i16>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv2i8.nxv32i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 32 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg3_nxv2i8_nxv32i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv2i8_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv2i8.nxv32i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv2i8_nxv32i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv2i8_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv2i8.nxv32i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv2i8.nxv4i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i32>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv2i8.nxv4i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg3_nxv2i8_nxv4i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv2i8_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv2i8.nxv4i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv2i8_nxv4i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv2i8_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv2i8.nxv4i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv2i8.nxv16i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i8>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv2i8.nxv16i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg3_nxv2i8_nxv16i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv2i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv2i8.nxv16i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv2i8_nxv16i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv2i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv2i8.nxv16i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv2i8.nxv1i64(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv2i8.nxv1i64(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i64>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg3_nxv2i8_nxv1i64(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv2i8_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg3ei64.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv2i8.nxv1i64(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv2i8_nxv1i64(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv2i8_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg3ei64.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv2i8.nxv1i64(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv2i8.nxv1i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv2i8.nxv1i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg3_nxv2i8_nxv1i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv2i8_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv2i8.nxv1i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv2i8_nxv1i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv2i8_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv2i8.nxv1i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv2i8.nxv8i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i16>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv2i8.nxv8i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg3_nxv2i8_nxv8i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv2i8_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv2i8.nxv8i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv2i8_nxv8i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv2i8_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv2i8.nxv8i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv2i8.nxv4i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i8>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv2i8.nxv4i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg3_nxv2i8_nxv4i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv2i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv2i8.nxv4i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv2i8_nxv4i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv2i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv2i8.nxv4i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv2i8.nxv1i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv2i8.nxv1i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg3_nxv2i8_nxv1i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv2i8_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv2i8.nxv1i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv2i8_nxv1i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv2i8_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv2i8.nxv1i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv2i8.nxv2i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i32>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv2i8.nxv2i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg3_nxv2i8_nxv2i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv2i8_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv2i8.nxv2i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv2i8_nxv2i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv2i8_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv2i8.nxv2i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv2i8.nxv8i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i8>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv2i8.nxv8i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg3_nxv2i8_nxv8i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv2i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv2i8.nxv8i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv2i8_nxv8i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv2i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv2i8.nxv8i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv2i8.nxv4i64(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i64>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv2i8.nxv4i64(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i64>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg3_nxv2i8_nxv4i64(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv2i8_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg3ei64.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv2i8.nxv4i64(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv2i8_nxv4i64(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv2i8_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg3ei64.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv2i8.nxv4i64(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv2i8.nxv64i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 64 x i8>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv2i8.nxv64i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 64 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg3_nxv2i8_nxv64i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv2i8_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv2i8.nxv64i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv2i8_nxv64i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv2i8_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv2i8.nxv64i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv2i8.nxv4i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i16>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv2i8.nxv4i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg3_nxv2i8_nxv4i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv2i8_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv2i8.nxv4i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv2i8_nxv4i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv2i8_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv2i8.nxv4i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv2i8.nxv8i64(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i64>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv2i8.nxv8i64(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i64>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg3_nxv2i8_nxv8i64(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv2i8_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg3ei64.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv2i8.nxv8i64(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv2i8_nxv8i64(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv2i8_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg3ei64.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv2i8.nxv8i64(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv2i8.nxv1i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv2i8.nxv1i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg3_nxv2i8_nxv1i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv2i8_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv2i8.nxv1i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv2i8_nxv1i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv2i8_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv2i8.nxv1i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv2i8.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i8>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv2i8.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg3_nxv2i8_nxv2i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv2i8_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv2i8.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv2i8_nxv2i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv2i8_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv2i8.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv2i8.nxv8i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i32>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv2i8.nxv8i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg3_nxv2i8_nxv8i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv2i8_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv2i8.nxv8i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv2i8_nxv8i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv2i8_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv2i8.nxv8i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv2i8.nxv32i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 32 x i8>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv2i8.nxv32i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 32 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg3_nxv2i8_nxv32i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv2i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv2i8.nxv32i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv2i8_nxv32i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv2i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv2i8.nxv32i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv2i8.nxv16i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i32>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv2i8.nxv16i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg3_nxv2i8_nxv16i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv2i8_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv2i8.nxv16i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv2i8_nxv16i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv2i8_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv2i8.nxv16i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv2i8.nxv2i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i16>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv2i8.nxv2i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg3_nxv2i8_nxv2i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv2i8_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv2i8.nxv2i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv2i8_nxv2i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv2i8_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv2i8.nxv2i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv2i8.nxv2i64(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i64>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv2i8.nxv2i64(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg3_nxv2i8_nxv2i64(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv2i8_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg3ei64.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv2i8.nxv2i64(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv2i8_nxv2i64(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv2i8_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg3ei64.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv2i8.nxv2i64(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv2i8.nxv16i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i16>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv2i8.nxv16i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg4_nxv2i8_nxv16i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv2i8_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv2i8.nxv16i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv2i8_nxv16i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv2i8_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv2i8.nxv16i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv2i8.nxv32i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 32 x i16>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv2i8.nxv32i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 32 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg4_nxv2i8_nxv32i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv2i8_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv2i8.nxv32i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv2i8_nxv32i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv2i8_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv2i8.nxv32i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv2i8.nxv4i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i32>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv2i8.nxv4i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg4_nxv2i8_nxv4i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv2i8_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv2i8.nxv4i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv2i8_nxv4i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv2i8_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv2i8.nxv4i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv2i8.nxv16i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i8>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv2i8.nxv16i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg4_nxv2i8_nxv16i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv2i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv2i8.nxv16i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv2i8_nxv16i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv2i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv2i8.nxv16i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv2i8.nxv1i64(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv2i8.nxv1i64(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i64>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg4_nxv2i8_nxv1i64(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv2i8_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg4ei64.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv2i8.nxv1i64(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv2i8_nxv1i64(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv2i8_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg4ei64.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv2i8.nxv1i64(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv2i8.nxv1i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv2i8.nxv1i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg4_nxv2i8_nxv1i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv2i8_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv2i8.nxv1i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv2i8_nxv1i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv2i8_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv2i8.nxv1i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv2i8.nxv8i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i16>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv2i8.nxv8i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg4_nxv2i8_nxv8i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv2i8_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv2i8.nxv8i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv2i8_nxv8i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv2i8_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv2i8.nxv8i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv2i8.nxv4i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i8>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv2i8.nxv4i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg4_nxv2i8_nxv4i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv2i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv2i8.nxv4i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv2i8_nxv4i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv2i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv2i8.nxv4i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv2i8.nxv1i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv2i8.nxv1i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg4_nxv2i8_nxv1i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv2i8_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv2i8.nxv1i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv2i8_nxv1i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv2i8_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv2i8.nxv1i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv2i8.nxv2i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i32>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv2i8.nxv2i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg4_nxv2i8_nxv2i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv2i8_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv2i8.nxv2i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv2i8_nxv2i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv2i8_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv2i8.nxv2i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv2i8.nxv8i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i8>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv2i8.nxv8i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg4_nxv2i8_nxv8i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv2i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv2i8.nxv8i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv2i8_nxv8i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv2i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv2i8.nxv8i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv2i8.nxv4i64(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i64>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv2i8.nxv4i64(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i64>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg4_nxv2i8_nxv4i64(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv2i8_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg4ei64.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv2i8.nxv4i64(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv2i8_nxv4i64(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv2i8_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg4ei64.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv2i8.nxv4i64(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv2i8.nxv64i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 64 x i8>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv2i8.nxv64i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 64 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg4_nxv2i8_nxv64i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv2i8_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv2i8.nxv64i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv2i8_nxv64i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv2i8_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv2i8.nxv64i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv2i8.nxv4i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i16>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv2i8.nxv4i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg4_nxv2i8_nxv4i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv2i8_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv2i8.nxv4i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv2i8_nxv4i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv2i8_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv2i8.nxv4i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv2i8.nxv8i64(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i64>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv2i8.nxv8i64(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i64>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg4_nxv2i8_nxv8i64(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv2i8_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg4ei64.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv2i8.nxv8i64(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv2i8_nxv8i64(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv2i8_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg4ei64.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv2i8.nxv8i64(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv2i8.nxv1i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv2i8.nxv1i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg4_nxv2i8_nxv1i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv2i8_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv2i8.nxv1i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv2i8_nxv1i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv2i8_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv2i8.nxv1i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv2i8.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i8>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv2i8.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg4_nxv2i8_nxv2i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv2i8_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv2i8.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv2i8_nxv2i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv2i8_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv2i8.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv2i8.nxv8i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i32>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv2i8.nxv8i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg4_nxv2i8_nxv8i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv2i8_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv2i8.nxv8i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv2i8_nxv8i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv2i8_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv2i8.nxv8i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv2i8.nxv32i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 32 x i8>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv2i8.nxv32i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 32 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg4_nxv2i8_nxv32i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv2i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv2i8.nxv32i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv2i8_nxv32i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv2i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv2i8.nxv32i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv2i8.nxv16i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i32>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv2i8.nxv16i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg4_nxv2i8_nxv16i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv2i8_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv2i8.nxv16i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv2i8_nxv16i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv2i8_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv2i8.nxv16i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv2i8.nxv2i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i16>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv2i8.nxv2i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg4_nxv2i8_nxv2i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv2i8_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv2i8.nxv2i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv2i8_nxv2i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv2i8_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv2i8.nxv2i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv2i8.nxv2i64(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i64>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv2i8.nxv2i64(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg4_nxv2i8_nxv2i64(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv2i8_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg4ei64.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv2i8.nxv2i64(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv2i8_nxv2i64(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv2i8_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg4ei64.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv2i8.nxv2i64(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv2i8.nxv16i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i16>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv2i8.nxv16i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg5_nxv2i8_nxv16i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv2i8_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv2i8.nxv16i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv2i8_nxv16i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv2i8_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv2i8.nxv16i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv2i8.nxv32i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 32 x i16>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv2i8.nxv32i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 32 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg5_nxv2i8_nxv32i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv2i8_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv2i8.nxv32i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv2i8_nxv32i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv2i8_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv2i8.nxv32i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv2i8.nxv4i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i32>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv2i8.nxv4i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg5_nxv2i8_nxv4i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv2i8_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg5ei32.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv2i8.nxv4i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv2i8_nxv4i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv2i8_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg5ei32.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv2i8.nxv4i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv2i8.nxv16i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i8>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv2i8.nxv16i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg5_nxv2i8_nxv16i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv2i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv2i8.nxv16i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv2i8_nxv16i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv2i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv2i8.nxv16i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv2i8.nxv1i64(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv2i8.nxv1i64(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i64>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg5_nxv2i8_nxv1i64(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv2i8_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg5ei64.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv2i8.nxv1i64(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv2i8_nxv1i64(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv2i8_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg5ei64.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv2i8.nxv1i64(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv2i8.nxv1i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv2i8.nxv1i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg5_nxv2i8_nxv1i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv2i8_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg5ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv2i8.nxv1i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv2i8_nxv1i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv2i8_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg5ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv2i8.nxv1i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv2i8.nxv8i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i16>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv2i8.nxv8i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg5_nxv2i8_nxv8i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv2i8_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv2i8.nxv8i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv2i8_nxv8i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv2i8_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv2i8.nxv8i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv2i8.nxv4i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i8>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv2i8.nxv4i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg5_nxv2i8_nxv4i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv2i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv2i8.nxv4i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv2i8_nxv4i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv2i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv2i8.nxv4i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv2i8.nxv1i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv2i8.nxv1i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg5_nxv2i8_nxv1i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv2i8_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv2i8.nxv1i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv2i8_nxv1i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv2i8_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv2i8.nxv1i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv2i8.nxv2i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i32>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv2i8.nxv2i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg5_nxv2i8_nxv2i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv2i8_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg5ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv2i8.nxv2i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv2i8_nxv2i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv2i8_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg5ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv2i8.nxv2i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv2i8.nxv8i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i8>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv2i8.nxv8i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg5_nxv2i8_nxv8i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv2i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv2i8.nxv8i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv2i8_nxv8i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv2i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv2i8.nxv8i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv2i8.nxv4i64(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i64>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv2i8.nxv4i64(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i64>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg5_nxv2i8_nxv4i64(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv2i8_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg5ei64.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv2i8.nxv4i64(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv2i8_nxv4i64(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv2i8_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg5ei64.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv2i8.nxv4i64(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv2i8.nxv64i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 64 x i8>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv2i8.nxv64i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 64 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg5_nxv2i8_nxv64i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv2i8_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv2i8.nxv64i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv2i8_nxv64i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv2i8_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv2i8.nxv64i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv2i8.nxv4i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i16>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv2i8.nxv4i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg5_nxv2i8_nxv4i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv2i8_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv2i8.nxv4i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv2i8_nxv4i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv2i8_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv2i8.nxv4i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv2i8.nxv8i64(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i64>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv2i8.nxv8i64(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i64>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg5_nxv2i8_nxv8i64(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv2i8_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg5ei64.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv2i8.nxv8i64(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv2i8_nxv8i64(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv2i8_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg5ei64.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv2i8.nxv8i64(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv2i8.nxv1i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv2i8.nxv1i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg5_nxv2i8_nxv1i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv2i8_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv2i8.nxv1i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv2i8_nxv1i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv2i8_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv2i8.nxv1i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv2i8.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i8>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv2i8.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg5_nxv2i8_nxv2i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv2i8_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv2i8.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv2i8_nxv2i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv2i8_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv2i8.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv2i8.nxv8i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i32>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv2i8.nxv8i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg5_nxv2i8_nxv8i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv2i8_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg5ei32.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv2i8.nxv8i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv2i8_nxv8i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv2i8_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg5ei32.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv2i8.nxv8i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv2i8.nxv32i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 32 x i8>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv2i8.nxv32i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 32 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg5_nxv2i8_nxv32i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv2i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv2i8.nxv32i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv2i8_nxv32i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv2i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv2i8.nxv32i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv2i8.nxv16i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i32>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv2i8.nxv16i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg5_nxv2i8_nxv16i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv2i8_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg5ei32.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv2i8.nxv16i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv2i8_nxv16i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv2i8_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg5ei32.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv2i8.nxv16i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv2i8.nxv2i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i16>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv2i8.nxv2i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg5_nxv2i8_nxv2i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv2i8_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv2i8.nxv2i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv2i8_nxv2i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv2i8_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv2i8.nxv2i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv2i8.nxv2i64(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i64>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv2i8.nxv2i64(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg5_nxv2i8_nxv2i64(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv2i8_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg5ei64.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv2i8.nxv2i64(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv2i8_nxv2i64(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv2i8_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg5ei64.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv2i8.nxv2i64(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv2i8.nxv16i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i16>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv2i8.nxv16i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg6_nxv2i8_nxv16i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv2i8_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv2i8.nxv16i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv2i8_nxv16i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv2i8_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv2i8.nxv16i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv2i8.nxv32i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 32 x i16>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv2i8.nxv32i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 32 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg6_nxv2i8_nxv32i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv2i8_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv2i8.nxv32i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv2i8_nxv32i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv2i8_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv2i8.nxv32i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv2i8.nxv4i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i32>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv2i8.nxv4i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg6_nxv2i8_nxv4i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv2i8_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg6ei32.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv2i8.nxv4i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv2i8_nxv4i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv2i8_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg6ei32.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv2i8.nxv4i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv2i8.nxv16i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i8>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv2i8.nxv16i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg6_nxv2i8_nxv16i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv2i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv2i8.nxv16i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv2i8_nxv16i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv2i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv2i8.nxv16i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv2i8.nxv1i64(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv2i8.nxv1i64(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i64>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg6_nxv2i8_nxv1i64(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv2i8_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg6ei64.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv2i8.nxv1i64(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv2i8_nxv1i64(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv2i8_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg6ei64.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv2i8.nxv1i64(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv2i8.nxv1i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv2i8.nxv1i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg6_nxv2i8_nxv1i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv2i8_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg6ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv2i8.nxv1i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv2i8_nxv1i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv2i8_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg6ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv2i8.nxv1i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv2i8.nxv8i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i16>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv2i8.nxv8i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg6_nxv2i8_nxv8i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv2i8_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv2i8.nxv8i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv2i8_nxv8i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv2i8_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv2i8.nxv8i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv2i8.nxv4i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i8>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv2i8.nxv4i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg6_nxv2i8_nxv4i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv2i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv2i8.nxv4i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv2i8_nxv4i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv2i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv2i8.nxv4i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv2i8.nxv1i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv2i8.nxv1i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg6_nxv2i8_nxv1i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv2i8_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv2i8.nxv1i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv2i8_nxv1i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv2i8_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv2i8.nxv1i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv2i8.nxv2i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i32>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv2i8.nxv2i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg6_nxv2i8_nxv2i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv2i8_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg6ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv2i8.nxv2i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv2i8_nxv2i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv2i8_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg6ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv2i8.nxv2i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv2i8.nxv8i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i8>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv2i8.nxv8i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg6_nxv2i8_nxv8i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv2i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv2i8.nxv8i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv2i8_nxv8i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv2i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv2i8.nxv8i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv2i8.nxv4i64(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i64>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv2i8.nxv4i64(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i64>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg6_nxv2i8_nxv4i64(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv2i8_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg6ei64.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv2i8.nxv4i64(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv2i8_nxv4i64(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv2i8_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg6ei64.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv2i8.nxv4i64(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv2i8.nxv64i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 64 x i8>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv2i8.nxv64i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 64 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg6_nxv2i8_nxv64i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv2i8_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv2i8.nxv64i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv2i8_nxv64i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv2i8_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv2i8.nxv64i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv2i8.nxv4i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i16>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv2i8.nxv4i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg6_nxv2i8_nxv4i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv2i8_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv2i8.nxv4i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv2i8_nxv4i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv2i8_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv2i8.nxv4i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv2i8.nxv8i64(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i64>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv2i8.nxv8i64(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i64>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg6_nxv2i8_nxv8i64(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv2i8_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg6ei64.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv2i8.nxv8i64(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv2i8_nxv8i64(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv2i8_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg6ei64.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv2i8.nxv8i64(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv2i8.nxv1i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv2i8.nxv1i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg6_nxv2i8_nxv1i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv2i8_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv2i8.nxv1i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv2i8_nxv1i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv2i8_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv2i8.nxv1i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv2i8.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i8>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv2i8.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg6_nxv2i8_nxv2i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv2i8_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv2i8.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv2i8_nxv2i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv2i8_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv2i8.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv2i8.nxv8i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i32>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv2i8.nxv8i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg6_nxv2i8_nxv8i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv2i8_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg6ei32.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv2i8.nxv8i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv2i8_nxv8i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv2i8_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg6ei32.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv2i8.nxv8i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv2i8.nxv32i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 32 x i8>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv2i8.nxv32i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 32 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg6_nxv2i8_nxv32i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv2i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv2i8.nxv32i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv2i8_nxv32i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv2i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv2i8.nxv32i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv2i8.nxv16i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i32>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv2i8.nxv16i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg6_nxv2i8_nxv16i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv2i8_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg6ei32.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv2i8.nxv16i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv2i8_nxv16i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv2i8_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg6ei32.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv2i8.nxv16i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv2i8.nxv2i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i16>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv2i8.nxv2i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg6_nxv2i8_nxv2i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv2i8_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv2i8.nxv2i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv2i8_nxv2i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv2i8_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv2i8.nxv2i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv2i8.nxv2i64(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i64>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv2i8.nxv2i64(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg6_nxv2i8_nxv2i64(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv2i8_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg6ei64.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv2i8.nxv2i64(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv2i8_nxv2i64(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv2i8_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg6ei64.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv2i8.nxv2i64(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv2i8.nxv16i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i16>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv2i8.nxv16i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg7_nxv2i8_nxv16i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv2i8_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv2i8.nxv16i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv2i8_nxv16i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv2i8_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv2i8.nxv16i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv2i8.nxv32i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 32 x i16>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv2i8.nxv32i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 32 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg7_nxv2i8_nxv32i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv2i8_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv2i8.nxv32i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv2i8_nxv32i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv2i8_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv2i8.nxv32i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv2i8.nxv4i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i32>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv2i8.nxv4i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg7_nxv2i8_nxv4i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv2i8_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg7ei32.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv2i8.nxv4i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv2i8_nxv4i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv2i8_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg7ei32.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv2i8.nxv4i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv2i8.nxv16i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i8>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv2i8.nxv16i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg7_nxv2i8_nxv16i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv2i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv2i8.nxv16i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv2i8_nxv16i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv2i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv2i8.nxv16i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv2i8.nxv1i64(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv2i8.nxv1i64(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i64>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg7_nxv2i8_nxv1i64(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv2i8_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg7ei64.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv2i8.nxv1i64(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv2i8_nxv1i64(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv2i8_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg7ei64.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv2i8.nxv1i64(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv2i8.nxv1i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv2i8.nxv1i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg7_nxv2i8_nxv1i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv2i8_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg7ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv2i8.nxv1i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv2i8_nxv1i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv2i8_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg7ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv2i8.nxv1i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv2i8.nxv8i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i16>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv2i8.nxv8i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg7_nxv2i8_nxv8i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv2i8_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv2i8.nxv8i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv2i8_nxv8i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv2i8_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv2i8.nxv8i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv2i8.nxv4i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i8>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv2i8.nxv4i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg7_nxv2i8_nxv4i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv2i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv2i8.nxv4i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv2i8_nxv4i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv2i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv2i8.nxv4i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv2i8.nxv1i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv2i8.nxv1i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg7_nxv2i8_nxv1i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv2i8_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv2i8.nxv1i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv2i8_nxv1i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv2i8_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv2i8.nxv1i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv2i8.nxv2i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i32>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv2i8.nxv2i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg7_nxv2i8_nxv2i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv2i8_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg7ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv2i8.nxv2i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv2i8_nxv2i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv2i8_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg7ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv2i8.nxv2i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv2i8.nxv8i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i8>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv2i8.nxv8i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg7_nxv2i8_nxv8i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv2i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv2i8.nxv8i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv2i8_nxv8i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv2i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv2i8.nxv8i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv2i8.nxv4i64(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i64>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv2i8.nxv4i64(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i64>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg7_nxv2i8_nxv4i64(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv2i8_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg7ei64.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv2i8.nxv4i64(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv2i8_nxv4i64(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv2i8_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg7ei64.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv2i8.nxv4i64(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv2i8.nxv64i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 64 x i8>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv2i8.nxv64i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 64 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg7_nxv2i8_nxv64i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv2i8_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv2i8.nxv64i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv2i8_nxv64i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv2i8_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv2i8.nxv64i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv2i8.nxv4i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i16>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv2i8.nxv4i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg7_nxv2i8_nxv4i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv2i8_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv2i8.nxv4i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv2i8_nxv4i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv2i8_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv2i8.nxv4i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv2i8.nxv8i64(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i64>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv2i8.nxv8i64(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i64>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg7_nxv2i8_nxv8i64(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv2i8_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg7ei64.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv2i8.nxv8i64(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv2i8_nxv8i64(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv2i8_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg7ei64.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv2i8.nxv8i64(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv2i8.nxv1i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv2i8.nxv1i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg7_nxv2i8_nxv1i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv2i8_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv2i8.nxv1i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv2i8_nxv1i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv2i8_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv2i8.nxv1i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv2i8.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i8>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv2i8.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg7_nxv2i8_nxv2i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv2i8_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv2i8.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv2i8_nxv2i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv2i8_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv2i8.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv2i8.nxv8i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i32>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv2i8.nxv8i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg7_nxv2i8_nxv8i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv2i8_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg7ei32.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv2i8.nxv8i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv2i8_nxv8i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv2i8_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg7ei32.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv2i8.nxv8i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv2i8.nxv32i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 32 x i8>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv2i8.nxv32i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 32 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg7_nxv2i8_nxv32i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv2i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv2i8.nxv32i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv2i8_nxv32i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv2i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv2i8.nxv32i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv2i8.nxv16i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i32>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv2i8.nxv16i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg7_nxv2i8_nxv16i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv2i8_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg7ei32.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv2i8.nxv16i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv2i8_nxv16i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv2i8_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg7ei32.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv2i8.nxv16i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv2i8.nxv2i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i16>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv2i8.nxv2i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg7_nxv2i8_nxv2i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv2i8_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv2i8.nxv2i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv2i8_nxv2i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv2i8_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv2i8.nxv2i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv2i8.nxv2i64(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i64>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv2i8.nxv2i64(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg7_nxv2i8_nxv2i64(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv2i8_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg7ei64.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv2i8.nxv2i64(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv2i8_nxv2i64(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv2i8_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg7ei64.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv2i8.nxv2i64(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv2i8.nxv16i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i16>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv2i8.nxv16i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg8_nxv2i8_nxv16i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv2i8_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv2i8.nxv16i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv2i8_nxv16i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv2i8_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv2i8.nxv16i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv2i8.nxv32i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 32 x i16>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv2i8.nxv32i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 32 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg8_nxv2i8_nxv32i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv2i8_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vmv1r.v v23, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv2i8.nxv32i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv2i8_nxv32i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv2i8_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vmv1r.v v23, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv2i8.nxv32i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv2i8.nxv4i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i32>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv2i8.nxv4i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg8_nxv2i8_nxv4i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv2i8_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg8ei32.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv2i8.nxv4i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv2i8_nxv4i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv2i8_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg8ei32.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv2i8.nxv4i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv2i8.nxv16i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i8>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv2i8.nxv16i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg8_nxv2i8_nxv16i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv2i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv2i8.nxv16i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv2i8_nxv16i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv2i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv2i8.nxv16i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv2i8.nxv1i64(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv2i8.nxv1i64(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i64>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg8_nxv2i8_nxv1i64(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv2i8_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg8ei64.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv2i8.nxv1i64(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv2i8_nxv1i64(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv2i8_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg8ei64.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv2i8.nxv1i64(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv2i8.nxv1i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv2i8.nxv1i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg8_nxv2i8_nxv1i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv2i8_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg8ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv2i8.nxv1i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv2i8_nxv1i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv2i8_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg8ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv2i8.nxv1i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv2i8.nxv8i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i16>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv2i8.nxv8i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg8_nxv2i8_nxv8i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv2i8_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv2i8.nxv8i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv2i8_nxv8i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv2i8_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv2i8.nxv8i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv2i8.nxv4i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i8>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv2i8.nxv4i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg8_nxv2i8_nxv4i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv2i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv2i8.nxv4i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv2i8_nxv4i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv2i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv2i8.nxv4i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv2i8.nxv1i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv2i8.nxv1i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg8_nxv2i8_nxv1i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv2i8_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv2i8.nxv1i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv2i8_nxv1i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv2i8_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv2i8.nxv1i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv2i8.nxv2i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i32>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv2i8.nxv2i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg8_nxv2i8_nxv2i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv2i8_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg8ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv2i8.nxv2i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv2i8_nxv2i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv2i8_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg8ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv2i8.nxv2i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv2i8.nxv8i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i8>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv2i8.nxv8i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg8_nxv2i8_nxv8i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv2i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv2i8.nxv8i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv2i8_nxv8i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv2i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv2i8.nxv8i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv2i8.nxv4i64(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i64>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv2i8.nxv4i64(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i64>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg8_nxv2i8_nxv4i64(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv2i8_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg8ei64.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv2i8.nxv4i64(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv2i8_nxv4i64(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv2i8_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg8ei64.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv2i8.nxv4i64(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv2i8.nxv64i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 64 x i8>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv2i8.nxv64i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 64 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg8_nxv2i8_nxv64i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv2i8_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vmv1r.v v23, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv2i8.nxv64i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv2i8_nxv64i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv2i8_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vmv1r.v v23, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv2i8.nxv64i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv2i8.nxv4i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i16>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv2i8.nxv4i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 4 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg8_nxv2i8_nxv4i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv2i8_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv2i8.nxv4i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv2i8_nxv4i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv2i8_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv2i8.nxv4i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv2i8.nxv8i64(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i64>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv2i8.nxv8i64(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i64>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg8_nxv2i8_nxv8i64(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv2i8_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vmv1r.v v23, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg8ei64.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv2i8.nxv8i64(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv2i8_nxv8i64(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv2i8_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vmv1r.v v23, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg8ei64.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv2i8.nxv8i64(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv2i8.nxv1i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv2i8.nxv1i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 1 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg8_nxv2i8_nxv1i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv2i8_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv2i8.nxv1i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv2i8_nxv1i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv2i8_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv2i8.nxv1i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv2i8.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i8>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv2i8.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg8_nxv2i8_nxv2i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv2i8_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv2i8.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv2i8_nxv2i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv2i8_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv2i8.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv2i8.nxv8i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i32>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv2i8.nxv8i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 8 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg8_nxv2i8_nxv8i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv2i8_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg8ei32.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv2i8.nxv8i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv2i8_nxv8i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv2i8_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg8ei32.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv2i8.nxv8i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv2i8.nxv32i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 32 x i8>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv2i8.nxv32i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 32 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg8_nxv2i8_nxv32i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv2i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv2i8.nxv32i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv2i8_nxv32i8(<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv2i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv2i8.nxv32i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv2i8.nxv16i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i32>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv2i8.nxv16i32(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 16 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg8_nxv2i8_nxv16i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv2i8_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vmv1r.v v23, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg8ei32.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv2i8.nxv16i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv2i8_nxv16i32(<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv2i8_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vmv1r.v v23, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg8ei32.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv2i8.nxv16i32(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv2i8.nxv2i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i16>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv2i8.nxv2i16(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg8_nxv2i8_nxv2i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv2i8_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv2i8.nxv2i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv2i8_nxv2i16(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv2i8_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv2i8.nxv2i16(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv2i8.nxv2i64(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i64>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv2i8.nxv2i64(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg8_nxv2i8_nxv2i64(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv2i8_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg8ei64.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv2i8.nxv2i64(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv2i8_nxv2i64(<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv2i8_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vsxseg8ei64.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv2i8.nxv2i64(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv8i32.nxv16i16(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 16 x i16>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv8i32.nxv16i16(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 16 x i16>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg2_nxv8i32_nxv16i16(<vscale x 8 x i32> %val, i32* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv8i32_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv4r.v v28, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v28
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv8i32.nxv16i16(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 16 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv8i32_nxv16i16(<vscale x 8 x i32> %val, i32* %base, <vscale x 16 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv8i32_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv4r.v v28, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v28, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv8i32.nxv16i16(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 16 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv8i32.nxv32i16(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 32 x i16>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv8i32.nxv32i16(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 32 x i16>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg2_nxv8i32_nxv32i16(<vscale x 8 x i32> %val, i32* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv8i32_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv8i32.nxv32i16(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 32 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv8i32_nxv32i16(<vscale x 8 x i32> %val, i32* %base, <vscale x 32 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv8i32_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv8i32.nxv32i16(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 32 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv8i32.nxv4i32(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 4 x i32>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv8i32.nxv4i32(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 4 x i32>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg2_nxv8i32_nxv4i32(<vscale x 8 x i32> %val, i32* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv8i32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv2r.v v26, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v26
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv8i32.nxv4i32(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 4 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv8i32_nxv4i32(<vscale x 8 x i32> %val, i32* %base, <vscale x 4 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv8i32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv2r.v v26, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v26, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv8i32.nxv4i32(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 4 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv8i32.nxv16i8(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 16 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv8i32.nxv16i8(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 16 x i8>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg2_nxv8i32_nxv16i8(<vscale x 8 x i32> %val, i32* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv8i32_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv2r.v v26, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v26
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv8i32.nxv16i8(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 16 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv8i32_nxv16i8(<vscale x 8 x i32> %val, i32* %base, <vscale x 16 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv8i32_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv2r.v v26, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v26, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv8i32.nxv16i8(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 16 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv8i32.nxv1i64(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv8i32.nxv1i64(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 1 x i64>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg2_nxv8i32_nxv1i64(<vscale x 8 x i32> %val, i32* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv8i32_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv1r.v v25, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv8i32.nxv1i64(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 1 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv8i32_nxv1i64(<vscale x 8 x i32> %val, i32* %base, <vscale x 1 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv8i32_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv1r.v v25, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv8i32.nxv1i64(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 1 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv8i32.nxv1i32(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv8i32.nxv1i32(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 1 x i32>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg2_nxv8i32_nxv1i32(<vscale x 8 x i32> %val, i32* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv8i32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv1r.v v25, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv8i32.nxv1i32(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 1 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv8i32_nxv1i32(<vscale x 8 x i32> %val, i32* %base, <vscale x 1 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv8i32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv1r.v v25, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv8i32.nxv1i32(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 1 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv8i32.nxv8i16(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 8 x i16>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv8i32.nxv8i16(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 8 x i16>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg2_nxv8i32_nxv8i16(<vscale x 8 x i32> %val, i32* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv8i32_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv2r.v v26, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v26
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv8i32.nxv8i16(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 8 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv8i32_nxv8i16(<vscale x 8 x i32> %val, i32* %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv8i32_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv2r.v v26, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v26, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv8i32.nxv8i16(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv8i32.nxv4i8(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 4 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv8i32.nxv4i8(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 4 x i8>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg2_nxv8i32_nxv4i8(<vscale x 8 x i32> %val, i32* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv8i32_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv1r.v v25, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv8i32.nxv4i8(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 4 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv8i32_nxv4i8(<vscale x 8 x i32> %val, i32* %base, <vscale x 4 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv8i32_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv1r.v v25, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv8i32.nxv4i8(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 4 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv8i32.nxv1i16(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv8i32.nxv1i16(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 1 x i16>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg2_nxv8i32_nxv1i16(<vscale x 8 x i32> %val, i32* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv8i32_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv1r.v v25, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv8i32.nxv1i16(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 1 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv8i32_nxv1i16(<vscale x 8 x i32> %val, i32* %base, <vscale x 1 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv8i32_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv1r.v v25, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv8i32.nxv1i16(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 1 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv8i32.nxv2i32(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 2 x i32>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv8i32.nxv2i32(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 2 x i32>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg2_nxv8i32_nxv2i32(<vscale x 8 x i32> %val, i32* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv8i32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv1r.v v25, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv8i32.nxv2i32(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 2 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv8i32_nxv2i32(<vscale x 8 x i32> %val, i32* %base, <vscale x 2 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv8i32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv1r.v v25, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv8i32.nxv2i32(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 2 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv8i32.nxv8i8(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 8 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv8i32.nxv8i8(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 8 x i8>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg2_nxv8i32_nxv8i8(<vscale x 8 x i32> %val, i32* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv8i32_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv1r.v v25, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv8i32.nxv8i8(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 8 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv8i32_nxv8i8(<vscale x 8 x i32> %val, i32* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv8i32_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv1r.v v25, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv8i32.nxv8i8(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv8i32.nxv4i64(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 4 x i64>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv8i32.nxv4i64(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 4 x i64>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg2_nxv8i32_nxv4i64(<vscale x 8 x i32> %val, i32* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv8i32_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv4r.v v28, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v28
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv8i32.nxv4i64(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 4 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv8i32_nxv4i64(<vscale x 8 x i32> %val, i32* %base, <vscale x 4 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv8i32_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv4r.v v28, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v28, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv8i32.nxv4i64(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 4 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv8i32.nxv64i8(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 64 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv8i32.nxv64i8(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 64 x i8>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg2_nxv8i32_nxv64i8(<vscale x 8 x i32> %val, i32* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv8i32_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv8i32.nxv64i8(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 64 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv8i32_nxv64i8(<vscale x 8 x i32> %val, i32* %base, <vscale x 64 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv8i32_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv8i32.nxv64i8(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 64 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv8i32.nxv4i16(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 4 x i16>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv8i32.nxv4i16(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 4 x i16>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg2_nxv8i32_nxv4i16(<vscale x 8 x i32> %val, i32* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv8i32_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv1r.v v25, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv8i32.nxv4i16(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 4 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv8i32_nxv4i16(<vscale x 8 x i32> %val, i32* %base, <vscale x 4 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv8i32_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv1r.v v25, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv8i32.nxv4i16(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 4 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv8i32.nxv8i64(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 8 x i64>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv8i32.nxv8i64(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 8 x i64>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg2_nxv8i32_nxv8i64(<vscale x 8 x i32> %val, i32* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv8i32_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv8i32.nxv8i64(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 8 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv8i32_nxv8i64(<vscale x 8 x i32> %val, i32* %base, <vscale x 8 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv8i32_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv8i32.nxv8i64(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 8 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv8i32.nxv1i8(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv8i32.nxv1i8(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 1 x i8>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg2_nxv8i32_nxv1i8(<vscale x 8 x i32> %val, i32* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv8i32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv1r.v v25, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv8i32.nxv1i8(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 1 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv8i32_nxv1i8(<vscale x 8 x i32> %val, i32* %base, <vscale x 1 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv8i32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv1r.v v25, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv8i32.nxv1i8(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 1 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv8i32.nxv2i8(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 2 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv8i32.nxv2i8(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 2 x i8>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg2_nxv8i32_nxv2i8(<vscale x 8 x i32> %val, i32* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv8i32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv1r.v v25, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv8i32.nxv2i8(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 2 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv8i32_nxv2i8(<vscale x 8 x i32> %val, i32* %base, <vscale x 2 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv8i32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv1r.v v25, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv8i32.nxv2i8(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 2 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv8i32.nxv8i32(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 8 x i32>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv8i32.nxv8i32(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 8 x i32>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg2_nxv8i32_nxv8i32(<vscale x 8 x i32> %val, i32* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv8i32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv4r.v v28, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v28
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv8i32.nxv8i32(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 8 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv8i32_nxv8i32(<vscale x 8 x i32> %val, i32* %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv8i32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv4r.v v28, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v28, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv8i32.nxv8i32(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv8i32.nxv32i8(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 32 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv8i32.nxv32i8(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 32 x i8>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg2_nxv8i32_nxv32i8(<vscale x 8 x i32> %val, i32* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv8i32_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv4r.v v28, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v28
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv8i32.nxv32i8(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 32 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv8i32_nxv32i8(<vscale x 8 x i32> %val, i32* %base, <vscale x 32 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv8i32_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv4r.v v28, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v28, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv8i32.nxv32i8(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 32 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv8i32.nxv16i32(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 16 x i32>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv8i32.nxv16i32(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 16 x i32>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg2_nxv8i32_nxv16i32(<vscale x 8 x i32> %val, i32* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv8i32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv8i32.nxv16i32(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 16 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv8i32_nxv16i32(<vscale x 8 x i32> %val, i32* %base, <vscale x 16 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv8i32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv8i32.nxv16i32(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 16 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv8i32.nxv2i16(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 2 x i16>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv8i32.nxv2i16(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 2 x i16>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg2_nxv8i32_nxv2i16(<vscale x 8 x i32> %val, i32* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv8i32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv1r.v v25, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv8i32.nxv2i16(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 2 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv8i32_nxv2i16(<vscale x 8 x i32> %val, i32* %base, <vscale x 2 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv8i32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv1r.v v25, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv8i32.nxv2i16(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 2 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv8i32.nxv2i64(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 2 x i64>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv8i32.nxv2i64(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 2 x i64>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg2_nxv8i32_nxv2i64(<vscale x 8 x i32> %val, i32* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv8i32_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv2r.v v26, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v26
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv8i32.nxv2i64(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 2 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv8i32_nxv2i64(<vscale x 8 x i32> %val, i32* %base, <vscale x 2 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv8i32_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv2r.v v26, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v26, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv8i32.nxv2i64(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 2 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv32i8.nxv16i16(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 16 x i16>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv32i8.nxv16i16(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 16 x i16>, <vscale x 32 x i1>, i64)
+
+define void @test_vsxseg2_nxv32i8_nxv16i16(<vscale x 32 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv32i8_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv4r.v v28, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v28
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv32i8.nxv16i16(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, <vscale x 16 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv32i8_nxv16i16(<vscale x 32 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 32 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv32i8_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv4r.v v28, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v28, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv32i8.nxv16i16(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, <vscale x 16 x i16> %index, <vscale x 32 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv32i8.nxv32i16(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 32 x i16>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv32i8.nxv32i16(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 32 x i16>, <vscale x 32 x i1>, i64)
+
+define void @test_vsxseg2_nxv32i8_nxv32i16(<vscale x 32 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv32i8_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv32i8.nxv32i16(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, <vscale x 32 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv32i8_nxv32i16(<vscale x 32 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 32 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv32i8_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv32i8.nxv32i16(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, <vscale x 32 x i16> %index, <vscale x 32 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv32i8.nxv4i32(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 4 x i32>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv32i8.nxv4i32(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 4 x i32>, <vscale x 32 x i1>, i64)
+
+define void @test_vsxseg2_nxv32i8_nxv4i32(<vscale x 32 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv32i8_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv2r.v v26, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v26
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv32i8.nxv4i32(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, <vscale x 4 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv32i8_nxv4i32(<vscale x 32 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 32 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv32i8_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv2r.v v26, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v26, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv32i8.nxv4i32(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, <vscale x 4 x i32> %index, <vscale x 32 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv32i8.nxv16i8(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 16 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv32i8.nxv16i8(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 16 x i8>, <vscale x 32 x i1>, i64)
+
+define void @test_vsxseg2_nxv32i8_nxv16i8(<vscale x 32 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv32i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv2r.v v26, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v26
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv32i8.nxv16i8(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, <vscale x 16 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv32i8_nxv16i8(<vscale x 32 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 32 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv32i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv2r.v v26, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v26, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv32i8.nxv16i8(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, <vscale x 16 x i8> %index, <vscale x 32 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv32i8.nxv1i64(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv32i8.nxv1i64(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 1 x i64>, <vscale x 32 x i1>, i64)
+
+define void @test_vsxseg2_nxv32i8_nxv1i64(<vscale x 32 x i8> %val, i8* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv32i8_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv1r.v v25, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv32i8.nxv1i64(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, <vscale x 1 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv32i8_nxv1i64(<vscale x 32 x i8> %val, i8* %base, <vscale x 1 x i64> %index, <vscale x 32 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv32i8_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv1r.v v25, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv32i8.nxv1i64(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, <vscale x 1 x i64> %index, <vscale x 32 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv32i8.nxv1i32(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv32i8.nxv1i32(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 1 x i32>, <vscale x 32 x i1>, i64)
+
+define void @test_vsxseg2_nxv32i8_nxv1i32(<vscale x 32 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv32i8_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv1r.v v25, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv32i8.nxv1i32(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, <vscale x 1 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv32i8_nxv1i32(<vscale x 32 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 32 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv32i8_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv1r.v v25, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv32i8.nxv1i32(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, <vscale x 1 x i32> %index, <vscale x 32 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv32i8.nxv8i16(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 8 x i16>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv32i8.nxv8i16(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 8 x i16>, <vscale x 32 x i1>, i64)
+
+define void @test_vsxseg2_nxv32i8_nxv8i16(<vscale x 32 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv32i8_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv2r.v v26, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v26
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv32i8.nxv8i16(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, <vscale x 8 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv32i8_nxv8i16(<vscale x 32 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 32 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv32i8_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv2r.v v26, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v26, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv32i8.nxv8i16(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, <vscale x 8 x i16> %index, <vscale x 32 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv32i8.nxv4i8(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 4 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv32i8.nxv4i8(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 4 x i8>, <vscale x 32 x i1>, i64)
+
+define void @test_vsxseg2_nxv32i8_nxv4i8(<vscale x 32 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv32i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv1r.v v25, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv32i8.nxv4i8(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, <vscale x 4 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv32i8_nxv4i8(<vscale x 32 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 32 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv32i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv1r.v v25, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv32i8.nxv4i8(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, <vscale x 4 x i8> %index, <vscale x 32 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv32i8.nxv1i16(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv32i8.nxv1i16(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 1 x i16>, <vscale x 32 x i1>, i64)
+
+define void @test_vsxseg2_nxv32i8_nxv1i16(<vscale x 32 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv32i8_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv1r.v v25, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv32i8.nxv1i16(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, <vscale x 1 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv32i8_nxv1i16(<vscale x 32 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 32 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv32i8_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv1r.v v25, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv32i8.nxv1i16(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, <vscale x 1 x i16> %index, <vscale x 32 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv32i8.nxv2i32(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 2 x i32>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv32i8.nxv2i32(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 2 x i32>, <vscale x 32 x i1>, i64)
+
+define void @test_vsxseg2_nxv32i8_nxv2i32(<vscale x 32 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv32i8_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv1r.v v25, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv32i8.nxv2i32(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, <vscale x 2 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv32i8_nxv2i32(<vscale x 32 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 32 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv32i8_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv1r.v v25, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv32i8.nxv2i32(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, <vscale x 2 x i32> %index, <vscale x 32 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv32i8.nxv8i8(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 8 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv32i8.nxv8i8(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 8 x i8>, <vscale x 32 x i1>, i64)
+
+define void @test_vsxseg2_nxv32i8_nxv8i8(<vscale x 32 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv32i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv1r.v v25, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv32i8.nxv8i8(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, <vscale x 8 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv32i8_nxv8i8(<vscale x 32 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 32 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv32i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv1r.v v25, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv32i8.nxv8i8(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, <vscale x 8 x i8> %index, <vscale x 32 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv32i8.nxv4i64(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 4 x i64>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv32i8.nxv4i64(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 4 x i64>, <vscale x 32 x i1>, i64)
+
+define void @test_vsxseg2_nxv32i8_nxv4i64(<vscale x 32 x i8> %val, i8* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv32i8_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv4r.v v28, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v28
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv32i8.nxv4i64(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, <vscale x 4 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv32i8_nxv4i64(<vscale x 32 x i8> %val, i8* %base, <vscale x 4 x i64> %index, <vscale x 32 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv32i8_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv4r.v v28, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v28, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv32i8.nxv4i64(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, <vscale x 4 x i64> %index, <vscale x 32 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv32i8.nxv64i8(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 64 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv32i8.nxv64i8(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 64 x i8>, <vscale x 32 x i1>, i64)
+
+define void @test_vsxseg2_nxv32i8_nxv64i8(<vscale x 32 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv32i8_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv32i8.nxv64i8(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, <vscale x 64 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv32i8_nxv64i8(<vscale x 32 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 32 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv32i8_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv32i8.nxv64i8(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, <vscale x 64 x i8> %index, <vscale x 32 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv32i8.nxv4i16(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 4 x i16>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv32i8.nxv4i16(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 4 x i16>, <vscale x 32 x i1>, i64)
+
+define void @test_vsxseg2_nxv32i8_nxv4i16(<vscale x 32 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv32i8_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv1r.v v25, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv32i8.nxv4i16(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, <vscale x 4 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv32i8_nxv4i16(<vscale x 32 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 32 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv32i8_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv1r.v v25, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv32i8.nxv4i16(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, <vscale x 4 x i16> %index, <vscale x 32 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv32i8.nxv8i64(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 8 x i64>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv32i8.nxv8i64(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 8 x i64>, <vscale x 32 x i1>, i64)
+
+define void @test_vsxseg2_nxv32i8_nxv8i64(<vscale x 32 x i8> %val, i8* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv32i8_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv32i8.nxv8i64(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, <vscale x 8 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv32i8_nxv8i64(<vscale x 32 x i8> %val, i8* %base, <vscale x 8 x i64> %index, <vscale x 32 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv32i8_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv32i8.nxv8i64(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, <vscale x 8 x i64> %index, <vscale x 32 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv32i8.nxv1i8(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv32i8.nxv1i8(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 1 x i8>, <vscale x 32 x i1>, i64)
+
+define void @test_vsxseg2_nxv32i8_nxv1i8(<vscale x 32 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv32i8_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv1r.v v25, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv32i8.nxv1i8(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, <vscale x 1 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv32i8_nxv1i8(<vscale x 32 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 32 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv32i8_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv1r.v v25, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv32i8.nxv1i8(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, <vscale x 1 x i8> %index, <vscale x 32 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv32i8.nxv2i8(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 2 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv32i8.nxv2i8(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 2 x i8>, <vscale x 32 x i1>, i64)
+
+define void @test_vsxseg2_nxv32i8_nxv2i8(<vscale x 32 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv32i8_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv1r.v v25, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv32i8.nxv2i8(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, <vscale x 2 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv32i8_nxv2i8(<vscale x 32 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 32 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv32i8_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv1r.v v25, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv32i8.nxv2i8(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, <vscale x 2 x i8> %index, <vscale x 32 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv32i8.nxv8i32(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 8 x i32>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv32i8.nxv8i32(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 8 x i32>, <vscale x 32 x i1>, i64)
+
+define void @test_vsxseg2_nxv32i8_nxv8i32(<vscale x 32 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv32i8_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv4r.v v28, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v28
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv32i8.nxv8i32(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, <vscale x 8 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv32i8_nxv8i32(<vscale x 32 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 32 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv32i8_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv4r.v v28, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v28, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv32i8.nxv8i32(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, <vscale x 8 x i32> %index, <vscale x 32 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv32i8.nxv32i8(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 32 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv32i8.nxv32i8(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 32 x i8>, <vscale x 32 x i1>, i64)
+
+define void @test_vsxseg2_nxv32i8_nxv32i8(<vscale x 32 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv32i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv4r.v v28, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v28
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv32i8.nxv32i8(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, <vscale x 32 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv32i8_nxv32i8(<vscale x 32 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 32 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv32i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv4r.v v28, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v28, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv32i8.nxv32i8(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, <vscale x 32 x i8> %index, <vscale x 32 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv32i8.nxv16i32(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 16 x i32>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv32i8.nxv16i32(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 16 x i32>, <vscale x 32 x i1>, i64)
+
+define void @test_vsxseg2_nxv32i8_nxv16i32(<vscale x 32 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv32i8_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv32i8.nxv16i32(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, <vscale x 16 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv32i8_nxv16i32(<vscale x 32 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 32 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv32i8_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e8,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv32i8.nxv16i32(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, <vscale x 16 x i32> %index, <vscale x 32 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv32i8.nxv2i16(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 2 x i16>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv32i8.nxv2i16(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 2 x i16>, <vscale x 32 x i1>, i64)
+
+define void @test_vsxseg2_nxv32i8_nxv2i16(<vscale x 32 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv32i8_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv1r.v v25, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv32i8.nxv2i16(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, <vscale x 2 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv32i8_nxv2i16(<vscale x 32 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 32 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv32i8_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv1r.v v25, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv32i8.nxv2i16(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, <vscale x 2 x i16> %index, <vscale x 32 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv32i8.nxv2i64(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 2 x i64>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv32i8.nxv2i64(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 2 x i64>, <vscale x 32 x i1>, i64)
+
+define void @test_vsxseg2_nxv32i8_nxv2i64(<vscale x 32 x i8> %val, i8* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv32i8_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv2r.v v26, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v26
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv32i8.nxv2i64(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, <vscale x 2 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv32i8_nxv2i64(<vscale x 32 x i8> %val, i8* %base, <vscale x 2 x i64> %index, <vscale x 32 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv32i8_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv2r.v v26, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e8,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v26, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv32i8.nxv2i64(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, <vscale x 2 x i64> %index, <vscale x 32 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv2i16.nxv16i16(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i16>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv2i16.nxv16i16(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg2_nxv2i16_nxv16i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv2i16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv2i16.nxv16i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv2i16_nxv16i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv2i16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv2i16.nxv16i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv2i16.nxv32i16(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 32 x i16>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv2i16.nxv32i16(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 32 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg2_nxv2i16_nxv32i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv2i16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv2i16.nxv32i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv2i16_nxv32i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv2i16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv2i16.nxv32i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv2i16.nxv4i32(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i32>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv2i16.nxv4i32(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg2_nxv2i16_nxv4i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv2i16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv2i16.nxv4i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv2i16_nxv4i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv2i16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv2i16.nxv4i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv2i16.nxv16i8(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv2i16.nxv16i8(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg2_nxv2i16_nxv16i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv2i16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv2i16.nxv16i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv2i16_nxv16i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv2i16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv2i16.nxv16i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv2i16.nxv1i64(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv2i16.nxv1i64(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i64>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg2_nxv2i16_nxv1i64(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv2i16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv2i16.nxv1i64(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv2i16_nxv1i64(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv2i16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv2i16.nxv1i64(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv2i16.nxv1i32(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv2i16.nxv1i32(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg2_nxv2i16_nxv1i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv2i16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv2i16.nxv1i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv2i16_nxv1i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv2i16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv2i16.nxv1i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv2i16.nxv8i16(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i16>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv2i16.nxv8i16(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg2_nxv2i16_nxv8i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv2i16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv2i16.nxv8i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv2i16_nxv8i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv2i16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv2i16.nxv8i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv2i16.nxv4i8(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv2i16.nxv4i8(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg2_nxv2i16_nxv4i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv2i16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv2i16.nxv4i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv2i16_nxv4i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv2i16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv2i16.nxv4i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv2i16.nxv1i16(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv2i16.nxv1i16(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg2_nxv2i16_nxv1i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv2i16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv2i16.nxv1i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv2i16_nxv1i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv2i16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv2i16.nxv1i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv2i16.nxv2i32(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i32>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv2i16.nxv2i32(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg2_nxv2i16_nxv2i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv2i16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv2i16.nxv2i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv2i16_nxv2i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv2i16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv2i16.nxv2i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv2i16.nxv8i8(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv2i16.nxv8i8(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg2_nxv2i16_nxv8i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv2i16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv2i16.nxv8i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv2i16_nxv8i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv2i16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv2i16.nxv8i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv2i16.nxv4i64(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i64>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv2i16.nxv4i64(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i64>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg2_nxv2i16_nxv4i64(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv2i16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv2i16.nxv4i64(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv2i16_nxv4i64(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv2i16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv2i16.nxv4i64(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv2i16.nxv64i8(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 64 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv2i16.nxv64i8(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 64 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg2_nxv2i16_nxv64i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv2i16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv2i16.nxv64i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv2i16_nxv64i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv2i16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv2i16.nxv64i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv2i16.nxv4i16(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i16>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv2i16.nxv4i16(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg2_nxv2i16_nxv4i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv2i16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv2i16.nxv4i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv2i16_nxv4i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv2i16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv2i16.nxv4i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv2i16.nxv8i64(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i64>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv2i16.nxv8i64(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i64>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg2_nxv2i16_nxv8i64(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv2i16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv2i16.nxv8i64(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv2i16_nxv8i64(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv2i16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv2i16.nxv8i64(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv2i16.nxv1i8(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv2i16.nxv1i8(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg2_nxv2i16_nxv1i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv2i16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv2i16.nxv1i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv2i16_nxv1i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv2i16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv2i16.nxv1i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv2i16.nxv2i8(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv2i16.nxv2i8(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg2_nxv2i16_nxv2i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv2i16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv2i16.nxv2i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv2i16_nxv2i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv2i16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv2i16.nxv2i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv2i16.nxv8i32(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i32>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv2i16.nxv8i32(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg2_nxv2i16_nxv8i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv2i16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv2i16.nxv8i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv2i16_nxv8i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv2i16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv2i16.nxv8i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv2i16.nxv32i8(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 32 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv2i16.nxv32i8(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 32 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg2_nxv2i16_nxv32i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv2i16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv2i16.nxv32i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv2i16_nxv32i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv2i16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv2i16.nxv32i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv2i16.nxv16i32(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i32>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv2i16.nxv16i32(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg2_nxv2i16_nxv16i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv2i16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv2i16.nxv16i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv2i16_nxv16i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv2i16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv2i16.nxv16i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv2i16.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i16>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv2i16.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg2_nxv2i16_nxv2i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv2i16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv2i16.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv2i16_nxv2i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv2i16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv2i16.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv2i16.nxv2i64(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i64>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv2i16.nxv2i64(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg2_nxv2i16_nxv2i64(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv2i16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv2i16.nxv2i64(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv2i16_nxv2i64(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv2i16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv2i16.nxv2i64(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv2i16.nxv16i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i16>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv2i16.nxv16i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg3_nxv2i16_nxv16i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv2i16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv2i16.nxv16i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv2i16_nxv16i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv2i16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv2i16.nxv16i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv2i16.nxv32i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 32 x i16>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv2i16.nxv32i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 32 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg3_nxv2i16_nxv32i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv2i16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv2i16.nxv32i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv2i16_nxv32i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv2i16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv2i16.nxv32i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv2i16.nxv4i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i32>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv2i16.nxv4i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg3_nxv2i16_nxv4i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv2i16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv2i16.nxv4i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv2i16_nxv4i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv2i16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv2i16.nxv4i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv2i16.nxv16i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i8>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv2i16.nxv16i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg3_nxv2i16_nxv16i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv2i16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv2i16.nxv16i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv2i16_nxv16i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv2i16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv2i16.nxv16i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv2i16.nxv1i64(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv2i16.nxv1i64(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i64>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg3_nxv2i16_nxv1i64(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv2i16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei64.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv2i16.nxv1i64(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv2i16_nxv1i64(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv2i16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei64.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv2i16.nxv1i64(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv2i16.nxv1i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv2i16.nxv1i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg3_nxv2i16_nxv1i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv2i16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv2i16.nxv1i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv2i16_nxv1i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv2i16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv2i16.nxv1i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv2i16.nxv8i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i16>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv2i16.nxv8i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg3_nxv2i16_nxv8i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv2i16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv2i16.nxv8i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv2i16_nxv8i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv2i16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv2i16.nxv8i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv2i16.nxv4i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i8>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv2i16.nxv4i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg3_nxv2i16_nxv4i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv2i16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv2i16.nxv4i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv2i16_nxv4i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv2i16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv2i16.nxv4i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv2i16.nxv1i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv2i16.nxv1i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg3_nxv2i16_nxv1i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv2i16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv2i16.nxv1i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv2i16_nxv1i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv2i16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv2i16.nxv1i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv2i16.nxv2i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i32>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv2i16.nxv2i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg3_nxv2i16_nxv2i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv2i16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv2i16.nxv2i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv2i16_nxv2i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv2i16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv2i16.nxv2i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv2i16.nxv8i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i8>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv2i16.nxv8i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg3_nxv2i16_nxv8i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv2i16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv2i16.nxv8i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv2i16_nxv8i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv2i16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv2i16.nxv8i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv2i16.nxv4i64(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i64>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv2i16.nxv4i64(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i64>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg3_nxv2i16_nxv4i64(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv2i16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei64.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv2i16.nxv4i64(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv2i16_nxv4i64(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv2i16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei64.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv2i16.nxv4i64(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv2i16.nxv64i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 64 x i8>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv2i16.nxv64i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 64 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg3_nxv2i16_nxv64i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv2i16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv2i16.nxv64i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv2i16_nxv64i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv2i16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv2i16.nxv64i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv2i16.nxv4i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i16>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv2i16.nxv4i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg3_nxv2i16_nxv4i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv2i16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv2i16.nxv4i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv2i16_nxv4i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv2i16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv2i16.nxv4i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv2i16.nxv8i64(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i64>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv2i16.nxv8i64(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i64>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg3_nxv2i16_nxv8i64(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv2i16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei64.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv2i16.nxv8i64(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv2i16_nxv8i64(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv2i16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei64.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv2i16.nxv8i64(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv2i16.nxv1i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv2i16.nxv1i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg3_nxv2i16_nxv1i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv2i16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv2i16.nxv1i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv2i16_nxv1i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv2i16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv2i16.nxv1i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv2i16.nxv2i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i8>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv2i16.nxv2i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg3_nxv2i16_nxv2i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv2i16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv2i16.nxv2i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv2i16_nxv2i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv2i16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv2i16.nxv2i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv2i16.nxv8i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i32>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv2i16.nxv8i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg3_nxv2i16_nxv8i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv2i16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv2i16.nxv8i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv2i16_nxv8i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv2i16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv2i16.nxv8i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv2i16.nxv32i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 32 x i8>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv2i16.nxv32i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 32 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg3_nxv2i16_nxv32i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv2i16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv2i16.nxv32i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv2i16_nxv32i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv2i16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv2i16.nxv32i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv2i16.nxv16i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i32>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv2i16.nxv16i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg3_nxv2i16_nxv16i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv2i16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv2i16.nxv16i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv2i16_nxv16i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv2i16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv2i16.nxv16i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv2i16.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i16>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv2i16.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg3_nxv2i16_nxv2i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv2i16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv2i16.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv2i16_nxv2i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv2i16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv2i16.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv2i16.nxv2i64(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i64>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv2i16.nxv2i64(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg3_nxv2i16_nxv2i64(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv2i16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei64.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv2i16.nxv2i64(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv2i16_nxv2i64(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv2i16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei64.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv2i16.nxv2i64(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv2i16.nxv16i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i16>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv2i16.nxv16i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg4_nxv2i16_nxv16i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv2i16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv2i16.nxv16i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv2i16_nxv16i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv2i16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv2i16.nxv16i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv2i16.nxv32i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 32 x i16>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv2i16.nxv32i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 32 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg4_nxv2i16_nxv32i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv2i16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv2i16.nxv32i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv2i16_nxv32i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv2i16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv2i16.nxv32i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv2i16.nxv4i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i32>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv2i16.nxv4i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg4_nxv2i16_nxv4i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv2i16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv2i16.nxv4i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv2i16_nxv4i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv2i16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv2i16.nxv4i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv2i16.nxv16i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i8>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv2i16.nxv16i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg4_nxv2i16_nxv16i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv2i16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv2i16.nxv16i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv2i16_nxv16i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv2i16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv2i16.nxv16i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv2i16.nxv1i64(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv2i16.nxv1i64(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i64>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg4_nxv2i16_nxv1i64(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv2i16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei64.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv2i16.nxv1i64(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv2i16_nxv1i64(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv2i16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei64.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv2i16.nxv1i64(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv2i16.nxv1i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv2i16.nxv1i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg4_nxv2i16_nxv1i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv2i16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv2i16.nxv1i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv2i16_nxv1i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv2i16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv2i16.nxv1i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv2i16.nxv8i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i16>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv2i16.nxv8i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg4_nxv2i16_nxv8i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv2i16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv2i16.nxv8i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv2i16_nxv8i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv2i16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv2i16.nxv8i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv2i16.nxv4i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i8>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv2i16.nxv4i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg4_nxv2i16_nxv4i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv2i16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv2i16.nxv4i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv2i16_nxv4i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv2i16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv2i16.nxv4i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv2i16.nxv1i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv2i16.nxv1i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg4_nxv2i16_nxv1i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv2i16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv2i16.nxv1i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv2i16_nxv1i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv2i16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv2i16.nxv1i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv2i16.nxv2i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i32>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv2i16.nxv2i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg4_nxv2i16_nxv2i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv2i16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv2i16.nxv2i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv2i16_nxv2i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv2i16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv2i16.nxv2i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv2i16.nxv8i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i8>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv2i16.nxv8i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg4_nxv2i16_nxv8i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv2i16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv2i16.nxv8i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv2i16_nxv8i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv2i16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv2i16.nxv8i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv2i16.nxv4i64(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i64>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv2i16.nxv4i64(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i64>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg4_nxv2i16_nxv4i64(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv2i16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei64.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv2i16.nxv4i64(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv2i16_nxv4i64(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv2i16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei64.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv2i16.nxv4i64(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv2i16.nxv64i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 64 x i8>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv2i16.nxv64i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 64 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg4_nxv2i16_nxv64i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv2i16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv2i16.nxv64i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv2i16_nxv64i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv2i16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv2i16.nxv64i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv2i16.nxv4i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i16>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv2i16.nxv4i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg4_nxv2i16_nxv4i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv2i16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv2i16.nxv4i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv2i16_nxv4i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv2i16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv2i16.nxv4i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv2i16.nxv8i64(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i64>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv2i16.nxv8i64(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i64>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg4_nxv2i16_nxv8i64(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv2i16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei64.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv2i16.nxv8i64(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv2i16_nxv8i64(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv2i16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei64.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv2i16.nxv8i64(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv2i16.nxv1i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv2i16.nxv1i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg4_nxv2i16_nxv1i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv2i16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv2i16.nxv1i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv2i16_nxv1i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv2i16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv2i16.nxv1i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv2i16.nxv2i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i8>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv2i16.nxv2i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg4_nxv2i16_nxv2i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv2i16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv2i16.nxv2i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv2i16_nxv2i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv2i16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv2i16.nxv2i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv2i16.nxv8i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i32>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv2i16.nxv8i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg4_nxv2i16_nxv8i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv2i16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv2i16.nxv8i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv2i16_nxv8i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv2i16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv2i16.nxv8i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv2i16.nxv32i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 32 x i8>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv2i16.nxv32i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 32 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg4_nxv2i16_nxv32i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv2i16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv2i16.nxv32i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv2i16_nxv32i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv2i16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv2i16.nxv32i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv2i16.nxv16i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i32>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv2i16.nxv16i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg4_nxv2i16_nxv16i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv2i16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv2i16.nxv16i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv2i16_nxv16i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv2i16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv2i16.nxv16i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv2i16.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i16>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv2i16.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg4_nxv2i16_nxv2i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv2i16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv2i16.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv2i16_nxv2i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv2i16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv2i16.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv2i16.nxv2i64(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i64>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv2i16.nxv2i64(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg4_nxv2i16_nxv2i64(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv2i16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei64.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv2i16.nxv2i64(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv2i16_nxv2i64(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv2i16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei64.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv2i16.nxv2i64(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv2i16.nxv16i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i16>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv2i16.nxv16i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg5_nxv2i16_nxv16i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv2i16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv2i16.nxv16i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv2i16_nxv16i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv2i16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv2i16.nxv16i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv2i16.nxv32i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 32 x i16>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv2i16.nxv32i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 32 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg5_nxv2i16_nxv32i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv2i16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv2i16.nxv32i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv2i16_nxv32i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv2i16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv2i16.nxv32i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv2i16.nxv4i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i32>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv2i16.nxv4i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg5_nxv2i16_nxv4i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv2i16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei32.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv2i16.nxv4i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv2i16_nxv4i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv2i16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei32.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv2i16.nxv4i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv2i16.nxv16i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i8>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv2i16.nxv16i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg5_nxv2i16_nxv16i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv2i16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv2i16.nxv16i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv2i16_nxv16i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv2i16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv2i16.nxv16i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv2i16.nxv1i64(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv2i16.nxv1i64(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i64>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg5_nxv2i16_nxv1i64(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv2i16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei64.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv2i16.nxv1i64(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv2i16_nxv1i64(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv2i16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei64.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv2i16.nxv1i64(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv2i16.nxv1i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv2i16.nxv1i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg5_nxv2i16_nxv1i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv2i16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv2i16.nxv1i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv2i16_nxv1i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv2i16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv2i16.nxv1i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv2i16.nxv8i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i16>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv2i16.nxv8i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg5_nxv2i16_nxv8i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv2i16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv2i16.nxv8i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv2i16_nxv8i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv2i16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv2i16.nxv8i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv2i16.nxv4i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i8>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv2i16.nxv4i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg5_nxv2i16_nxv4i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv2i16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv2i16.nxv4i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv2i16_nxv4i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv2i16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv2i16.nxv4i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv2i16.nxv1i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv2i16.nxv1i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg5_nxv2i16_nxv1i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv2i16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv2i16.nxv1i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv2i16_nxv1i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv2i16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv2i16.nxv1i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv2i16.nxv2i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i32>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv2i16.nxv2i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg5_nxv2i16_nxv2i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv2i16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv2i16.nxv2i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv2i16_nxv2i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv2i16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv2i16.nxv2i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv2i16.nxv8i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i8>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv2i16.nxv8i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg5_nxv2i16_nxv8i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv2i16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv2i16.nxv8i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv2i16_nxv8i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv2i16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv2i16.nxv8i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv2i16.nxv4i64(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i64>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv2i16.nxv4i64(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i64>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg5_nxv2i16_nxv4i64(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv2i16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei64.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv2i16.nxv4i64(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv2i16_nxv4i64(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv2i16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei64.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv2i16.nxv4i64(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv2i16.nxv64i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 64 x i8>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv2i16.nxv64i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 64 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg5_nxv2i16_nxv64i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv2i16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv2i16.nxv64i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv2i16_nxv64i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv2i16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv2i16.nxv64i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv2i16.nxv4i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i16>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv2i16.nxv4i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg5_nxv2i16_nxv4i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv2i16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv2i16.nxv4i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv2i16_nxv4i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv2i16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv2i16.nxv4i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv2i16.nxv8i64(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i64>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv2i16.nxv8i64(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i64>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg5_nxv2i16_nxv8i64(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv2i16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei64.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv2i16.nxv8i64(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv2i16_nxv8i64(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv2i16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei64.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv2i16.nxv8i64(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv2i16.nxv1i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv2i16.nxv1i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg5_nxv2i16_nxv1i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv2i16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv2i16.nxv1i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv2i16_nxv1i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv2i16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv2i16.nxv1i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv2i16.nxv2i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i8>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv2i16.nxv2i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg5_nxv2i16_nxv2i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv2i16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv2i16.nxv2i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv2i16_nxv2i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv2i16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv2i16.nxv2i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv2i16.nxv8i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i32>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv2i16.nxv8i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg5_nxv2i16_nxv8i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv2i16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei32.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv2i16.nxv8i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv2i16_nxv8i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv2i16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei32.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv2i16.nxv8i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv2i16.nxv32i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 32 x i8>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv2i16.nxv32i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 32 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg5_nxv2i16_nxv32i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv2i16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv2i16.nxv32i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv2i16_nxv32i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv2i16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv2i16.nxv32i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv2i16.nxv16i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i32>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv2i16.nxv16i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg5_nxv2i16_nxv16i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv2i16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei32.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv2i16.nxv16i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv2i16_nxv16i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv2i16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei32.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv2i16.nxv16i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv2i16.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i16>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv2i16.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg5_nxv2i16_nxv2i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv2i16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv2i16.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv2i16_nxv2i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv2i16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv2i16.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv2i16.nxv2i64(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i64>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv2i16.nxv2i64(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg5_nxv2i16_nxv2i64(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv2i16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei64.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv2i16.nxv2i64(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv2i16_nxv2i64(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv2i16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei64.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv2i16.nxv2i64(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv2i16.nxv16i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i16>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv2i16.nxv16i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg6_nxv2i16_nxv16i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv2i16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv2i16.nxv16i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv2i16_nxv16i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv2i16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv2i16.nxv16i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv2i16.nxv32i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 32 x i16>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv2i16.nxv32i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 32 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg6_nxv2i16_nxv32i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv2i16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv2i16.nxv32i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv2i16_nxv32i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv2i16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv2i16.nxv32i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv2i16.nxv4i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i32>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv2i16.nxv4i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg6_nxv2i16_nxv4i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv2i16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei32.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv2i16.nxv4i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv2i16_nxv4i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv2i16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei32.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv2i16.nxv4i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv2i16.nxv16i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i8>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv2i16.nxv16i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg6_nxv2i16_nxv16i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv2i16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv2i16.nxv16i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv2i16_nxv16i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv2i16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv2i16.nxv16i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv2i16.nxv1i64(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv2i16.nxv1i64(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i64>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg6_nxv2i16_nxv1i64(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv2i16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei64.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv2i16.nxv1i64(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv2i16_nxv1i64(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv2i16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei64.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv2i16.nxv1i64(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv2i16.nxv1i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv2i16.nxv1i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg6_nxv2i16_nxv1i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv2i16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv2i16.nxv1i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv2i16_nxv1i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv2i16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv2i16.nxv1i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv2i16.nxv8i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i16>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv2i16.nxv8i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg6_nxv2i16_nxv8i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv2i16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv2i16.nxv8i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv2i16_nxv8i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv2i16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv2i16.nxv8i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv2i16.nxv4i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i8>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv2i16.nxv4i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg6_nxv2i16_nxv4i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv2i16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv2i16.nxv4i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv2i16_nxv4i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv2i16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv2i16.nxv4i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv2i16.nxv1i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv2i16.nxv1i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg6_nxv2i16_nxv1i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv2i16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv2i16.nxv1i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv2i16_nxv1i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv2i16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv2i16.nxv1i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv2i16.nxv2i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i32>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv2i16.nxv2i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg6_nxv2i16_nxv2i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv2i16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv2i16.nxv2i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv2i16_nxv2i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv2i16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv2i16.nxv2i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv2i16.nxv8i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i8>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv2i16.nxv8i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg6_nxv2i16_nxv8i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv2i16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv2i16.nxv8i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv2i16_nxv8i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv2i16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv2i16.nxv8i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv2i16.nxv4i64(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i64>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv2i16.nxv4i64(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i64>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg6_nxv2i16_nxv4i64(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv2i16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei64.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv2i16.nxv4i64(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv2i16_nxv4i64(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv2i16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei64.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv2i16.nxv4i64(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv2i16.nxv64i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 64 x i8>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv2i16.nxv64i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 64 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg6_nxv2i16_nxv64i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv2i16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv2i16.nxv64i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv2i16_nxv64i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv2i16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv2i16.nxv64i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv2i16.nxv4i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i16>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv2i16.nxv4i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg6_nxv2i16_nxv4i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv2i16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv2i16.nxv4i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv2i16_nxv4i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv2i16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv2i16.nxv4i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv2i16.nxv8i64(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i64>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv2i16.nxv8i64(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i64>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg6_nxv2i16_nxv8i64(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv2i16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei64.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv2i16.nxv8i64(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv2i16_nxv8i64(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv2i16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei64.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv2i16.nxv8i64(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv2i16.nxv1i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv2i16.nxv1i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg6_nxv2i16_nxv1i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv2i16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv2i16.nxv1i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv2i16_nxv1i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv2i16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv2i16.nxv1i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv2i16.nxv2i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i8>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv2i16.nxv2i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg6_nxv2i16_nxv2i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv2i16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv2i16.nxv2i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv2i16_nxv2i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv2i16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv2i16.nxv2i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv2i16.nxv8i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i32>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv2i16.nxv8i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg6_nxv2i16_nxv8i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv2i16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei32.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv2i16.nxv8i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv2i16_nxv8i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv2i16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei32.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv2i16.nxv8i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv2i16.nxv32i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 32 x i8>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv2i16.nxv32i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 32 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg6_nxv2i16_nxv32i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv2i16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv2i16.nxv32i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv2i16_nxv32i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv2i16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv2i16.nxv32i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv2i16.nxv16i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i32>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv2i16.nxv16i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg6_nxv2i16_nxv16i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv2i16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei32.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv2i16.nxv16i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv2i16_nxv16i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv2i16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei32.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv2i16.nxv16i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv2i16.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i16>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv2i16.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg6_nxv2i16_nxv2i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv2i16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv2i16.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv2i16_nxv2i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv2i16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv2i16.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv2i16.nxv2i64(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i64>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv2i16.nxv2i64(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg6_nxv2i16_nxv2i64(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv2i16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei64.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv2i16.nxv2i64(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv2i16_nxv2i64(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv2i16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei64.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv2i16.nxv2i64(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv2i16.nxv16i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i16>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv2i16.nxv16i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg7_nxv2i16_nxv16i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv2i16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv2i16.nxv16i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv2i16_nxv16i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv2i16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv2i16.nxv16i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv2i16.nxv32i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 32 x i16>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv2i16.nxv32i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 32 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg7_nxv2i16_nxv32i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv2i16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv2i16.nxv32i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv2i16_nxv32i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv2i16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv2i16.nxv32i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv2i16.nxv4i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i32>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv2i16.nxv4i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg7_nxv2i16_nxv4i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv2i16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei32.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv2i16.nxv4i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv2i16_nxv4i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv2i16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei32.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv2i16.nxv4i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv2i16.nxv16i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i8>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv2i16.nxv16i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg7_nxv2i16_nxv16i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv2i16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv2i16.nxv16i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv2i16_nxv16i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv2i16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv2i16.nxv16i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv2i16.nxv1i64(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv2i16.nxv1i64(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i64>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg7_nxv2i16_nxv1i64(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv2i16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei64.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv2i16.nxv1i64(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv2i16_nxv1i64(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv2i16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei64.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv2i16.nxv1i64(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv2i16.nxv1i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv2i16.nxv1i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg7_nxv2i16_nxv1i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv2i16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv2i16.nxv1i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv2i16_nxv1i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv2i16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv2i16.nxv1i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv2i16.nxv8i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i16>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv2i16.nxv8i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg7_nxv2i16_nxv8i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv2i16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv2i16.nxv8i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv2i16_nxv8i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv2i16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv2i16.nxv8i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv2i16.nxv4i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i8>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv2i16.nxv4i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg7_nxv2i16_nxv4i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv2i16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv2i16.nxv4i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv2i16_nxv4i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv2i16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv2i16.nxv4i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv2i16.nxv1i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv2i16.nxv1i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg7_nxv2i16_nxv1i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv2i16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv2i16.nxv1i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv2i16_nxv1i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv2i16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv2i16.nxv1i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv2i16.nxv2i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i32>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv2i16.nxv2i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg7_nxv2i16_nxv2i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv2i16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv2i16.nxv2i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv2i16_nxv2i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv2i16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv2i16.nxv2i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv2i16.nxv8i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i8>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv2i16.nxv8i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg7_nxv2i16_nxv8i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv2i16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv2i16.nxv8i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv2i16_nxv8i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv2i16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv2i16.nxv8i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv2i16.nxv4i64(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i64>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv2i16.nxv4i64(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i64>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg7_nxv2i16_nxv4i64(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv2i16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei64.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv2i16.nxv4i64(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv2i16_nxv4i64(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv2i16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei64.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv2i16.nxv4i64(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv2i16.nxv64i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 64 x i8>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv2i16.nxv64i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 64 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg7_nxv2i16_nxv64i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv2i16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv2i16.nxv64i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv2i16_nxv64i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv2i16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv2i16.nxv64i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv2i16.nxv4i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i16>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv2i16.nxv4i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg7_nxv2i16_nxv4i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv2i16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv2i16.nxv4i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv2i16_nxv4i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv2i16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv2i16.nxv4i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv2i16.nxv8i64(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i64>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv2i16.nxv8i64(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i64>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg7_nxv2i16_nxv8i64(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv2i16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei64.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv2i16.nxv8i64(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv2i16_nxv8i64(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv2i16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei64.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv2i16.nxv8i64(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv2i16.nxv1i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv2i16.nxv1i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg7_nxv2i16_nxv1i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv2i16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv2i16.nxv1i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv2i16_nxv1i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv2i16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv2i16.nxv1i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv2i16.nxv2i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i8>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv2i16.nxv2i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg7_nxv2i16_nxv2i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv2i16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv2i16.nxv2i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv2i16_nxv2i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv2i16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv2i16.nxv2i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv2i16.nxv8i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i32>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv2i16.nxv8i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg7_nxv2i16_nxv8i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv2i16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei32.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv2i16.nxv8i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv2i16_nxv8i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv2i16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei32.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv2i16.nxv8i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv2i16.nxv32i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 32 x i8>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv2i16.nxv32i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 32 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg7_nxv2i16_nxv32i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv2i16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv2i16.nxv32i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv2i16_nxv32i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv2i16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv2i16.nxv32i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv2i16.nxv16i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i32>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv2i16.nxv16i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg7_nxv2i16_nxv16i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv2i16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei32.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv2i16.nxv16i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv2i16_nxv16i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv2i16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei32.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv2i16.nxv16i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv2i16.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i16>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv2i16.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg7_nxv2i16_nxv2i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv2i16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv2i16.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv2i16_nxv2i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv2i16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv2i16.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv2i16.nxv2i64(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i64>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv2i16.nxv2i64(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg7_nxv2i16_nxv2i64(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv2i16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei64.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv2i16.nxv2i64(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv2i16_nxv2i64(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv2i16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei64.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv2i16.nxv2i64(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv2i16.nxv16i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i16>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv2i16.nxv16i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg8_nxv2i16_nxv16i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv2i16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv2i16.nxv16i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv2i16_nxv16i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv2i16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv2i16.nxv16i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv2i16.nxv32i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 32 x i16>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv2i16.nxv32i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 32 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg8_nxv2i16_nxv32i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv2i16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vmv1r.v v23, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv2i16.nxv32i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv2i16_nxv32i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv2i16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vmv1r.v v23, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv2i16.nxv32i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv2i16.nxv4i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i32>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv2i16.nxv4i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg8_nxv2i16_nxv4i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv2i16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei32.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv2i16.nxv4i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv2i16_nxv4i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv2i16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei32.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv2i16.nxv4i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv2i16.nxv16i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i8>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv2i16.nxv16i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg8_nxv2i16_nxv16i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv2i16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv2i16.nxv16i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv2i16_nxv16i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv2i16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv2i16.nxv16i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv2i16.nxv1i64(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv2i16.nxv1i64(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i64>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg8_nxv2i16_nxv1i64(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv2i16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei64.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv2i16.nxv1i64(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv2i16_nxv1i64(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv2i16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei64.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv2i16.nxv1i64(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv2i16.nxv1i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv2i16.nxv1i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg8_nxv2i16_nxv1i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv2i16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv2i16.nxv1i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv2i16_nxv1i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv2i16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv2i16.nxv1i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv2i16.nxv8i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i16>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv2i16.nxv8i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg8_nxv2i16_nxv8i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv2i16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv2i16.nxv8i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv2i16_nxv8i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv2i16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv2i16.nxv8i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv2i16.nxv4i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i8>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv2i16.nxv4i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg8_nxv2i16_nxv4i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv2i16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv2i16.nxv4i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv2i16_nxv4i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv2i16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv2i16.nxv4i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv2i16.nxv1i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv2i16.nxv1i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg8_nxv2i16_nxv1i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv2i16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv2i16.nxv1i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv2i16_nxv1i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv2i16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv2i16.nxv1i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv2i16.nxv2i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i32>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv2i16.nxv2i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg8_nxv2i16_nxv2i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv2i16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv2i16.nxv2i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv2i16_nxv2i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv2i16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv2i16.nxv2i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv2i16.nxv8i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i8>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv2i16.nxv8i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg8_nxv2i16_nxv8i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv2i16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv2i16.nxv8i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv2i16_nxv8i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv2i16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv2i16.nxv8i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv2i16.nxv4i64(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i64>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv2i16.nxv4i64(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i64>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg8_nxv2i16_nxv4i64(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv2i16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei64.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv2i16.nxv4i64(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv2i16_nxv4i64(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv2i16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei64.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv2i16.nxv4i64(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv2i16.nxv64i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 64 x i8>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv2i16.nxv64i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 64 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg8_nxv2i16_nxv64i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv2i16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vmv1r.v v23, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv2i16.nxv64i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 64 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv2i16_nxv64i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv2i16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vmv1r.v v23, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv2i16.nxv64i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv2i16.nxv4i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i16>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv2i16.nxv4i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 4 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg8_nxv2i16_nxv4i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv2i16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv2i16.nxv4i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv2i16_nxv4i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv2i16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv2i16.nxv4i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv2i16.nxv8i64(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i64>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv2i16.nxv8i64(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i64>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg8_nxv2i16_nxv8i64(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv2i16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vmv1r.v v23, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei64.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv2i16.nxv8i64(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv2i16_nxv8i64(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv2i16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vmv1r.v v23, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei64.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv2i16.nxv8i64(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv2i16.nxv1i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv2i16.nxv1i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 1 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg8_nxv2i16_nxv1i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv2i16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv2i16.nxv1i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv2i16_nxv1i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv2i16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv2i16.nxv1i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv2i16.nxv2i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i8>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv2i16.nxv2i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg8_nxv2i16_nxv2i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv2i16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv2i16.nxv2i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv2i16_nxv2i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv2i16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv2i16.nxv2i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv2i16.nxv8i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i32>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv2i16.nxv8i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 8 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg8_nxv2i16_nxv8i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv2i16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei32.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv2i16.nxv8i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv2i16_nxv8i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv2i16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei32.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv2i16.nxv8i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv2i16.nxv32i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 32 x i8>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv2i16.nxv32i8(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 32 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg8_nxv2i16_nxv32i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv2i16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv2i16.nxv32i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv2i16_nxv32i8(<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv2i16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv2i16.nxv32i8(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv2i16.nxv16i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i32>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv2i16.nxv16i32(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 16 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg8_nxv2i16_nxv16i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv2i16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vmv1r.v v23, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei32.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv2i16.nxv16i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv2i16_nxv16i32(<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv2i16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vmv1r.v v23, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei32.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv2i16.nxv16i32(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv2i16.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i16>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv2i16.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg8_nxv2i16_nxv2i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv2i16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv2i16.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv2i16_nxv2i16(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv2i16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv2i16.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv2i16.nxv2i64(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i64>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv2i16.nxv2i64(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg8_nxv2i16_nxv2i64(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv2i16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei64.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv2i16.nxv2i64(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv2i16_nxv2i64(<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv2i16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei64.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv2i16.nxv2i64(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv2i64.nxv16i16(<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 16 x i16>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv2i64.nxv16i16(<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 16 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg2_nxv2i64_nxv16i16(<vscale x 2 x i64> %val, i64* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv2i64_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv2i64.nxv16i16(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 16 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv2i64_nxv16i16(<vscale x 2 x i64> %val, i64* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv2i64_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv2i64.nxv16i16(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv2i64.nxv32i16(<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 32 x i16>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv2i64.nxv32i16(<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 32 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg2_nxv2i64_nxv32i16(<vscale x 2 x i64> %val, i64* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv2i64_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a2, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv2i64.nxv32i16(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 32 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv2i64_nxv32i16(<vscale x 2 x i64> %val, i64* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv2i64_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a2, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv2i64.nxv32i16(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv2i64.nxv4i32(<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 4 x i32>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv2i64.nxv4i32(<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 4 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg2_nxv2i64_nxv4i32(<vscale x 2 x i64> %val, i64* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv2i64_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv2r.v v26, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v26
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv2i64.nxv4i32(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 4 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv2i64_nxv4i32(<vscale x 2 x i64> %val, i64* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv2i64_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv2r.v v26, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v26, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv2i64.nxv4i32(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv2i64.nxv16i8(<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 16 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv2i64.nxv16i8(<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 16 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg2_nxv2i64_nxv16i8(<vscale x 2 x i64> %val, i64* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv2i64_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv2r.v v26, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v26
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv2i64.nxv16i8(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 16 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv2i64_nxv16i8(<vscale x 2 x i64> %val, i64* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv2i64_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv2r.v v26, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v26, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv2i64.nxv16i8(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv2i64.nxv1i64(<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv2i64.nxv1i64(<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 1 x i64>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg2_nxv2i64_nxv1i64(<vscale x 2 x i64> %val, i64* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv2i64_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv1r.v v25, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv2i64.nxv1i64(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 1 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv2i64_nxv1i64(<vscale x 2 x i64> %val, i64* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv2i64_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv1r.v v25, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv2i64.nxv1i64(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv2i64.nxv1i32(<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv2i64.nxv1i32(<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 1 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg2_nxv2i64_nxv1i32(<vscale x 2 x i64> %val, i64* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv2i64_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv1r.v v25, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv2i64.nxv1i32(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 1 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv2i64_nxv1i32(<vscale x 2 x i64> %val, i64* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv2i64_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv1r.v v25, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv2i64.nxv1i32(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv2i64.nxv8i16(<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 8 x i16>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv2i64.nxv8i16(<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 8 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg2_nxv2i64_nxv8i16(<vscale x 2 x i64> %val, i64* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv2i64_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv2r.v v26, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v26
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv2i64.nxv8i16(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 8 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv2i64_nxv8i16(<vscale x 2 x i64> %val, i64* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv2i64_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv2r.v v26, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v26, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv2i64.nxv8i16(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv2i64.nxv4i8(<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 4 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv2i64.nxv4i8(<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 4 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg2_nxv2i64_nxv4i8(<vscale x 2 x i64> %val, i64* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv2i64_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv1r.v v25, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv2i64.nxv4i8(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 4 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv2i64_nxv4i8(<vscale x 2 x i64> %val, i64* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv2i64_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv1r.v v25, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv2i64.nxv4i8(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv2i64.nxv1i16(<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv2i64.nxv1i16(<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 1 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg2_nxv2i64_nxv1i16(<vscale x 2 x i64> %val, i64* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv2i64_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv1r.v v25, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv2i64.nxv1i16(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 1 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv2i64_nxv1i16(<vscale x 2 x i64> %val, i64* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv2i64_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv1r.v v25, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv2i64.nxv1i16(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv2i64.nxv2i32(<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 2 x i32>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv2i64.nxv2i32(<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg2_nxv2i64_nxv2i32(<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv2i64_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv1r.v v25, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv2i64.nxv2i32(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv2i64_nxv2i32(<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv2i64_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv1r.v v25, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv2i64.nxv2i32(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv2i64.nxv8i8(<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 8 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv2i64.nxv8i8(<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 8 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg2_nxv2i64_nxv8i8(<vscale x 2 x i64> %val, i64* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv2i64_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv1r.v v25, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv2i64.nxv8i8(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 8 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv2i64_nxv8i8(<vscale x 2 x i64> %val, i64* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv2i64_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv1r.v v25, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv2i64.nxv8i8(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv2i64.nxv4i64(<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 4 x i64>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv2i64.nxv4i64(<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 4 x i64>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg2_nxv2i64_nxv4i64(<vscale x 2 x i64> %val, i64* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv2i64_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv2i64.nxv4i64(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 4 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv2i64_nxv4i64(<vscale x 2 x i64> %val, i64* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv2i64_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv2i64.nxv4i64(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv2i64.nxv64i8(<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 64 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv2i64.nxv64i8(<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 64 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg2_nxv2i64_nxv64i8(<vscale x 2 x i64> %val, i64* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv2i64_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a2, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv2i64.nxv64i8(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 64 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv2i64_nxv64i8(<vscale x 2 x i64> %val, i64* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv2i64_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a2, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv2i64.nxv64i8(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv2i64.nxv4i16(<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 4 x i16>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv2i64.nxv4i16(<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 4 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg2_nxv2i64_nxv4i16(<vscale x 2 x i64> %val, i64* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv2i64_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv1r.v v25, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv2i64.nxv4i16(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 4 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv2i64_nxv4i16(<vscale x 2 x i64> %val, i64* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv2i64_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv1r.v v25, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv2i64.nxv4i16(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv2i64.nxv8i64(<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 8 x i64>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv2i64.nxv8i64(<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 8 x i64>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg2_nxv2i64_nxv8i64(<vscale x 2 x i64> %val, i64* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv2i64_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a2, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv2i64.nxv8i64(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 8 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv2i64_nxv8i64(<vscale x 2 x i64> %val, i64* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv2i64_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a2, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv2i64.nxv8i64(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv2i64.nxv1i8(<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv2i64.nxv1i8(<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 1 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg2_nxv2i64_nxv1i8(<vscale x 2 x i64> %val, i64* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv2i64_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv1r.v v25, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv2i64.nxv1i8(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 1 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv2i64_nxv1i8(<vscale x 2 x i64> %val, i64* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv2i64_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv1r.v v25, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv2i64.nxv1i8(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv2i64.nxv2i8(<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 2 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv2i64.nxv2i8(<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg2_nxv2i64_nxv2i8(<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv2i64_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv1r.v v25, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv2i64.nxv2i8(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv2i64_nxv2i8(<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv2i64_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv1r.v v25, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv2i64.nxv2i8(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv2i64.nxv8i32(<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 8 x i32>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv2i64.nxv8i32(<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 8 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg2_nxv2i64_nxv8i32(<vscale x 2 x i64> %val, i64* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv2i64_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv2i64.nxv8i32(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 8 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv2i64_nxv8i32(<vscale x 2 x i64> %val, i64* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv2i64_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv2i64.nxv8i32(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv2i64.nxv32i8(<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 32 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv2i64.nxv32i8(<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 32 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg2_nxv2i64_nxv32i8(<vscale x 2 x i64> %val, i64* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv2i64_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv2i64.nxv32i8(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 32 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv2i64_nxv32i8(<vscale x 2 x i64> %val, i64* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv2i64_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv2i64.nxv32i8(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv2i64.nxv16i32(<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 16 x i32>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv2i64.nxv16i32(<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 16 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg2_nxv2i64_nxv16i32(<vscale x 2 x i64> %val, i64* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv2i64_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a2, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv2i64.nxv16i32(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 16 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv2i64_nxv16i32(<vscale x 2 x i64> %val, i64* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv2i64_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a2, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv2i64.nxv16i32(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv2i64.nxv2i16(<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 2 x i16>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv2i64.nxv2i16(<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg2_nxv2i64_nxv2i16(<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv2i64_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv1r.v v25, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv2i64.nxv2i16(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv2i64_nxv2i16(<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv2i64_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv1r.v v25, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv2i64.nxv2i16(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv2i64.nxv2i64(<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 2 x i64>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv2i64.nxv2i64(<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg2_nxv2i64_nxv2i64(<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv2i64_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv2r.v v26, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v26
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv2i64.nxv2i64(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv2i64_nxv2i64(<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv2i64_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv2r.v v26, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v26, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv2i64.nxv2i64(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv2i64.nxv16i16(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 16 x i16>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv2i64.nxv16i16(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 16 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg3_nxv2i64_nxv16i16(<vscale x 2 x i64> %val, i64* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv2i64_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv2i64.nxv16i16(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 16 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv2i64_nxv16i16(<vscale x 2 x i64> %val, i64* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv2i64_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v2, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv2i64.nxv16i16(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv2i64.nxv32i16(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 32 x i16>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv2i64.nxv32i16(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 32 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg3_nxv2i64_nxv32i16(<vscale x 2 x i64> %val, i64* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv2i64_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vmv2r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv2i64.nxv32i16(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 32 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv2i64_nxv32i16(<vscale x 2 x i64> %val, i64* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv2i64_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vmv2r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv2i64.nxv32i16(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv2i64.nxv4i32(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 4 x i32>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv2i64.nxv4i32(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 4 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg3_nxv2i64_nxv4i32(<vscale x 2 x i64> %val, i64* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv2i64_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv2i64.nxv4i32(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 4 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv2i64_nxv4i32(<vscale x 2 x i64> %val, i64* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv2i64_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv2i64.nxv4i32(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv2i64.nxv16i8(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 16 x i8>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv2i64.nxv16i8(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 16 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg3_nxv2i64_nxv16i8(<vscale x 2 x i64> %val, i64* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv2i64_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv2i64.nxv16i8(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 16 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv2i64_nxv16i8(<vscale x 2 x i64> %val, i64* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv2i64_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv2i64.nxv16i8(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv2i64.nxv1i64(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv2i64.nxv1i64(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 1 x i64>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg3_nxv2i64_nxv1i64(<vscale x 2 x i64> %val, i64* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv2i64_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei64.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv2i64.nxv1i64(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 1 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv2i64_nxv1i64(<vscale x 2 x i64> %val, i64* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv2i64_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei64.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv2i64.nxv1i64(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv2i64.nxv1i32(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv2i64.nxv1i32(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 1 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg3_nxv2i64_nxv1i32(<vscale x 2 x i64> %val, i64* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv2i64_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv2i64.nxv1i32(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 1 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv2i64_nxv1i32(<vscale x 2 x i64> %val, i64* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv2i64_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv2i64.nxv1i32(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv2i64.nxv8i16(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 8 x i16>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv2i64.nxv8i16(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 8 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg3_nxv2i64_nxv8i16(<vscale x 2 x i64> %val, i64* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv2i64_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv2i64.nxv8i16(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 8 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv2i64_nxv8i16(<vscale x 2 x i64> %val, i64* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv2i64_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv2i64.nxv8i16(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv2i64.nxv4i8(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 4 x i8>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv2i64.nxv4i8(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 4 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg3_nxv2i64_nxv4i8(<vscale x 2 x i64> %val, i64* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv2i64_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv2i64.nxv4i8(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 4 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv2i64_nxv4i8(<vscale x 2 x i64> %val, i64* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv2i64_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv2i64.nxv4i8(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv2i64.nxv1i16(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv2i64.nxv1i16(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 1 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg3_nxv2i64_nxv1i16(<vscale x 2 x i64> %val, i64* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv2i64_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv2i64.nxv1i16(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 1 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv2i64_nxv1i16(<vscale x 2 x i64> %val, i64* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv2i64_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv2i64.nxv1i16(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv2i64.nxv2i32(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 2 x i32>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv2i64.nxv2i32(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg3_nxv2i64_nxv2i32(<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv2i64_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv2i64.nxv2i32(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv2i64_nxv2i32(<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv2i64_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv2i64.nxv2i32(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv2i64.nxv8i8(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 8 x i8>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv2i64.nxv8i8(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 8 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg3_nxv2i64_nxv8i8(<vscale x 2 x i64> %val, i64* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv2i64_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv2i64.nxv8i8(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 8 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv2i64_nxv8i8(<vscale x 2 x i64> %val, i64* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv2i64_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv2i64.nxv8i8(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv2i64.nxv4i64(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 4 x i64>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv2i64.nxv4i64(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 4 x i64>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg3_nxv2i64_nxv4i64(<vscale x 2 x i64> %val, i64* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv2i64_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei64.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv2i64.nxv4i64(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 4 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv2i64_nxv4i64(<vscale x 2 x i64> %val, i64* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv2i64_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei64.v v2, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv2i64.nxv4i64(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv2i64.nxv64i8(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 64 x i8>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv2i64.nxv64i8(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 64 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg3_nxv2i64_nxv64i8(<vscale x 2 x i64> %val, i64* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv2i64_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vmv2r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv2i64.nxv64i8(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 64 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv2i64_nxv64i8(<vscale x 2 x i64> %val, i64* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv2i64_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vmv2r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv2i64.nxv64i8(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv2i64.nxv4i16(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 4 x i16>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv2i64.nxv4i16(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 4 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg3_nxv2i64_nxv4i16(<vscale x 2 x i64> %val, i64* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv2i64_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv2i64.nxv4i16(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 4 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv2i64_nxv4i16(<vscale x 2 x i64> %val, i64* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv2i64_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv2i64.nxv4i16(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv2i64.nxv8i64(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 8 x i64>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv2i64.nxv8i64(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 8 x i64>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg3_nxv2i64_nxv8i64(<vscale x 2 x i64> %val, i64* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv2i64_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vmv2r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei64.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv2i64.nxv8i64(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 8 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv2i64_nxv8i64(<vscale x 2 x i64> %val, i64* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv2i64_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vmv2r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei64.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv2i64.nxv8i64(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv2i64.nxv1i8(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv2i64.nxv1i8(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 1 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg3_nxv2i64_nxv1i8(<vscale x 2 x i64> %val, i64* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv2i64_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv2i64.nxv1i8(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 1 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv2i64_nxv1i8(<vscale x 2 x i64> %val, i64* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv2i64_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv2i64.nxv1i8(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv2i64.nxv2i8(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 2 x i8>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv2i64.nxv2i8(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg3_nxv2i64_nxv2i8(<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv2i64_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv2i64.nxv2i8(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv2i64_nxv2i8(<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv2i64_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv2i64.nxv2i8(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv2i64.nxv8i32(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 8 x i32>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv2i64.nxv8i32(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 8 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg3_nxv2i64_nxv8i32(<vscale x 2 x i64> %val, i64* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv2i64_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv2i64.nxv8i32(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 8 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv2i64_nxv8i32(<vscale x 2 x i64> %val, i64* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv2i64_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v2, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv2i64.nxv8i32(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv2i64.nxv32i8(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 32 x i8>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv2i64.nxv32i8(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 32 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg3_nxv2i64_nxv32i8(<vscale x 2 x i64> %val, i64* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv2i64_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv2i64.nxv32i8(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 32 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv2i64_nxv32i8(<vscale x 2 x i64> %val, i64* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv2i64_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v2, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv2i64.nxv32i8(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv2i64.nxv16i32(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 16 x i32>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv2i64.nxv16i32(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 16 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg3_nxv2i64_nxv16i32(<vscale x 2 x i64> %val, i64* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv2i64_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vmv2r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv2i64.nxv16i32(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 16 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv2i64_nxv16i32(<vscale x 2 x i64> %val, i64* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv2i64_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vmv2r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv2i64.nxv16i32(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv2i64.nxv2i16(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 2 x i16>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv2i64.nxv2i16(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg3_nxv2i64_nxv2i16(<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv2i64_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv2i64.nxv2i16(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv2i64_nxv2i16(<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv2i64_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv2i64.nxv2i16(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv2i64.nxv2i64(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 2 x i64>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv2i64.nxv2i64(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg3_nxv2i64_nxv2i64(<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv2i64_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei64.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv2i64.nxv2i64(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv2i64_nxv2i64(<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv2i64_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei64.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv2i64.nxv2i64(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv2i64.nxv16i16(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 16 x i16>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv2i64.nxv16i16(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 16 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg4_nxv2i64_nxv16i16(<vscale x 2 x i64> %val, i64* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv2i64_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vmv2r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv2i64.nxv16i16(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 16 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv2i64_nxv16i16(<vscale x 2 x i64> %val, i64* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv2i64_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v2, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv2i64.nxv16i16(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv2i64.nxv32i16(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 32 x i16>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv2i64.nxv32i16(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 32 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg4_nxv2i64_nxv32i16(<vscale x 2 x i64> %val, i64* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv2i64_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2_v22m2
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vmv2r.v v20, v16
+; CHECK-NEXT:    vmv2r.v v22, v16
+; CHECK-NEXT:    vsetvli a1, a2, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv2i64.nxv32i16(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 32 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv2i64_nxv32i16(<vscale x 2 x i64> %val, i64* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv2i64_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2_v22m2
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vmv2r.v v20, v16
+; CHECK-NEXT:    vmv2r.v v22, v16
+; CHECK-NEXT:    vsetvli a1, a2, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv2i64.nxv32i16(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv2i64.nxv4i32(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 4 x i32>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv2i64.nxv4i32(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 4 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg4_nxv2i64_nxv4i32(<vscale x 2 x i64> %val, i64* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv2i64_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vmv2r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv2i64.nxv4i32(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 4 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv2i64_nxv4i32(<vscale x 2 x i64> %val, i64* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv2i64_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv2i64.nxv4i32(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv2i64.nxv16i8(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 16 x i8>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv2i64.nxv16i8(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 16 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg4_nxv2i64_nxv16i8(<vscale x 2 x i64> %val, i64* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv2i64_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vmv2r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv2i64.nxv16i8(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 16 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv2i64_nxv16i8(<vscale x 2 x i64> %val, i64* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv2i64_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv2i64.nxv16i8(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv2i64.nxv1i64(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv2i64.nxv1i64(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 1 x i64>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg4_nxv2i64_nxv1i64(<vscale x 2 x i64> %val, i64* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv2i64_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vmv2r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei64.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv2i64.nxv1i64(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 1 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv2i64_nxv1i64(<vscale x 2 x i64> %val, i64* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv2i64_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei64.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv2i64.nxv1i64(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv2i64.nxv1i32(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv2i64.nxv1i32(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 1 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg4_nxv2i64_nxv1i32(<vscale x 2 x i64> %val, i64* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv2i64_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vmv2r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv2i64.nxv1i32(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 1 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv2i64_nxv1i32(<vscale x 2 x i64> %val, i64* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv2i64_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv2i64.nxv1i32(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv2i64.nxv8i16(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 8 x i16>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv2i64.nxv8i16(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 8 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg4_nxv2i64_nxv8i16(<vscale x 2 x i64> %val, i64* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv2i64_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vmv2r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv2i64.nxv8i16(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 8 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv2i64_nxv8i16(<vscale x 2 x i64> %val, i64* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv2i64_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv2i64.nxv8i16(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv2i64.nxv4i8(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 4 x i8>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv2i64.nxv4i8(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 4 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg4_nxv2i64_nxv4i8(<vscale x 2 x i64> %val, i64* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv2i64_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vmv2r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv2i64.nxv4i8(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 4 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv2i64_nxv4i8(<vscale x 2 x i64> %val, i64* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv2i64_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv2i64.nxv4i8(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv2i64.nxv1i16(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv2i64.nxv1i16(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 1 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg4_nxv2i64_nxv1i16(<vscale x 2 x i64> %val, i64* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv2i64_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vmv2r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv2i64.nxv1i16(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 1 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv2i64_nxv1i16(<vscale x 2 x i64> %val, i64* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv2i64_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv2i64.nxv1i16(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv2i64.nxv2i32(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 2 x i32>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv2i64.nxv2i32(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg4_nxv2i64_nxv2i32(<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv2i64_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vmv2r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv2i64.nxv2i32(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv2i64_nxv2i32(<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv2i64_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv2i64.nxv2i32(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv2i64.nxv8i8(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 8 x i8>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv2i64.nxv8i8(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 8 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg4_nxv2i64_nxv8i8(<vscale x 2 x i64> %val, i64* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv2i64_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vmv2r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv2i64.nxv8i8(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 8 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv2i64_nxv8i8(<vscale x 2 x i64> %val, i64* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv2i64_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv2i64.nxv8i8(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv2i64.nxv4i64(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 4 x i64>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv2i64.nxv4i64(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 4 x i64>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg4_nxv2i64_nxv4i64(<vscale x 2 x i64> %val, i64* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv2i64_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vmv2r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei64.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv2i64.nxv4i64(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 4 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv2i64_nxv4i64(<vscale x 2 x i64> %val, i64* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv2i64_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei64.v v2, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv2i64.nxv4i64(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv2i64.nxv64i8(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 64 x i8>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv2i64.nxv64i8(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 64 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg4_nxv2i64_nxv64i8(<vscale x 2 x i64> %val, i64* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv2i64_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2_v22m2
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vmv2r.v v20, v16
+; CHECK-NEXT:    vmv2r.v v22, v16
+; CHECK-NEXT:    vsetvli a1, a2, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv2i64.nxv64i8(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 64 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv2i64_nxv64i8(<vscale x 2 x i64> %val, i64* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv2i64_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2_v22m2
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vmv2r.v v20, v16
+; CHECK-NEXT:    vmv2r.v v22, v16
+; CHECK-NEXT:    vsetvli a1, a2, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv2i64.nxv64i8(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv2i64.nxv4i16(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 4 x i16>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv2i64.nxv4i16(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 4 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg4_nxv2i64_nxv4i16(<vscale x 2 x i64> %val, i64* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv2i64_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vmv2r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv2i64.nxv4i16(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 4 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv2i64_nxv4i16(<vscale x 2 x i64> %val, i64* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv2i64_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv2i64.nxv4i16(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv2i64.nxv8i64(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 8 x i64>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv2i64.nxv8i64(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 8 x i64>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg4_nxv2i64_nxv8i64(<vscale x 2 x i64> %val, i64* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv2i64_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2_v22m2
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vmv2r.v v20, v16
+; CHECK-NEXT:    vmv2r.v v22, v16
+; CHECK-NEXT:    vsetvli a1, a2, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei64.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv2i64.nxv8i64(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 8 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv2i64_nxv8i64(<vscale x 2 x i64> %val, i64* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv2i64_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2_v22m2
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vmv2r.v v20, v16
+; CHECK-NEXT:    vmv2r.v v22, v16
+; CHECK-NEXT:    vsetvli a1, a2, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei64.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv2i64.nxv8i64(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv2i64.nxv1i8(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv2i64.nxv1i8(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 1 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg4_nxv2i64_nxv1i8(<vscale x 2 x i64> %val, i64* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv2i64_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vmv2r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv2i64.nxv1i8(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 1 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv2i64_nxv1i8(<vscale x 2 x i64> %val, i64* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv2i64_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv2i64.nxv1i8(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv2i64.nxv2i8(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 2 x i8>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv2i64.nxv2i8(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg4_nxv2i64_nxv2i8(<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv2i64_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vmv2r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv2i64.nxv2i8(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv2i64_nxv2i8(<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv2i64_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv2i64.nxv2i8(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv2i64.nxv8i32(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 8 x i32>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv2i64.nxv8i32(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 8 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg4_nxv2i64_nxv8i32(<vscale x 2 x i64> %val, i64* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv2i64_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vmv2r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv2i64.nxv8i32(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 8 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv2i64_nxv8i32(<vscale x 2 x i64> %val, i64* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv2i64_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v2, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv2i64.nxv8i32(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv2i64.nxv32i8(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 32 x i8>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv2i64.nxv32i8(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 32 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg4_nxv2i64_nxv32i8(<vscale x 2 x i64> %val, i64* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv2i64_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vmv2r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv2i64.nxv32i8(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 32 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv2i64_nxv32i8(<vscale x 2 x i64> %val, i64* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv2i64_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v2, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv2i64.nxv32i8(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv2i64.nxv16i32(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 16 x i32>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv2i64.nxv16i32(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 16 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg4_nxv2i64_nxv16i32(<vscale x 2 x i64> %val, i64* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv2i64_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2_v22m2
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vmv2r.v v20, v16
+; CHECK-NEXT:    vmv2r.v v22, v16
+; CHECK-NEXT:    vsetvli a1, a2, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv2i64.nxv16i32(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 16 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv2i64_nxv16i32(<vscale x 2 x i64> %val, i64* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv2i64_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2_v22m2
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vmv2r.v v20, v16
+; CHECK-NEXT:    vmv2r.v v22, v16
+; CHECK-NEXT:    vsetvli a1, a2, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv2i64.nxv16i32(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv2i64.nxv2i16(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 2 x i16>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv2i64.nxv2i16(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg4_nxv2i64_nxv2i16(<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv2i64_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vmv2r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv2i64.nxv2i16(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv2i64_nxv2i16(<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv2i64_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv2i64.nxv2i16(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv2i64.nxv2i64(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 2 x i64>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv2i64.nxv2i64(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg4_nxv2i64_nxv2i64(<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv2i64_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vmv2r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei64.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv2i64.nxv2i64(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv2i64_nxv2i64(<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv2i64_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei64.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv2i64.nxv2i64(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv16f16.nxv16i16(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 16 x i16>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv16f16.nxv16i16(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 16 x i16>, <vscale x 16 x i1>, i64)
+
+define void @test_vsxseg2_nxv16f16_nxv16i16(<vscale x 16 x half> %val, half* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv16f16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv4r.v v28, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v28
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv16f16.nxv16i16(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 16 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv16f16_nxv16i16(<vscale x 16 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv16f16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv4r.v v28, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v28, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv16f16.nxv16i16(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv16f16.nxv32i16(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 32 x i16>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv16f16.nxv32i16(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 32 x i16>, <vscale x 16 x i1>, i64)
+
+define void @test_vsxseg2_nxv16f16_nxv32i16(<vscale x 16 x half> %val, half* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv16f16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv16f16.nxv32i16(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 32 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv16f16_nxv32i16(<vscale x 16 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv16f16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv16f16.nxv32i16(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv16f16.nxv4i32(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 4 x i32>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv16f16.nxv4i32(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 4 x i32>, <vscale x 16 x i1>, i64)
+
+define void @test_vsxseg2_nxv16f16_nxv4i32(<vscale x 16 x half> %val, half* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv16f16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv2r.v v26, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v26
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv16f16.nxv4i32(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 4 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv16f16_nxv4i32(<vscale x 16 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv16f16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv2r.v v26, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v26, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv16f16.nxv4i32(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv16f16.nxv16i8(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 16 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv16f16.nxv16i8(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 16 x i8>, <vscale x 16 x i1>, i64)
+
+define void @test_vsxseg2_nxv16f16_nxv16i8(<vscale x 16 x half> %val, half* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv16f16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv2r.v v26, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v26
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv16f16.nxv16i8(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 16 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv16f16_nxv16i8(<vscale x 16 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv16f16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv2r.v v26, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v26, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv16f16.nxv16i8(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv16f16.nxv1i64(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv16f16.nxv1i64(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 1 x i64>, <vscale x 16 x i1>, i64)
+
+define void @test_vsxseg2_nxv16f16_nxv1i64(<vscale x 16 x half> %val, half* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv16f16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv1r.v v25, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv16f16.nxv1i64(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 1 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv16f16_nxv1i64(<vscale x 16 x half> %val, half* %base, <vscale x 1 x i64> %index, <vscale x 16 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv16f16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv1r.v v25, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv16f16.nxv1i64(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 1 x i64> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv16f16.nxv1i32(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv16f16.nxv1i32(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 1 x i32>, <vscale x 16 x i1>, i64)
+
+define void @test_vsxseg2_nxv16f16_nxv1i32(<vscale x 16 x half> %val, half* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv16f16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv1r.v v25, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv16f16.nxv1i32(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 1 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv16f16_nxv1i32(<vscale x 16 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv16f16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv1r.v v25, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv16f16.nxv1i32(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv16f16.nxv8i16(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 8 x i16>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv16f16.nxv8i16(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 8 x i16>, <vscale x 16 x i1>, i64)
+
+define void @test_vsxseg2_nxv16f16_nxv8i16(<vscale x 16 x half> %val, half* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv16f16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv2r.v v26, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v26
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv16f16.nxv8i16(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 8 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv16f16_nxv8i16(<vscale x 16 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv16f16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv2r.v v26, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v26, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv16f16.nxv8i16(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv16f16.nxv4i8(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 4 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv16f16.nxv4i8(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 4 x i8>, <vscale x 16 x i1>, i64)
+
+define void @test_vsxseg2_nxv16f16_nxv4i8(<vscale x 16 x half> %val, half* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv16f16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv1r.v v25, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv16f16.nxv4i8(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 4 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv16f16_nxv4i8(<vscale x 16 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv16f16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv1r.v v25, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv16f16.nxv4i8(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv16f16.nxv1i16(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv16f16.nxv1i16(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 1 x i16>, <vscale x 16 x i1>, i64)
+
+define void @test_vsxseg2_nxv16f16_nxv1i16(<vscale x 16 x half> %val, half* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv16f16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv1r.v v25, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv16f16.nxv1i16(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 1 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv16f16_nxv1i16(<vscale x 16 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv16f16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv1r.v v25, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv16f16.nxv1i16(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv16f16.nxv2i32(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 2 x i32>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv16f16.nxv2i32(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 2 x i32>, <vscale x 16 x i1>, i64)
+
+define void @test_vsxseg2_nxv16f16_nxv2i32(<vscale x 16 x half> %val, half* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv16f16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv1r.v v25, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv16f16.nxv2i32(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 2 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv16f16_nxv2i32(<vscale x 16 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv16f16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv1r.v v25, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv16f16.nxv2i32(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv16f16.nxv8i8(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 8 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv16f16.nxv8i8(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 8 x i8>, <vscale x 16 x i1>, i64)
+
+define void @test_vsxseg2_nxv16f16_nxv8i8(<vscale x 16 x half> %val, half* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv16f16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv1r.v v25, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv16f16.nxv8i8(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 8 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv16f16_nxv8i8(<vscale x 16 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv16f16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv1r.v v25, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv16f16.nxv8i8(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv16f16.nxv4i64(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 4 x i64>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv16f16.nxv4i64(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 4 x i64>, <vscale x 16 x i1>, i64)
+
+define void @test_vsxseg2_nxv16f16_nxv4i64(<vscale x 16 x half> %val, half* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv16f16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv4r.v v28, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v28
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv16f16.nxv4i64(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 4 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv16f16_nxv4i64(<vscale x 16 x half> %val, half* %base, <vscale x 4 x i64> %index, <vscale x 16 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv16f16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv4r.v v28, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v28, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv16f16.nxv4i64(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 4 x i64> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv16f16.nxv64i8(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 64 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv16f16.nxv64i8(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 64 x i8>, <vscale x 16 x i1>, i64)
+
+define void @test_vsxseg2_nxv16f16_nxv64i8(<vscale x 16 x half> %val, half* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv16f16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv16f16.nxv64i8(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 64 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv16f16_nxv64i8(<vscale x 16 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv16f16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv16f16.nxv64i8(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv16f16.nxv4i16(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 4 x i16>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv16f16.nxv4i16(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 4 x i16>, <vscale x 16 x i1>, i64)
+
+define void @test_vsxseg2_nxv16f16_nxv4i16(<vscale x 16 x half> %val, half* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv16f16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv1r.v v25, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv16f16.nxv4i16(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 4 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv16f16_nxv4i16(<vscale x 16 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv16f16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv1r.v v25, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv16f16.nxv4i16(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv16f16.nxv8i64(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 8 x i64>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv16f16.nxv8i64(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 8 x i64>, <vscale x 16 x i1>, i64)
+
+define void @test_vsxseg2_nxv16f16_nxv8i64(<vscale x 16 x half> %val, half* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv16f16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv16f16.nxv8i64(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 8 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv16f16_nxv8i64(<vscale x 16 x half> %val, half* %base, <vscale x 8 x i64> %index, <vscale x 16 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv16f16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv16f16.nxv8i64(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 8 x i64> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv16f16.nxv1i8(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv16f16.nxv1i8(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 1 x i8>, <vscale x 16 x i1>, i64)
+
+define void @test_vsxseg2_nxv16f16_nxv1i8(<vscale x 16 x half> %val, half* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv16f16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv1r.v v25, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv16f16.nxv1i8(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 1 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv16f16_nxv1i8(<vscale x 16 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv16f16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv1r.v v25, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv16f16.nxv1i8(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv16f16.nxv2i8(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 2 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv16f16.nxv2i8(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 2 x i8>, <vscale x 16 x i1>, i64)
+
+define void @test_vsxseg2_nxv16f16_nxv2i8(<vscale x 16 x half> %val, half* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv16f16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv1r.v v25, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv16f16.nxv2i8(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 2 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv16f16_nxv2i8(<vscale x 16 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv16f16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv1r.v v25, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv16f16.nxv2i8(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv16f16.nxv8i32(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 8 x i32>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv16f16.nxv8i32(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 8 x i32>, <vscale x 16 x i1>, i64)
+
+define void @test_vsxseg2_nxv16f16_nxv8i32(<vscale x 16 x half> %val, half* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv16f16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv4r.v v28, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v28
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv16f16.nxv8i32(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 8 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv16f16_nxv8i32(<vscale x 16 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv16f16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv4r.v v28, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v28, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv16f16.nxv8i32(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv16f16.nxv32i8(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 32 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv16f16.nxv32i8(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 32 x i8>, <vscale x 16 x i1>, i64)
+
+define void @test_vsxseg2_nxv16f16_nxv32i8(<vscale x 16 x half> %val, half* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv16f16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv4r.v v28, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v28
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv16f16.nxv32i8(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 32 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv16f16_nxv32i8(<vscale x 16 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv16f16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv4r.v v28, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v28, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv16f16.nxv32i8(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv16f16.nxv16i32(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 16 x i32>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv16f16.nxv16i32(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 16 x i32>, <vscale x 16 x i1>, i64)
+
+define void @test_vsxseg2_nxv16f16_nxv16i32(<vscale x 16 x half> %val, half* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv16f16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv16f16.nxv16i32(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 16 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv16f16_nxv16i32(<vscale x 16 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv16f16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv16f16.nxv16i32(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv16f16.nxv2i16(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 2 x i16>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv16f16.nxv2i16(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 2 x i16>, <vscale x 16 x i1>, i64)
+
+define void @test_vsxseg2_nxv16f16_nxv2i16(<vscale x 16 x half> %val, half* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv16f16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv1r.v v25, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv16f16.nxv2i16(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 2 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv16f16_nxv2i16(<vscale x 16 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv16f16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv1r.v v25, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv16f16.nxv2i16(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv16f16.nxv2i64(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 2 x i64>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv16f16.nxv2i64(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 2 x i64>, <vscale x 16 x i1>, i64)
+
+define void @test_vsxseg2_nxv16f16_nxv2i64(<vscale x 16 x half> %val, half* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv16f16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv2r.v v26, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v26
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv16f16.nxv2i64(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 2 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv16f16_nxv2i64(<vscale x 16 x half> %val, half* %base, <vscale x 2 x i64> %index, <vscale x 16 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv16f16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv2r.v v26, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v26, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv16f16.nxv2i64(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 2 x i64> %index, <vscale x 16 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv4f64.nxv16i16(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 16 x i16>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv4f64.nxv16i16(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 16 x i16>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg2_nxv4f64_nxv16i16(<vscale x 4 x double> %val, double* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv4f64_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv4r.v v28, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v28
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv4f64.nxv16i16(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 16 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv4f64_nxv16i16(<vscale x 4 x double> %val, double* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv4f64_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv4r.v v28, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v28, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv4f64.nxv16i16(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv4f64.nxv32i16(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 32 x i16>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv4f64.nxv32i16(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 32 x i16>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg2_nxv4f64_nxv32i16(<vscale x 4 x double> %val, double* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv4f64_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e64,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv4f64.nxv32i16(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 32 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv4f64_nxv32i16(<vscale x 4 x double> %val, double* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv4f64_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e64,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv4f64.nxv32i16(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv4f64.nxv4i32(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 4 x i32>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv4f64.nxv4i32(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 4 x i32>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg2_nxv4f64_nxv4i32(<vscale x 4 x double> %val, double* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv4f64_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv2r.v v26, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v26
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv4f64.nxv4i32(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 4 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv4f64_nxv4i32(<vscale x 4 x double> %val, double* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv4f64_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv2r.v v26, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v26, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv4f64.nxv4i32(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv4f64.nxv16i8(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 16 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv4f64.nxv16i8(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 16 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg2_nxv4f64_nxv16i8(<vscale x 4 x double> %val, double* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv4f64_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv2r.v v26, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v26
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv4f64.nxv16i8(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 16 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv4f64_nxv16i8(<vscale x 4 x double> %val, double* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv4f64_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv2r.v v26, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v26, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv4f64.nxv16i8(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv4f64.nxv1i64(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv4f64.nxv1i64(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 1 x i64>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg2_nxv4f64_nxv1i64(<vscale x 4 x double> %val, double* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv4f64_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv1r.v v25, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv4f64.nxv1i64(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 1 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv4f64_nxv1i64(<vscale x 4 x double> %val, double* %base, <vscale x 1 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv4f64_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv1r.v v25, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv4f64.nxv1i64(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 1 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv4f64.nxv1i32(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv4f64.nxv1i32(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 1 x i32>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg2_nxv4f64_nxv1i32(<vscale x 4 x double> %val, double* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv4f64_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv1r.v v25, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv4f64.nxv1i32(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 1 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv4f64_nxv1i32(<vscale x 4 x double> %val, double* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv4f64_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv1r.v v25, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv4f64.nxv1i32(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv4f64.nxv8i16(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 8 x i16>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv4f64.nxv8i16(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 8 x i16>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg2_nxv4f64_nxv8i16(<vscale x 4 x double> %val, double* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv4f64_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv2r.v v26, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v26
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv4f64.nxv8i16(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 8 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv4f64_nxv8i16(<vscale x 4 x double> %val, double* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv4f64_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv2r.v v26, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v26, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv4f64.nxv8i16(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv4f64.nxv4i8(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 4 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv4f64.nxv4i8(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 4 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg2_nxv4f64_nxv4i8(<vscale x 4 x double> %val, double* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv4f64_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv1r.v v25, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv4f64.nxv4i8(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 4 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv4f64_nxv4i8(<vscale x 4 x double> %val, double* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv4f64_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv1r.v v25, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv4f64.nxv4i8(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv4f64.nxv1i16(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv4f64.nxv1i16(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 1 x i16>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg2_nxv4f64_nxv1i16(<vscale x 4 x double> %val, double* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv4f64_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv1r.v v25, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv4f64.nxv1i16(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 1 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv4f64_nxv1i16(<vscale x 4 x double> %val, double* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv4f64_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv1r.v v25, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv4f64.nxv1i16(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv4f64.nxv2i32(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 2 x i32>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv4f64.nxv2i32(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 2 x i32>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg2_nxv4f64_nxv2i32(<vscale x 4 x double> %val, double* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv4f64_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv1r.v v25, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv4f64.nxv2i32(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 2 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv4f64_nxv2i32(<vscale x 4 x double> %val, double* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv4f64_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv1r.v v25, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv4f64.nxv2i32(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv4f64.nxv8i8(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 8 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv4f64.nxv8i8(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 8 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg2_nxv4f64_nxv8i8(<vscale x 4 x double> %val, double* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv4f64_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv1r.v v25, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv4f64.nxv8i8(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 8 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv4f64_nxv8i8(<vscale x 4 x double> %val, double* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv4f64_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv1r.v v25, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv4f64.nxv8i8(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv4f64.nxv4i64(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 4 x i64>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv4f64.nxv4i64(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 4 x i64>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg2_nxv4f64_nxv4i64(<vscale x 4 x double> %val, double* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv4f64_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv4r.v v28, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v28
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv4f64.nxv4i64(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 4 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv4f64_nxv4i64(<vscale x 4 x double> %val, double* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv4f64_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv4r.v v28, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v28, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv4f64.nxv4i64(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv4f64.nxv64i8(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 64 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv4f64.nxv64i8(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 64 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg2_nxv4f64_nxv64i8(<vscale x 4 x double> %val, double* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv4f64_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e64,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv4f64.nxv64i8(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 64 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv4f64_nxv64i8(<vscale x 4 x double> %val, double* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv4f64_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e64,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv4f64.nxv64i8(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv4f64.nxv4i16(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 4 x i16>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv4f64.nxv4i16(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 4 x i16>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg2_nxv4f64_nxv4i16(<vscale x 4 x double> %val, double* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv4f64_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv1r.v v25, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv4f64.nxv4i16(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 4 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv4f64_nxv4i16(<vscale x 4 x double> %val, double* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv4f64_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv1r.v v25, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv4f64.nxv4i16(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv4f64.nxv8i64(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 8 x i64>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv4f64.nxv8i64(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 8 x i64>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg2_nxv4f64_nxv8i64(<vscale x 4 x double> %val, double* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv4f64_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e64,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv4f64.nxv8i64(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 8 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv4f64_nxv8i64(<vscale x 4 x double> %val, double* %base, <vscale x 8 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv4f64_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e64,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv4f64.nxv8i64(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 8 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv4f64.nxv1i8(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv4f64.nxv1i8(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 1 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg2_nxv4f64_nxv1i8(<vscale x 4 x double> %val, double* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv4f64_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv1r.v v25, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv4f64.nxv1i8(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 1 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv4f64_nxv1i8(<vscale x 4 x double> %val, double* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv4f64_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv1r.v v25, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv4f64.nxv1i8(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv4f64.nxv2i8(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 2 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv4f64.nxv2i8(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 2 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg2_nxv4f64_nxv2i8(<vscale x 4 x double> %val, double* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv4f64_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv1r.v v25, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv4f64.nxv2i8(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 2 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv4f64_nxv2i8(<vscale x 4 x double> %val, double* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv4f64_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv1r.v v25, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv4f64.nxv2i8(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv4f64.nxv8i32(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 8 x i32>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv4f64.nxv8i32(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 8 x i32>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg2_nxv4f64_nxv8i32(<vscale x 4 x double> %val, double* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv4f64_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv4r.v v28, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v28
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv4f64.nxv8i32(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 8 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv4f64_nxv8i32(<vscale x 4 x double> %val, double* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv4f64_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv4r.v v28, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v28, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv4f64.nxv8i32(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv4f64.nxv32i8(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 32 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv4f64.nxv32i8(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 32 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg2_nxv4f64_nxv32i8(<vscale x 4 x double> %val, double* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv4f64_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv4r.v v28, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v28
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv4f64.nxv32i8(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 32 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv4f64_nxv32i8(<vscale x 4 x double> %val, double* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv4f64_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv4r.v v28, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v28, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv4f64.nxv32i8(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv4f64.nxv16i32(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 16 x i32>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv4f64.nxv16i32(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 16 x i32>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg2_nxv4f64_nxv16i32(<vscale x 4 x double> %val, double* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv4f64_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e64,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv4f64.nxv16i32(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 16 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv4f64_nxv16i32(<vscale x 4 x double> %val, double* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv4f64_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e64,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv4f64.nxv16i32(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv4f64.nxv2i16(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 2 x i16>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv4f64.nxv2i16(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 2 x i16>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg2_nxv4f64_nxv2i16(<vscale x 4 x double> %val, double* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv4f64_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv1r.v v25, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv4f64.nxv2i16(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 2 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv4f64_nxv2i16(<vscale x 4 x double> %val, double* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv4f64_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv1r.v v25, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv4f64.nxv2i16(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv4f64.nxv2i64(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 2 x i64>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv4f64.nxv2i64(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 2 x i64>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg2_nxv4f64_nxv2i64(<vscale x 4 x double> %val, double* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv4f64_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv2r.v v26, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v26
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv4f64.nxv2i64(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 2 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv4f64_nxv2i64(<vscale x 4 x double> %val, double* %base, <vscale x 2 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv4f64_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv2r.v v26, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v26, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv4f64.nxv2i64(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 2 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv1f64.nxv16i16(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i16>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv1f64.nxv16i16(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg2_nxv1f64_nxv16i16(<vscale x 1 x double> %val, double* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv1f64_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv1f64.nxv16i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 16 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv1f64_nxv16i16(<vscale x 1 x double> %val, double* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv1f64_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv1f64.nxv16i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv1f64.nxv32i16(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 32 x i16>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv1f64.nxv32i16(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 32 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg2_nxv1f64_nxv32i16(<vscale x 1 x double> %val, double* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv1f64_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a2, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv1f64.nxv32i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 32 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv1f64_nxv32i16(<vscale x 1 x double> %val, double* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv1f64_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a2, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv1f64.nxv32i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv1f64.nxv4i32(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i32>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv1f64.nxv4i32(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg2_nxv1f64_nxv4i32(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv1f64_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv1f64.nxv4i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv1f64_nxv4i32(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv1f64_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv1f64.nxv4i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv1f64.nxv16i8(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv1f64.nxv16i8(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg2_nxv1f64_nxv16i8(<vscale x 1 x double> %val, double* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv1f64_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv1f64.nxv16i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 16 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv1f64_nxv16i8(<vscale x 1 x double> %val, double* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv1f64_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv1f64.nxv16i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv1f64.nxv1i64(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv1f64.nxv1i64(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg2_nxv1f64_nxv1i64(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv1f64_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv1f64.nxv1i64(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv1f64_nxv1i64(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv1f64_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv1f64.nxv1i64(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv1f64.nxv1i32(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv1f64.nxv1i32(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg2_nxv1f64_nxv1i32(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv1f64_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv1f64.nxv1i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv1f64_nxv1i32(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv1f64_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv1f64.nxv1i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv1f64.nxv8i16(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i16>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv1f64.nxv8i16(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg2_nxv1f64_nxv8i16(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv1f64_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv1f64.nxv8i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv1f64_nxv8i16(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv1f64_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv1f64.nxv8i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv1f64.nxv4i8(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv1f64.nxv4i8(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg2_nxv1f64_nxv4i8(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv1f64_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv1f64.nxv4i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv1f64_nxv4i8(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv1f64_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv1f64.nxv4i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv1f64.nxv1i16(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv1f64.nxv1i16(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg2_nxv1f64_nxv1i16(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv1f64_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv1f64.nxv1i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv1f64_nxv1i16(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv1f64_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv1f64.nxv1i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv1f64.nxv2i32(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i32>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv1f64.nxv2i32(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg2_nxv1f64_nxv2i32(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv1f64_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv1f64.nxv2i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv1f64_nxv2i32(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv1f64_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv1f64.nxv2i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv1f64.nxv8i8(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv1f64.nxv8i8(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg2_nxv1f64_nxv8i8(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv1f64_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv1f64.nxv8i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv1f64_nxv8i8(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv1f64_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv1f64.nxv8i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv1f64.nxv4i64(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i64>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv1f64.nxv4i64(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg2_nxv1f64_nxv4i64(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv1f64_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv1f64.nxv4i64(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv1f64_nxv4i64(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv1f64_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv1f64.nxv4i64(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv1f64.nxv64i8(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 64 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv1f64.nxv64i8(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 64 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg2_nxv1f64_nxv64i8(<vscale x 1 x double> %val, double* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv1f64_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a2, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv1f64.nxv64i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 64 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv1f64_nxv64i8(<vscale x 1 x double> %val, double* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv1f64_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a2, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv1f64.nxv64i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv1f64.nxv4i16(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i16>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv1f64.nxv4i16(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg2_nxv1f64_nxv4i16(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv1f64_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv1f64.nxv4i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv1f64_nxv4i16(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv1f64_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv1f64.nxv4i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv1f64.nxv8i64(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i64>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv1f64.nxv8i64(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg2_nxv1f64_nxv8i64(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv1f64_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a2, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv1f64.nxv8i64(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv1f64_nxv8i64(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv1f64_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a2, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv1f64.nxv8i64(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv1f64.nxv1i8(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv1f64.nxv1i8(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg2_nxv1f64_nxv1i8(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv1f64_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv1f64.nxv1i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv1f64_nxv1i8(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv1f64_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv1f64.nxv1i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv1f64.nxv2i8(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv1f64.nxv2i8(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg2_nxv1f64_nxv2i8(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv1f64_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv1f64.nxv2i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv1f64_nxv2i8(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv1f64_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv1f64.nxv2i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv1f64.nxv8i32(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i32>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv1f64.nxv8i32(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg2_nxv1f64_nxv8i32(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv1f64_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv1f64.nxv8i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv1f64_nxv8i32(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv1f64_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv1f64.nxv8i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv1f64.nxv32i8(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 32 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv1f64.nxv32i8(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 32 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg2_nxv1f64_nxv32i8(<vscale x 1 x double> %val, double* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv1f64_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv1f64.nxv32i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 32 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv1f64_nxv32i8(<vscale x 1 x double> %val, double* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv1f64_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv1f64.nxv32i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv1f64.nxv16i32(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i32>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv1f64.nxv16i32(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg2_nxv1f64_nxv16i32(<vscale x 1 x double> %val, double* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv1f64_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a2, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv1f64.nxv16i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 16 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv1f64_nxv16i32(<vscale x 1 x double> %val, double* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv1f64_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a2, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv1f64.nxv16i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv1f64.nxv2i16(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i16>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv1f64.nxv2i16(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg2_nxv1f64_nxv2i16(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv1f64_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv1f64.nxv2i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv1f64_nxv2i16(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv1f64_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv1f64.nxv2i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv1f64.nxv2i64(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i64>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv1f64.nxv2i64(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg2_nxv1f64_nxv2i64(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv1f64_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv1f64.nxv2i64(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv1f64_nxv2i64(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv1f64_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv1f64.nxv2i64(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv1f64.nxv16i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i16>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv1f64.nxv16i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg3_nxv1f64_nxv16i16(<vscale x 1 x double> %val, double* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv1f64_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv1f64.nxv16i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 16 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv1f64_nxv16i16(<vscale x 1 x double> %val, double* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv1f64_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv1f64.nxv16i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv1f64.nxv32i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 32 x i16>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv1f64.nxv32i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 32 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg3_nxv1f64_nxv32i16(<vscale x 1 x double> %val, double* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv1f64_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a2, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv1f64.nxv32i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 32 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv1f64_nxv32i16(<vscale x 1 x double> %val, double* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv1f64_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a2, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv1f64.nxv32i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv1f64.nxv4i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i32>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv1f64.nxv4i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg3_nxv1f64_nxv4i32(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv1f64_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv1f64.nxv4i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv1f64_nxv4i32(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv1f64_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv1f64.nxv4i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv1f64.nxv16i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i8>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv1f64.nxv16i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg3_nxv1f64_nxv16i8(<vscale x 1 x double> %val, double* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv1f64_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv1f64.nxv16i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 16 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv1f64_nxv16i8(<vscale x 1 x double> %val, double* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv1f64_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv1f64.nxv16i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv1f64.nxv1i64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv1f64.nxv1i64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg3_nxv1f64_nxv1i64(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv1f64_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei64.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv1f64.nxv1i64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv1f64_nxv1i64(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv1f64_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei64.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv1f64.nxv1i64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv1f64.nxv1i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv1f64.nxv1i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg3_nxv1f64_nxv1i32(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv1f64_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv1f64.nxv1i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv1f64_nxv1i32(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv1f64_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv1f64.nxv1i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv1f64.nxv8i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i16>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv1f64.nxv8i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg3_nxv1f64_nxv8i16(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv1f64_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv1f64.nxv8i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv1f64_nxv8i16(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv1f64_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv1f64.nxv8i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv1f64.nxv4i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i8>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv1f64.nxv4i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg3_nxv1f64_nxv4i8(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv1f64_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv1f64.nxv4i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv1f64_nxv4i8(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv1f64_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv1f64.nxv4i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv1f64.nxv1i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv1f64.nxv1i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg3_nxv1f64_nxv1i16(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv1f64_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv1f64.nxv1i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv1f64_nxv1i16(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv1f64_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv1f64.nxv1i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv1f64.nxv2i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i32>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv1f64.nxv2i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg3_nxv1f64_nxv2i32(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv1f64_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv1f64.nxv2i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv1f64_nxv2i32(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv1f64_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv1f64.nxv2i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv1f64.nxv8i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i8>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv1f64.nxv8i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg3_nxv1f64_nxv8i8(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv1f64_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv1f64.nxv8i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv1f64_nxv8i8(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv1f64_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv1f64.nxv8i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv1f64.nxv4i64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i64>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv1f64.nxv4i64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg3_nxv1f64_nxv4i64(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv1f64_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei64.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv1f64.nxv4i64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv1f64_nxv4i64(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv1f64_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei64.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv1f64.nxv4i64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv1f64.nxv64i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 64 x i8>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv1f64.nxv64i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 64 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg3_nxv1f64_nxv64i8(<vscale x 1 x double> %val, double* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv1f64_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a2, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv1f64.nxv64i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 64 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv1f64_nxv64i8(<vscale x 1 x double> %val, double* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv1f64_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a2, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv1f64.nxv64i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv1f64.nxv4i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i16>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv1f64.nxv4i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg3_nxv1f64_nxv4i16(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv1f64_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv1f64.nxv4i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv1f64_nxv4i16(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv1f64_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv1f64.nxv4i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv1f64.nxv8i64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i64>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv1f64.nxv8i64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg3_nxv1f64_nxv8i64(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv1f64_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a2, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei64.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv1f64.nxv8i64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv1f64_nxv8i64(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv1f64_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a2, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei64.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv1f64.nxv8i64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv1f64.nxv1i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv1f64.nxv1i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg3_nxv1f64_nxv1i8(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv1f64_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv1f64.nxv1i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv1f64_nxv1i8(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv1f64_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv1f64.nxv1i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv1f64.nxv2i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i8>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv1f64.nxv2i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg3_nxv1f64_nxv2i8(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv1f64_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv1f64.nxv2i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv1f64_nxv2i8(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv1f64_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv1f64.nxv2i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv1f64.nxv8i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i32>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv1f64.nxv8i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg3_nxv1f64_nxv8i32(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv1f64_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv1f64.nxv8i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv1f64_nxv8i32(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv1f64_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv1f64.nxv8i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv1f64.nxv32i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 32 x i8>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv1f64.nxv32i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 32 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg3_nxv1f64_nxv32i8(<vscale x 1 x double> %val, double* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv1f64_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv1f64.nxv32i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 32 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv1f64_nxv32i8(<vscale x 1 x double> %val, double* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv1f64_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv1f64.nxv32i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv1f64.nxv16i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i32>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv1f64.nxv16i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg3_nxv1f64_nxv16i32(<vscale x 1 x double> %val, double* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv1f64_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a2, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv1f64.nxv16i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 16 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv1f64_nxv16i32(<vscale x 1 x double> %val, double* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv1f64_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a2, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv1f64.nxv16i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv1f64.nxv2i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i16>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv1f64.nxv2i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg3_nxv1f64_nxv2i16(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv1f64_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv1f64.nxv2i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv1f64_nxv2i16(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv1f64_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv1f64.nxv2i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv1f64.nxv2i64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i64>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv1f64.nxv2i64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg3_nxv1f64_nxv2i64(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv1f64_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei64.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv1f64.nxv2i64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv1f64_nxv2i64(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv1f64_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei64.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv1f64.nxv2i64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv1f64.nxv16i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i16>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv1f64.nxv16i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg4_nxv1f64_nxv16i16(<vscale x 1 x double> %val, double* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv1f64_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv1f64.nxv16i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 16 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv1f64_nxv16i16(<vscale x 1 x double> %val, double* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv1f64_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv1f64.nxv16i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv1f64.nxv32i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 32 x i16>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv1f64.nxv32i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 32 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg4_nxv1f64_nxv32i16(<vscale x 1 x double> %val, double* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv1f64_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a2, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv1f64.nxv32i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 32 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv1f64_nxv32i16(<vscale x 1 x double> %val, double* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv1f64_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a2, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv1f64.nxv32i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv1f64.nxv4i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i32>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv1f64.nxv4i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg4_nxv1f64_nxv4i32(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv1f64_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv1f64.nxv4i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv1f64_nxv4i32(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv1f64_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv1f64.nxv4i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv1f64.nxv16i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i8>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv1f64.nxv16i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg4_nxv1f64_nxv16i8(<vscale x 1 x double> %val, double* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv1f64_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv1f64.nxv16i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 16 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv1f64_nxv16i8(<vscale x 1 x double> %val, double* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv1f64_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv1f64.nxv16i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv1f64.nxv1i64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv1f64.nxv1i64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg4_nxv1f64_nxv1i64(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv1f64_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei64.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv1f64.nxv1i64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv1f64_nxv1i64(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv1f64_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei64.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv1f64.nxv1i64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv1f64.nxv1i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv1f64.nxv1i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg4_nxv1f64_nxv1i32(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv1f64_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv1f64.nxv1i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv1f64_nxv1i32(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv1f64_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv1f64.nxv1i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv1f64.nxv8i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i16>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv1f64.nxv8i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg4_nxv1f64_nxv8i16(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv1f64_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv1f64.nxv8i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv1f64_nxv8i16(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv1f64_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv1f64.nxv8i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv1f64.nxv4i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i8>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv1f64.nxv4i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg4_nxv1f64_nxv4i8(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv1f64_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv1f64.nxv4i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv1f64_nxv4i8(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv1f64_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv1f64.nxv4i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv1f64.nxv1i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv1f64.nxv1i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg4_nxv1f64_nxv1i16(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv1f64_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv1f64.nxv1i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv1f64_nxv1i16(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv1f64_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv1f64.nxv1i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv1f64.nxv2i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i32>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv1f64.nxv2i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg4_nxv1f64_nxv2i32(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv1f64_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv1f64.nxv2i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv1f64_nxv2i32(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv1f64_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv1f64.nxv2i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv1f64.nxv8i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i8>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv1f64.nxv8i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg4_nxv1f64_nxv8i8(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv1f64_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv1f64.nxv8i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv1f64_nxv8i8(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv1f64_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv1f64.nxv8i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv1f64.nxv4i64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i64>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv1f64.nxv4i64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg4_nxv1f64_nxv4i64(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv1f64_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei64.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv1f64.nxv4i64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv1f64_nxv4i64(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv1f64_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei64.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv1f64.nxv4i64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv1f64.nxv64i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 64 x i8>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv1f64.nxv64i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 64 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg4_nxv1f64_nxv64i8(<vscale x 1 x double> %val, double* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv1f64_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a2, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv1f64.nxv64i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 64 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv1f64_nxv64i8(<vscale x 1 x double> %val, double* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv1f64_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a2, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv1f64.nxv64i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv1f64.nxv4i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i16>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv1f64.nxv4i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg4_nxv1f64_nxv4i16(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv1f64_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv1f64.nxv4i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv1f64_nxv4i16(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv1f64_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv1f64.nxv4i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv1f64.nxv8i64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i64>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv1f64.nxv8i64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg4_nxv1f64_nxv8i64(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv1f64_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a2, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei64.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv1f64.nxv8i64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv1f64_nxv8i64(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv1f64_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a2, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei64.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv1f64.nxv8i64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv1f64.nxv1i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv1f64.nxv1i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg4_nxv1f64_nxv1i8(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv1f64_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv1f64.nxv1i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv1f64_nxv1i8(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv1f64_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv1f64.nxv1i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv1f64.nxv2i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i8>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv1f64.nxv2i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg4_nxv1f64_nxv2i8(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv1f64_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv1f64.nxv2i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv1f64_nxv2i8(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv1f64_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv1f64.nxv2i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv1f64.nxv8i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i32>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv1f64.nxv8i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg4_nxv1f64_nxv8i32(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv1f64_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv1f64.nxv8i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv1f64_nxv8i32(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv1f64_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv1f64.nxv8i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv1f64.nxv32i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 32 x i8>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv1f64.nxv32i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 32 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg4_nxv1f64_nxv32i8(<vscale x 1 x double> %val, double* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv1f64_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv1f64.nxv32i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 32 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv1f64_nxv32i8(<vscale x 1 x double> %val, double* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv1f64_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv1f64.nxv32i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv1f64.nxv16i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i32>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv1f64.nxv16i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg4_nxv1f64_nxv16i32(<vscale x 1 x double> %val, double* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv1f64_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a2, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv1f64.nxv16i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 16 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv1f64_nxv16i32(<vscale x 1 x double> %val, double* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv1f64_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a2, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv1f64.nxv16i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv1f64.nxv2i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i16>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv1f64.nxv2i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg4_nxv1f64_nxv2i16(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv1f64_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv1f64.nxv2i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv1f64_nxv2i16(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv1f64_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv1f64.nxv2i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv1f64.nxv2i64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i64>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv1f64.nxv2i64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg4_nxv1f64_nxv2i64(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv1f64_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei64.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv1f64.nxv2i64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv1f64_nxv2i64(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv1f64_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei64.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv1f64.nxv2i64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv1f64.nxv16i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i16>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv1f64.nxv16i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg5_nxv1f64_nxv16i16(<vscale x 1 x double> %val, double* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv1f64_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv1f64.nxv16i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 16 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv1f64_nxv16i16(<vscale x 1 x double> %val, double* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv1f64_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv1f64.nxv16i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv1f64.nxv32i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 32 x i16>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv1f64.nxv32i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 32 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg5_nxv1f64_nxv32i16(<vscale x 1 x double> %val, double* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv1f64_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv1f64.nxv32i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 32 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv1f64_nxv32i16(<vscale x 1 x double> %val, double* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv1f64_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv1f64.nxv32i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv1f64.nxv4i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i32>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv1f64.nxv4i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg5_nxv1f64_nxv4i32(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv1f64_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei32.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv1f64.nxv4i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv1f64_nxv4i32(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv1f64_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei32.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv1f64.nxv4i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv1f64.nxv16i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i8>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv1f64.nxv16i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg5_nxv1f64_nxv16i8(<vscale x 1 x double> %val, double* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv1f64_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv1f64.nxv16i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 16 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv1f64_nxv16i8(<vscale x 1 x double> %val, double* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv1f64_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv1f64.nxv16i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv1f64.nxv1i64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv1f64.nxv1i64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg5_nxv1f64_nxv1i64(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv1f64_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei64.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv1f64.nxv1i64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv1f64_nxv1i64(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv1f64_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei64.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv1f64.nxv1i64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv1f64.nxv1i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv1f64.nxv1i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg5_nxv1f64_nxv1i32(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv1f64_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv1f64.nxv1i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv1f64_nxv1i32(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv1f64_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv1f64.nxv1i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv1f64.nxv8i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i16>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv1f64.nxv8i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg5_nxv1f64_nxv8i16(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv1f64_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv1f64.nxv8i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv1f64_nxv8i16(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv1f64_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv1f64.nxv8i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv1f64.nxv4i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i8>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv1f64.nxv4i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg5_nxv1f64_nxv4i8(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv1f64_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv1f64.nxv4i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv1f64_nxv4i8(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv1f64_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv1f64.nxv4i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv1f64.nxv1i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv1f64.nxv1i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg5_nxv1f64_nxv1i16(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv1f64_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv1f64.nxv1i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv1f64_nxv1i16(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv1f64_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv1f64.nxv1i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv1f64.nxv2i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i32>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv1f64.nxv2i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg5_nxv1f64_nxv2i32(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv1f64_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv1f64.nxv2i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv1f64_nxv2i32(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv1f64_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv1f64.nxv2i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv1f64.nxv8i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i8>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv1f64.nxv8i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg5_nxv1f64_nxv8i8(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv1f64_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv1f64.nxv8i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv1f64_nxv8i8(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv1f64_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv1f64.nxv8i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv1f64.nxv4i64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i64>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv1f64.nxv4i64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg5_nxv1f64_nxv4i64(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv1f64_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei64.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv1f64.nxv4i64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv1f64_nxv4i64(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv1f64_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei64.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv1f64.nxv4i64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv1f64.nxv64i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 64 x i8>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv1f64.nxv64i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 64 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg5_nxv1f64_nxv64i8(<vscale x 1 x double> %val, double* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv1f64_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv1f64.nxv64i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 64 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv1f64_nxv64i8(<vscale x 1 x double> %val, double* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv1f64_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv1f64.nxv64i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv1f64.nxv4i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i16>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv1f64.nxv4i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg5_nxv1f64_nxv4i16(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv1f64_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv1f64.nxv4i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv1f64_nxv4i16(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv1f64_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv1f64.nxv4i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv1f64.nxv8i64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i64>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv1f64.nxv8i64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg5_nxv1f64_nxv8i64(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv1f64_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei64.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv1f64.nxv8i64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv1f64_nxv8i64(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv1f64_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei64.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv1f64.nxv8i64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv1f64.nxv1i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv1f64.nxv1i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg5_nxv1f64_nxv1i8(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv1f64_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv1f64.nxv1i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv1f64_nxv1i8(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv1f64_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv1f64.nxv1i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv1f64.nxv2i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i8>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv1f64.nxv2i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg5_nxv1f64_nxv2i8(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv1f64_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv1f64.nxv2i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv1f64_nxv2i8(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv1f64_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv1f64.nxv2i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv1f64.nxv8i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i32>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv1f64.nxv8i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg5_nxv1f64_nxv8i32(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv1f64_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei32.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv1f64.nxv8i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv1f64_nxv8i32(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv1f64_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei32.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv1f64.nxv8i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv1f64.nxv32i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 32 x i8>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv1f64.nxv32i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 32 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg5_nxv1f64_nxv32i8(<vscale x 1 x double> %val, double* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv1f64_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv1f64.nxv32i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 32 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv1f64_nxv32i8(<vscale x 1 x double> %val, double* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv1f64_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv1f64.nxv32i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv1f64.nxv16i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i32>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv1f64.nxv16i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg5_nxv1f64_nxv16i32(<vscale x 1 x double> %val, double* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv1f64_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei32.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv1f64.nxv16i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 16 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv1f64_nxv16i32(<vscale x 1 x double> %val, double* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv1f64_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei32.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv1f64.nxv16i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv1f64.nxv2i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i16>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv1f64.nxv2i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg5_nxv1f64_nxv2i16(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv1f64_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv1f64.nxv2i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv1f64_nxv2i16(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv1f64_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv1f64.nxv2i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv1f64.nxv2i64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i64>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv1f64.nxv2i64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg5_nxv1f64_nxv2i64(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv1f64_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei64.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv1f64.nxv2i64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv1f64_nxv2i64(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv1f64_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei64.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv1f64.nxv2i64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv1f64.nxv16i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i16>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv1f64.nxv16i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg6_nxv1f64_nxv16i16(<vscale x 1 x double> %val, double* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv1f64_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv1f64.nxv16i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 16 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv1f64_nxv16i16(<vscale x 1 x double> %val, double* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv1f64_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv1f64.nxv16i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv1f64.nxv32i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 32 x i16>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv1f64.nxv32i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 32 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg6_nxv1f64_nxv32i16(<vscale x 1 x double> %val, double* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv1f64_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vsetvli a1, a2, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv1f64.nxv32i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 32 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv1f64_nxv32i16(<vscale x 1 x double> %val, double* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv1f64_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vsetvli a1, a2, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv1f64.nxv32i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv1f64.nxv4i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i32>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv1f64.nxv4i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg6_nxv1f64_nxv4i32(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv1f64_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei32.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv1f64.nxv4i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv1f64_nxv4i32(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv1f64_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei32.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv1f64.nxv4i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv1f64.nxv16i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i8>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv1f64.nxv16i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg6_nxv1f64_nxv16i8(<vscale x 1 x double> %val, double* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv1f64_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv1f64.nxv16i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 16 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv1f64_nxv16i8(<vscale x 1 x double> %val, double* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv1f64_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv1f64.nxv16i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv1f64.nxv1i64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv1f64.nxv1i64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg6_nxv1f64_nxv1i64(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv1f64_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei64.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv1f64.nxv1i64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv1f64_nxv1i64(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv1f64_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei64.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv1f64.nxv1i64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv1f64.nxv1i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv1f64.nxv1i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg6_nxv1f64_nxv1i32(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv1f64_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv1f64.nxv1i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv1f64_nxv1i32(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv1f64_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv1f64.nxv1i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv1f64.nxv8i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i16>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv1f64.nxv8i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg6_nxv1f64_nxv8i16(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv1f64_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv1f64.nxv8i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv1f64_nxv8i16(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv1f64_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv1f64.nxv8i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv1f64.nxv4i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i8>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv1f64.nxv4i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg6_nxv1f64_nxv4i8(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv1f64_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv1f64.nxv4i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv1f64_nxv4i8(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv1f64_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv1f64.nxv4i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv1f64.nxv1i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv1f64.nxv1i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg6_nxv1f64_nxv1i16(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv1f64_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv1f64.nxv1i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv1f64_nxv1i16(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv1f64_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv1f64.nxv1i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv1f64.nxv2i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i32>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv1f64.nxv2i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg6_nxv1f64_nxv2i32(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv1f64_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv1f64.nxv2i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv1f64_nxv2i32(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv1f64_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv1f64.nxv2i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv1f64.nxv8i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i8>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv1f64.nxv8i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg6_nxv1f64_nxv8i8(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv1f64_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv1f64.nxv8i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv1f64_nxv8i8(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv1f64_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv1f64.nxv8i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv1f64.nxv4i64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i64>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv1f64.nxv4i64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg6_nxv1f64_nxv4i64(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv1f64_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei64.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv1f64.nxv4i64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv1f64_nxv4i64(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv1f64_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei64.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv1f64.nxv4i64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv1f64.nxv64i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 64 x i8>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv1f64.nxv64i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 64 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg6_nxv1f64_nxv64i8(<vscale x 1 x double> %val, double* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv1f64_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vsetvli a1, a2, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv1f64.nxv64i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 64 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv1f64_nxv64i8(<vscale x 1 x double> %val, double* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv1f64_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vsetvli a1, a2, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv1f64.nxv64i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv1f64.nxv4i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i16>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv1f64.nxv4i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg6_nxv1f64_nxv4i16(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv1f64_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv1f64.nxv4i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv1f64_nxv4i16(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv1f64_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv1f64.nxv4i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv1f64.nxv8i64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i64>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv1f64.nxv8i64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg6_nxv1f64_nxv8i64(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv1f64_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vsetvli a1, a2, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei64.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv1f64.nxv8i64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv1f64_nxv8i64(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv1f64_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vsetvli a1, a2, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei64.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv1f64.nxv8i64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv1f64.nxv1i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv1f64.nxv1i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg6_nxv1f64_nxv1i8(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv1f64_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv1f64.nxv1i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv1f64_nxv1i8(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv1f64_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv1f64.nxv1i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv1f64.nxv2i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i8>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv1f64.nxv2i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg6_nxv1f64_nxv2i8(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv1f64_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv1f64.nxv2i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv1f64_nxv2i8(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv1f64_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv1f64.nxv2i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv1f64.nxv8i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i32>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv1f64.nxv8i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg6_nxv1f64_nxv8i32(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv1f64_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei32.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv1f64.nxv8i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv1f64_nxv8i32(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv1f64_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei32.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv1f64.nxv8i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv1f64.nxv32i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 32 x i8>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv1f64.nxv32i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 32 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg6_nxv1f64_nxv32i8(<vscale x 1 x double> %val, double* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv1f64_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv1f64.nxv32i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 32 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv1f64_nxv32i8(<vscale x 1 x double> %val, double* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv1f64_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv1f64.nxv32i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv1f64.nxv16i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i32>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv1f64.nxv16i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg6_nxv1f64_nxv16i32(<vscale x 1 x double> %val, double* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv1f64_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vsetvli a1, a2, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei32.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv1f64.nxv16i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 16 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv1f64_nxv16i32(<vscale x 1 x double> %val, double* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv1f64_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vsetvli a1, a2, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei32.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv1f64.nxv16i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv1f64.nxv2i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i16>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv1f64.nxv2i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg6_nxv1f64_nxv2i16(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv1f64_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv1f64.nxv2i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv1f64_nxv2i16(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv1f64_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv1f64.nxv2i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv1f64.nxv2i64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i64>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv1f64.nxv2i64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg6_nxv1f64_nxv2i64(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv1f64_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei64.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv1f64.nxv2i64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv1f64_nxv2i64(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv1f64_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei64.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv1f64.nxv2i64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv1f64.nxv16i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i16>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv1f64.nxv16i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg7_nxv1f64_nxv16i16(<vscale x 1 x double> %val, double* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv1f64_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv1f64.nxv16i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 16 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv1f64_nxv16i16(<vscale x 1 x double> %val, double* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv1f64_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv1f64.nxv16i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv1f64.nxv32i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 32 x i16>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv1f64.nxv32i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 32 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg7_nxv1f64_nxv32i16(<vscale x 1 x double> %val, double* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv1f64_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vsetvli a1, a2, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv1f64.nxv32i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 32 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv1f64_nxv32i16(<vscale x 1 x double> %val, double* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv1f64_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vsetvli a1, a2, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv1f64.nxv32i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv1f64.nxv4i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i32>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv1f64.nxv4i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg7_nxv1f64_nxv4i32(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv1f64_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei32.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv1f64.nxv4i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv1f64_nxv4i32(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv1f64_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei32.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv1f64.nxv4i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv1f64.nxv16i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i8>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv1f64.nxv16i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg7_nxv1f64_nxv16i8(<vscale x 1 x double> %val, double* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv1f64_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv1f64.nxv16i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 16 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv1f64_nxv16i8(<vscale x 1 x double> %val, double* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv1f64_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv1f64.nxv16i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv1f64.nxv1i64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv1f64.nxv1i64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg7_nxv1f64_nxv1i64(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv1f64_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei64.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv1f64.nxv1i64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv1f64_nxv1i64(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv1f64_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei64.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv1f64.nxv1i64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv1f64.nxv1i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv1f64.nxv1i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg7_nxv1f64_nxv1i32(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv1f64_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv1f64.nxv1i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv1f64_nxv1i32(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv1f64_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv1f64.nxv1i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv1f64.nxv8i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i16>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv1f64.nxv8i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg7_nxv1f64_nxv8i16(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv1f64_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv1f64.nxv8i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv1f64_nxv8i16(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv1f64_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv1f64.nxv8i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv1f64.nxv4i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i8>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv1f64.nxv4i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg7_nxv1f64_nxv4i8(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv1f64_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv1f64.nxv4i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv1f64_nxv4i8(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv1f64_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv1f64.nxv4i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv1f64.nxv1i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv1f64.nxv1i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg7_nxv1f64_nxv1i16(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv1f64_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv1f64.nxv1i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv1f64_nxv1i16(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv1f64_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv1f64.nxv1i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv1f64.nxv2i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i32>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv1f64.nxv2i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg7_nxv1f64_nxv2i32(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv1f64_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv1f64.nxv2i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv1f64_nxv2i32(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv1f64_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv1f64.nxv2i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv1f64.nxv8i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i8>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv1f64.nxv8i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg7_nxv1f64_nxv8i8(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv1f64_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv1f64.nxv8i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv1f64_nxv8i8(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv1f64_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv1f64.nxv8i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv1f64.nxv4i64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i64>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv1f64.nxv4i64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg7_nxv1f64_nxv4i64(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv1f64_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei64.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv1f64.nxv4i64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv1f64_nxv4i64(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv1f64_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei64.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv1f64.nxv4i64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv1f64.nxv64i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 64 x i8>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv1f64.nxv64i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 64 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg7_nxv1f64_nxv64i8(<vscale x 1 x double> %val, double* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv1f64_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vsetvli a1, a2, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv1f64.nxv64i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 64 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv1f64_nxv64i8(<vscale x 1 x double> %val, double* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv1f64_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vsetvli a1, a2, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv1f64.nxv64i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv1f64.nxv4i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i16>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv1f64.nxv4i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg7_nxv1f64_nxv4i16(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv1f64_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv1f64.nxv4i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv1f64_nxv4i16(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv1f64_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv1f64.nxv4i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv1f64.nxv8i64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i64>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv1f64.nxv8i64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg7_nxv1f64_nxv8i64(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv1f64_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vsetvli a1, a2, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei64.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv1f64.nxv8i64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv1f64_nxv8i64(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv1f64_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vsetvli a1, a2, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei64.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv1f64.nxv8i64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv1f64.nxv1i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv1f64.nxv1i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg7_nxv1f64_nxv1i8(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv1f64_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv1f64.nxv1i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv1f64_nxv1i8(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv1f64_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv1f64.nxv1i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv1f64.nxv2i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i8>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv1f64.nxv2i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg7_nxv1f64_nxv2i8(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv1f64_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv1f64.nxv2i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv1f64_nxv2i8(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv1f64_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv1f64.nxv2i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv1f64.nxv8i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i32>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv1f64.nxv8i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg7_nxv1f64_nxv8i32(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv1f64_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei32.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv1f64.nxv8i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv1f64_nxv8i32(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv1f64_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei32.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv1f64.nxv8i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv1f64.nxv32i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 32 x i8>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv1f64.nxv32i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 32 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg7_nxv1f64_nxv32i8(<vscale x 1 x double> %val, double* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv1f64_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv1f64.nxv32i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 32 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv1f64_nxv32i8(<vscale x 1 x double> %val, double* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv1f64_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv1f64.nxv32i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv1f64.nxv16i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i32>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv1f64.nxv16i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg7_nxv1f64_nxv16i32(<vscale x 1 x double> %val, double* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv1f64_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vsetvli a1, a2, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei32.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv1f64.nxv16i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 16 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv1f64_nxv16i32(<vscale x 1 x double> %val, double* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv1f64_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vsetvli a1, a2, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei32.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv1f64.nxv16i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv1f64.nxv2i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i16>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv1f64.nxv2i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg7_nxv1f64_nxv2i16(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv1f64_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv1f64.nxv2i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv1f64_nxv2i16(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv1f64_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv1f64.nxv2i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv1f64.nxv2i64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i64>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv1f64.nxv2i64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg7_nxv1f64_nxv2i64(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv1f64_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei64.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv1f64.nxv2i64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv1f64_nxv2i64(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv1f64_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei64.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv1f64.nxv2i64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv1f64.nxv16i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i16>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv1f64.nxv16i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg8_nxv1f64_nxv16i16(<vscale x 1 x double> %val, double* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv1f64_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv1f64.nxv16i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 16 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv1f64_nxv16i16(<vscale x 1 x double> %val, double* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv1f64_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv1f64.nxv16i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv1f64.nxv32i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 32 x i16>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv1f64.nxv32i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 32 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg8_nxv1f64_nxv32i16(<vscale x 1 x double> %val, double* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv1f64_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vmv1r.v v23, v16
+; CHECK-NEXT:    vsetvli a1, a2, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv1f64.nxv32i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 32 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv1f64_nxv32i16(<vscale x 1 x double> %val, double* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv1f64_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vmv1r.v v23, v16
+; CHECK-NEXT:    vsetvli a1, a2, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv1f64.nxv32i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv1f64.nxv4i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i32>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv1f64.nxv4i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg8_nxv1f64_nxv4i32(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv1f64_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei32.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv1f64.nxv4i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv1f64_nxv4i32(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv1f64_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei32.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv1f64.nxv4i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv1f64.nxv16i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i8>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv1f64.nxv16i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg8_nxv1f64_nxv16i8(<vscale x 1 x double> %val, double* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv1f64_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv1f64.nxv16i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 16 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv1f64_nxv16i8(<vscale x 1 x double> %val, double* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv1f64_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv1f64.nxv16i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv1f64.nxv1i64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv1f64.nxv1i64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg8_nxv1f64_nxv1i64(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv1f64_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei64.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv1f64.nxv1i64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv1f64_nxv1i64(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv1f64_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei64.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv1f64.nxv1i64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv1f64.nxv1i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv1f64.nxv1i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg8_nxv1f64_nxv1i32(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv1f64_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv1f64.nxv1i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv1f64_nxv1i32(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv1f64_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv1f64.nxv1i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv1f64.nxv8i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i16>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv1f64.nxv8i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg8_nxv1f64_nxv8i16(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv1f64_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv1f64.nxv8i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv1f64_nxv8i16(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv1f64_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv1f64.nxv8i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv1f64.nxv4i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i8>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv1f64.nxv4i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg8_nxv1f64_nxv4i8(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv1f64_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv1f64.nxv4i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv1f64_nxv4i8(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv1f64_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv1f64.nxv4i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv1f64.nxv1i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv1f64.nxv1i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg8_nxv1f64_nxv1i16(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv1f64_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv1f64.nxv1i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv1f64_nxv1i16(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv1f64_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv1f64.nxv1i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv1f64.nxv2i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i32>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv1f64.nxv2i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg8_nxv1f64_nxv2i32(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv1f64_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv1f64.nxv2i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv1f64_nxv2i32(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv1f64_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv1f64.nxv2i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv1f64.nxv8i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i8>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv1f64.nxv8i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg8_nxv1f64_nxv8i8(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv1f64_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv1f64.nxv8i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv1f64_nxv8i8(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv1f64_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv1f64.nxv8i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv1f64.nxv4i64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i64>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv1f64.nxv4i64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg8_nxv1f64_nxv4i64(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv1f64_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei64.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv1f64.nxv4i64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv1f64_nxv4i64(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv1f64_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei64.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv1f64.nxv4i64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv1f64.nxv64i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 64 x i8>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv1f64.nxv64i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 64 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg8_nxv1f64_nxv64i8(<vscale x 1 x double> %val, double* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv1f64_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vmv1r.v v23, v16
+; CHECK-NEXT:    vsetvli a1, a2, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv1f64.nxv64i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 64 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv1f64_nxv64i8(<vscale x 1 x double> %val, double* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv1f64_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vmv1r.v v23, v16
+; CHECK-NEXT:    vsetvli a1, a2, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv1f64.nxv64i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv1f64.nxv4i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i16>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv1f64.nxv4i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 4 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg8_nxv1f64_nxv4i16(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv1f64_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv1f64.nxv4i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv1f64_nxv4i16(<vscale x 1 x double> %val, double* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv1f64_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv1f64.nxv4i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv1f64.nxv8i64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i64>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv1f64.nxv8i64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg8_nxv1f64_nxv8i64(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv1f64_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vmv1r.v v23, v16
+; CHECK-NEXT:    vsetvli a1, a2, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei64.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv1f64.nxv8i64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv1f64_nxv8i64(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv1f64_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vmv1r.v v23, v16
+; CHECK-NEXT:    vsetvli a1, a2, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei64.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv1f64.nxv8i64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv1f64.nxv1i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv1f64.nxv1i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg8_nxv1f64_nxv1i8(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv1f64_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv1f64.nxv1i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv1f64_nxv1i8(<vscale x 1 x double> %val, double* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv1f64_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv1f64.nxv1i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv1f64.nxv2i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i8>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv1f64.nxv2i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg8_nxv1f64_nxv2i8(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv1f64_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv1f64.nxv2i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv1f64_nxv2i8(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv1f64_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv1f64.nxv2i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv1f64.nxv8i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i32>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv1f64.nxv8i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 8 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg8_nxv1f64_nxv8i32(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv1f64_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei32.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv1f64.nxv8i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv1f64_nxv8i32(<vscale x 1 x double> %val, double* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv1f64_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei32.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv1f64.nxv8i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv1f64.nxv32i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 32 x i8>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv1f64.nxv32i8(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 32 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg8_nxv1f64_nxv32i8(<vscale x 1 x double> %val, double* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv1f64_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv1f64.nxv32i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 32 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv1f64_nxv32i8(<vscale x 1 x double> %val, double* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv1f64_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv1f64.nxv32i8(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv1f64.nxv16i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i32>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv1f64.nxv16i32(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 16 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg8_nxv1f64_nxv16i32(<vscale x 1 x double> %val, double* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv1f64_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vmv1r.v v23, v16
+; CHECK-NEXT:    vsetvli a1, a2, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei32.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv1f64.nxv16i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 16 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv1f64_nxv16i32(<vscale x 1 x double> %val, double* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv1f64_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vmv1r.v v23, v16
+; CHECK-NEXT:    vsetvli a1, a2, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei32.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv1f64.nxv16i32(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv1f64.nxv2i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i16>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv1f64.nxv2i16(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg8_nxv1f64_nxv2i16(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv1f64_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv1f64.nxv2i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv1f64_nxv2i16(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv1f64_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv1f64.nxv2i16(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv1f64.nxv2i64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i64>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv1f64.nxv2i64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 2 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg8_nxv1f64_nxv2i64(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv1f64_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei64.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv1f64.nxv2i64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv1f64_nxv2i64(<vscale x 1 x double> %val, double* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv1f64_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei64.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv1f64.nxv2i64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv2f32.nxv16i16(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i16>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv2f32.nxv16i16(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg2_nxv2f32_nxv16i16(<vscale x 2 x float> %val, float* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv2f32_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv2f32.nxv16i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 16 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv2f32_nxv16i16(<vscale x 2 x float> %val, float* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv2f32_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv2f32.nxv16i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv2f32.nxv32i16(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 32 x i16>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv2f32.nxv32i16(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 32 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg2_nxv2f32_nxv32i16(<vscale x 2 x float> %val, float* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv2f32_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv2f32.nxv32i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 32 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv2f32_nxv32i16(<vscale x 2 x float> %val, float* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv2f32_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv2f32.nxv32i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv2f32.nxv4i32(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i32>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv2f32.nxv4i32(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg2_nxv2f32_nxv4i32(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv2f32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv2f32.nxv4i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv2f32_nxv4i32(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv2f32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv2f32.nxv4i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv2f32.nxv16i8(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv2f32.nxv16i8(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg2_nxv2f32_nxv16i8(<vscale x 2 x float> %val, float* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv2f32_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv2f32.nxv16i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 16 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv2f32_nxv16i8(<vscale x 2 x float> %val, float* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv2f32_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv2f32.nxv16i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv2f32.nxv1i64(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv2f32.nxv1i64(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i64>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg2_nxv2f32_nxv1i64(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv2f32_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv2f32.nxv1i64(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv2f32_nxv1i64(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv2f32_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv2f32.nxv1i64(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv2f32.nxv1i32(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv2f32.nxv1i32(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg2_nxv2f32_nxv1i32(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv2f32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv2f32.nxv1i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv2f32_nxv1i32(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv2f32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv2f32.nxv1i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv2f32.nxv8i16(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i16>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv2f32.nxv8i16(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg2_nxv2f32_nxv8i16(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv2f32_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv2f32.nxv8i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv2f32_nxv8i16(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv2f32_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv2f32.nxv8i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv2f32.nxv4i8(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv2f32.nxv4i8(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg2_nxv2f32_nxv4i8(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv2f32_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv2f32.nxv4i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv2f32_nxv4i8(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv2f32_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv2f32.nxv4i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv2f32.nxv1i16(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv2f32.nxv1i16(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg2_nxv2f32_nxv1i16(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv2f32_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv2f32.nxv1i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv2f32_nxv1i16(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv2f32_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv2f32.nxv1i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv2f32.nxv2i32(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i32>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv2f32.nxv2i32(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg2_nxv2f32_nxv2i32(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv2f32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv2f32.nxv2i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv2f32_nxv2i32(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv2f32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv2f32.nxv2i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv2f32.nxv8i8(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv2f32.nxv8i8(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg2_nxv2f32_nxv8i8(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv2f32_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv2f32.nxv8i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv2f32_nxv8i8(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv2f32_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv2f32.nxv8i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv2f32.nxv4i64(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i64>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv2f32.nxv4i64(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i64>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg2_nxv2f32_nxv4i64(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv2f32_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv2f32.nxv4i64(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv2f32_nxv4i64(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv2f32_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv2f32.nxv4i64(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv2f32.nxv64i8(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 64 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv2f32.nxv64i8(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 64 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg2_nxv2f32_nxv64i8(<vscale x 2 x float> %val, float* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv2f32_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv2f32.nxv64i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 64 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv2f32_nxv64i8(<vscale x 2 x float> %val, float* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv2f32_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv2f32.nxv64i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv2f32.nxv4i16(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i16>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv2f32.nxv4i16(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg2_nxv2f32_nxv4i16(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv2f32_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv2f32.nxv4i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv2f32_nxv4i16(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv2f32_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv2f32.nxv4i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv2f32.nxv8i64(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i64>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv2f32.nxv8i64(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i64>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg2_nxv2f32_nxv8i64(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv2f32_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv2f32.nxv8i64(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv2f32_nxv8i64(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv2f32_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv2f32.nxv8i64(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv2f32.nxv1i8(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv2f32.nxv1i8(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg2_nxv2f32_nxv1i8(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv2f32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv2f32.nxv1i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv2f32_nxv1i8(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv2f32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv2f32.nxv1i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv2f32.nxv2i8(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv2f32.nxv2i8(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg2_nxv2f32_nxv2i8(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv2f32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv2f32.nxv2i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv2f32_nxv2i8(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv2f32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv2f32.nxv2i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv2f32.nxv8i32(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i32>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv2f32.nxv8i32(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg2_nxv2f32_nxv8i32(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv2f32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv2f32.nxv8i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv2f32_nxv8i32(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv2f32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv2f32.nxv8i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv2f32.nxv32i8(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 32 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv2f32.nxv32i8(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 32 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg2_nxv2f32_nxv32i8(<vscale x 2 x float> %val, float* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv2f32_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv2f32.nxv32i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 32 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv2f32_nxv32i8(<vscale x 2 x float> %val, float* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv2f32_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv2f32.nxv32i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv2f32.nxv16i32(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i32>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv2f32.nxv16i32(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg2_nxv2f32_nxv16i32(<vscale x 2 x float> %val, float* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv2f32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv2f32.nxv16i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 16 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv2f32_nxv16i32(<vscale x 2 x float> %val, float* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv2f32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv2f32.nxv16i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv2f32.nxv2i16(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i16>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv2f32.nxv2i16(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg2_nxv2f32_nxv2i16(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv2f32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv2f32.nxv2i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv2f32_nxv2i16(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv2f32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv2f32.nxv2i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv2f32.nxv2i64(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i64>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv2f32.nxv2i64(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg2_nxv2f32_nxv2i64(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv2f32_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv2f32.nxv2i64(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv2f32_nxv2i64(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv2f32_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv2f32.nxv2i64(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv2f32.nxv16i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i16>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv2f32.nxv16i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg3_nxv2f32_nxv16i16(<vscale x 2 x float> %val, float* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv2f32_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv2f32.nxv16i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 16 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv2f32_nxv16i16(<vscale x 2 x float> %val, float* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv2f32_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv2f32.nxv16i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv2f32.nxv32i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 32 x i16>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv2f32.nxv32i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 32 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg3_nxv2f32_nxv32i16(<vscale x 2 x float> %val, float* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv2f32_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv2f32.nxv32i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 32 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv2f32_nxv32i16(<vscale x 2 x float> %val, float* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv2f32_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv2f32.nxv32i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv2f32.nxv4i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i32>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv2f32.nxv4i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg3_nxv2f32_nxv4i32(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv2f32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv2f32.nxv4i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv2f32_nxv4i32(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv2f32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv2f32.nxv4i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv2f32.nxv16i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i8>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv2f32.nxv16i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg3_nxv2f32_nxv16i8(<vscale x 2 x float> %val, float* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv2f32_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv2f32.nxv16i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 16 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv2f32_nxv16i8(<vscale x 2 x float> %val, float* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv2f32_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv2f32.nxv16i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv2f32.nxv1i64(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv2f32.nxv1i64(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i64>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg3_nxv2f32_nxv1i64(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv2f32_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei64.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv2f32.nxv1i64(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv2f32_nxv1i64(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv2f32_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei64.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv2f32.nxv1i64(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv2f32.nxv1i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv2f32.nxv1i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg3_nxv2f32_nxv1i32(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv2f32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv2f32.nxv1i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv2f32_nxv1i32(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv2f32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv2f32.nxv1i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv2f32.nxv8i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i16>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv2f32.nxv8i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg3_nxv2f32_nxv8i16(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv2f32_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv2f32.nxv8i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv2f32_nxv8i16(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv2f32_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv2f32.nxv8i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv2f32.nxv4i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i8>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv2f32.nxv4i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg3_nxv2f32_nxv4i8(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv2f32_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv2f32.nxv4i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv2f32_nxv4i8(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv2f32_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv2f32.nxv4i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv2f32.nxv1i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv2f32.nxv1i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg3_nxv2f32_nxv1i16(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv2f32_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv2f32.nxv1i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv2f32_nxv1i16(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv2f32_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv2f32.nxv1i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv2f32.nxv2i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i32>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv2f32.nxv2i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg3_nxv2f32_nxv2i32(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv2f32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv2f32.nxv2i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv2f32_nxv2i32(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv2f32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv2f32.nxv2i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv2f32.nxv8i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i8>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv2f32.nxv8i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg3_nxv2f32_nxv8i8(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv2f32_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv2f32.nxv8i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv2f32_nxv8i8(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv2f32_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv2f32.nxv8i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv2f32.nxv4i64(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i64>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv2f32.nxv4i64(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i64>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg3_nxv2f32_nxv4i64(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv2f32_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei64.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv2f32.nxv4i64(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv2f32_nxv4i64(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv2f32_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei64.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv2f32.nxv4i64(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv2f32.nxv64i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 64 x i8>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv2f32.nxv64i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 64 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg3_nxv2f32_nxv64i8(<vscale x 2 x float> %val, float* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv2f32_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv2f32.nxv64i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 64 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv2f32_nxv64i8(<vscale x 2 x float> %val, float* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv2f32_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv2f32.nxv64i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv2f32.nxv4i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i16>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv2f32.nxv4i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg3_nxv2f32_nxv4i16(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv2f32_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv2f32.nxv4i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv2f32_nxv4i16(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv2f32_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv2f32.nxv4i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv2f32.nxv8i64(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i64>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv2f32.nxv8i64(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i64>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg3_nxv2f32_nxv8i64(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv2f32_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei64.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv2f32.nxv8i64(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv2f32_nxv8i64(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv2f32_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei64.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv2f32.nxv8i64(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv2f32.nxv1i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv2f32.nxv1i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg3_nxv2f32_nxv1i8(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv2f32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv2f32.nxv1i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv2f32_nxv1i8(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv2f32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv2f32.nxv1i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv2f32.nxv2i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i8>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv2f32.nxv2i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg3_nxv2f32_nxv2i8(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv2f32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv2f32.nxv2i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv2f32_nxv2i8(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv2f32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv2f32.nxv2i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv2f32.nxv8i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i32>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv2f32.nxv8i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg3_nxv2f32_nxv8i32(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv2f32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv2f32.nxv8i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv2f32_nxv8i32(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv2f32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv2f32.nxv8i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv2f32.nxv32i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 32 x i8>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv2f32.nxv32i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 32 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg3_nxv2f32_nxv32i8(<vscale x 2 x float> %val, float* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv2f32_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv2f32.nxv32i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 32 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv2f32_nxv32i8(<vscale x 2 x float> %val, float* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv2f32_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv2f32.nxv32i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv2f32.nxv16i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i32>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv2f32.nxv16i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg3_nxv2f32_nxv16i32(<vscale x 2 x float> %val, float* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv2f32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv2f32.nxv16i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 16 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv2f32_nxv16i32(<vscale x 2 x float> %val, float* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv2f32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv2f32.nxv16i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv2f32.nxv2i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i16>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv2f32.nxv2i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg3_nxv2f32_nxv2i16(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv2f32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv2f32.nxv2i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv2f32_nxv2i16(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv2f32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv2f32.nxv2i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv2f32.nxv2i64(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i64>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv2f32.nxv2i64(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg3_nxv2f32_nxv2i64(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv2f32_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei64.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv2f32.nxv2i64(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv2f32_nxv2i64(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv2f32_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei64.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv2f32.nxv2i64(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv2f32.nxv16i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i16>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv2f32.nxv16i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg4_nxv2f32_nxv16i16(<vscale x 2 x float> %val, float* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv2f32_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv2f32.nxv16i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 16 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv2f32_nxv16i16(<vscale x 2 x float> %val, float* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv2f32_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv2f32.nxv16i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv2f32.nxv32i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 32 x i16>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv2f32.nxv32i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 32 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg4_nxv2f32_nxv32i16(<vscale x 2 x float> %val, float* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv2f32_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv2f32.nxv32i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 32 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv2f32_nxv32i16(<vscale x 2 x float> %val, float* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv2f32_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv2f32.nxv32i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv2f32.nxv4i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i32>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv2f32.nxv4i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg4_nxv2f32_nxv4i32(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv2f32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv2f32.nxv4i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv2f32_nxv4i32(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv2f32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv2f32.nxv4i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv2f32.nxv16i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i8>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv2f32.nxv16i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg4_nxv2f32_nxv16i8(<vscale x 2 x float> %val, float* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv2f32_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv2f32.nxv16i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 16 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv2f32_nxv16i8(<vscale x 2 x float> %val, float* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv2f32_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv2f32.nxv16i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv2f32.nxv1i64(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv2f32.nxv1i64(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i64>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg4_nxv2f32_nxv1i64(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv2f32_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei64.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv2f32.nxv1i64(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv2f32_nxv1i64(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv2f32_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei64.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv2f32.nxv1i64(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv2f32.nxv1i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv2f32.nxv1i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg4_nxv2f32_nxv1i32(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv2f32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv2f32.nxv1i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv2f32_nxv1i32(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv2f32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv2f32.nxv1i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv2f32.nxv8i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i16>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv2f32.nxv8i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg4_nxv2f32_nxv8i16(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv2f32_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv2f32.nxv8i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv2f32_nxv8i16(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv2f32_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv2f32.nxv8i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv2f32.nxv4i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i8>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv2f32.nxv4i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg4_nxv2f32_nxv4i8(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv2f32_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv2f32.nxv4i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv2f32_nxv4i8(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv2f32_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv2f32.nxv4i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv2f32.nxv1i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv2f32.nxv1i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg4_nxv2f32_nxv1i16(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv2f32_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv2f32.nxv1i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv2f32_nxv1i16(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv2f32_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv2f32.nxv1i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv2f32.nxv2i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i32>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv2f32.nxv2i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg4_nxv2f32_nxv2i32(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv2f32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv2f32.nxv2i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv2f32_nxv2i32(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv2f32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv2f32.nxv2i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv2f32.nxv8i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i8>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv2f32.nxv8i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg4_nxv2f32_nxv8i8(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv2f32_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv2f32.nxv8i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv2f32_nxv8i8(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv2f32_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv2f32.nxv8i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv2f32.nxv4i64(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i64>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv2f32.nxv4i64(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i64>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg4_nxv2f32_nxv4i64(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv2f32_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei64.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv2f32.nxv4i64(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv2f32_nxv4i64(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv2f32_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei64.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv2f32.nxv4i64(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv2f32.nxv64i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 64 x i8>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv2f32.nxv64i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 64 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg4_nxv2f32_nxv64i8(<vscale x 2 x float> %val, float* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv2f32_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv2f32.nxv64i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 64 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv2f32_nxv64i8(<vscale x 2 x float> %val, float* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv2f32_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv2f32.nxv64i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv2f32.nxv4i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i16>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv2f32.nxv4i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg4_nxv2f32_nxv4i16(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv2f32_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv2f32.nxv4i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv2f32_nxv4i16(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv2f32_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv2f32.nxv4i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv2f32.nxv8i64(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i64>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv2f32.nxv8i64(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i64>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg4_nxv2f32_nxv8i64(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv2f32_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei64.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv2f32.nxv8i64(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv2f32_nxv8i64(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv2f32_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei64.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv2f32.nxv8i64(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv2f32.nxv1i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv2f32.nxv1i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg4_nxv2f32_nxv1i8(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv2f32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv2f32.nxv1i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv2f32_nxv1i8(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv2f32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv2f32.nxv1i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv2f32.nxv2i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i8>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv2f32.nxv2i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg4_nxv2f32_nxv2i8(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv2f32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv2f32.nxv2i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv2f32_nxv2i8(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv2f32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv2f32.nxv2i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv2f32.nxv8i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i32>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv2f32.nxv8i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg4_nxv2f32_nxv8i32(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv2f32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv2f32.nxv8i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv2f32_nxv8i32(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv2f32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv2f32.nxv8i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv2f32.nxv32i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 32 x i8>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv2f32.nxv32i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 32 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg4_nxv2f32_nxv32i8(<vscale x 2 x float> %val, float* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv2f32_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv2f32.nxv32i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 32 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv2f32_nxv32i8(<vscale x 2 x float> %val, float* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv2f32_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv2f32.nxv32i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv2f32.nxv16i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i32>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv2f32.nxv16i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg4_nxv2f32_nxv16i32(<vscale x 2 x float> %val, float* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv2f32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv2f32.nxv16i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 16 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv2f32_nxv16i32(<vscale x 2 x float> %val, float* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv2f32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv2f32.nxv16i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv2f32.nxv2i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i16>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv2f32.nxv2i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg4_nxv2f32_nxv2i16(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv2f32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv2f32.nxv2i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv2f32_nxv2i16(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv2f32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv2f32.nxv2i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv2f32.nxv2i64(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i64>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv2f32.nxv2i64(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg4_nxv2f32_nxv2i64(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv2f32_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei64.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv2f32.nxv2i64(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv2f32_nxv2i64(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv2f32_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei64.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv2f32.nxv2i64(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv2f32.nxv16i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i16>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv2f32.nxv16i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg5_nxv2f32_nxv16i16(<vscale x 2 x float> %val, float* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv2f32_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv2f32.nxv16i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 16 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv2f32_nxv16i16(<vscale x 2 x float> %val, float* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv2f32_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv2f32.nxv16i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv2f32.nxv32i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 32 x i16>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv2f32.nxv32i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 32 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg5_nxv2f32_nxv32i16(<vscale x 2 x float> %val, float* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv2f32_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv2f32.nxv32i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 32 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv2f32_nxv32i16(<vscale x 2 x float> %val, float* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv2f32_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv2f32.nxv32i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv2f32.nxv4i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i32>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv2f32.nxv4i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg5_nxv2f32_nxv4i32(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv2f32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei32.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv2f32.nxv4i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv2f32_nxv4i32(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv2f32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei32.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv2f32.nxv4i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv2f32.nxv16i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i8>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv2f32.nxv16i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg5_nxv2f32_nxv16i8(<vscale x 2 x float> %val, float* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv2f32_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv2f32.nxv16i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 16 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv2f32_nxv16i8(<vscale x 2 x float> %val, float* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv2f32_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv2f32.nxv16i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv2f32.nxv1i64(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv2f32.nxv1i64(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i64>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg5_nxv2f32_nxv1i64(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv2f32_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei64.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv2f32.nxv1i64(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv2f32_nxv1i64(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv2f32_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei64.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv2f32.nxv1i64(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv2f32.nxv1i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv2f32.nxv1i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg5_nxv2f32_nxv1i32(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv2f32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv2f32.nxv1i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv2f32_nxv1i32(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv2f32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv2f32.nxv1i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv2f32.nxv8i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i16>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv2f32.nxv8i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg5_nxv2f32_nxv8i16(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv2f32_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv2f32.nxv8i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv2f32_nxv8i16(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv2f32_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv2f32.nxv8i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv2f32.nxv4i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i8>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv2f32.nxv4i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg5_nxv2f32_nxv4i8(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv2f32_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv2f32.nxv4i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv2f32_nxv4i8(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv2f32_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv2f32.nxv4i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv2f32.nxv1i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv2f32.nxv1i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg5_nxv2f32_nxv1i16(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv2f32_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv2f32.nxv1i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv2f32_nxv1i16(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv2f32_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv2f32.nxv1i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv2f32.nxv2i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i32>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv2f32.nxv2i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg5_nxv2f32_nxv2i32(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv2f32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv2f32.nxv2i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv2f32_nxv2i32(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv2f32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv2f32.nxv2i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv2f32.nxv8i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i8>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv2f32.nxv8i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg5_nxv2f32_nxv8i8(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv2f32_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv2f32.nxv8i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv2f32_nxv8i8(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv2f32_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv2f32.nxv8i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv2f32.nxv4i64(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i64>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv2f32.nxv4i64(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i64>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg5_nxv2f32_nxv4i64(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv2f32_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei64.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv2f32.nxv4i64(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv2f32_nxv4i64(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv2f32_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei64.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv2f32.nxv4i64(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv2f32.nxv64i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 64 x i8>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv2f32.nxv64i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 64 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg5_nxv2f32_nxv64i8(<vscale x 2 x float> %val, float* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv2f32_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv2f32.nxv64i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 64 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv2f32_nxv64i8(<vscale x 2 x float> %val, float* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv2f32_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv2f32.nxv64i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv2f32.nxv4i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i16>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv2f32.nxv4i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg5_nxv2f32_nxv4i16(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv2f32_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv2f32.nxv4i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv2f32_nxv4i16(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv2f32_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv2f32.nxv4i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv2f32.nxv8i64(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i64>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv2f32.nxv8i64(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i64>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg5_nxv2f32_nxv8i64(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv2f32_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei64.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv2f32.nxv8i64(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv2f32_nxv8i64(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv2f32_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei64.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv2f32.nxv8i64(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv2f32.nxv1i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv2f32.nxv1i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg5_nxv2f32_nxv1i8(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv2f32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv2f32.nxv1i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv2f32_nxv1i8(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv2f32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv2f32.nxv1i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv2f32.nxv2i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i8>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv2f32.nxv2i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg5_nxv2f32_nxv2i8(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv2f32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv2f32.nxv2i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv2f32_nxv2i8(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv2f32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv2f32.nxv2i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv2f32.nxv8i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i32>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv2f32.nxv8i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg5_nxv2f32_nxv8i32(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv2f32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei32.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv2f32.nxv8i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv2f32_nxv8i32(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv2f32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei32.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv2f32.nxv8i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv2f32.nxv32i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 32 x i8>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv2f32.nxv32i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 32 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg5_nxv2f32_nxv32i8(<vscale x 2 x float> %val, float* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv2f32_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv2f32.nxv32i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 32 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv2f32_nxv32i8(<vscale x 2 x float> %val, float* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv2f32_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv2f32.nxv32i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv2f32.nxv16i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i32>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv2f32.nxv16i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg5_nxv2f32_nxv16i32(<vscale x 2 x float> %val, float* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv2f32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei32.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv2f32.nxv16i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 16 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv2f32_nxv16i32(<vscale x 2 x float> %val, float* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv2f32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei32.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv2f32.nxv16i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv2f32.nxv2i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i16>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv2f32.nxv2i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg5_nxv2f32_nxv2i16(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv2f32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv2f32.nxv2i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv2f32_nxv2i16(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv2f32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv2f32.nxv2i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv2f32.nxv2i64(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i64>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv2f32.nxv2i64(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg5_nxv2f32_nxv2i64(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv2f32_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei64.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv2f32.nxv2i64(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv2f32_nxv2i64(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv2f32_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei64.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv2f32.nxv2i64(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv2f32.nxv16i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i16>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv2f32.nxv16i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg6_nxv2f32_nxv16i16(<vscale x 2 x float> %val, float* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv2f32_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv2f32.nxv16i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 16 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv2f32_nxv16i16(<vscale x 2 x float> %val, float* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv2f32_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv2f32.nxv16i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv2f32.nxv32i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 32 x i16>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv2f32.nxv32i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 32 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg6_nxv2f32_nxv32i16(<vscale x 2 x float> %val, float* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv2f32_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv2f32.nxv32i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 32 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv2f32_nxv32i16(<vscale x 2 x float> %val, float* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv2f32_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv2f32.nxv32i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv2f32.nxv4i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i32>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv2f32.nxv4i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg6_nxv2f32_nxv4i32(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv2f32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei32.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv2f32.nxv4i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv2f32_nxv4i32(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv2f32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei32.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv2f32.nxv4i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv2f32.nxv16i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i8>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv2f32.nxv16i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg6_nxv2f32_nxv16i8(<vscale x 2 x float> %val, float* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv2f32_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv2f32.nxv16i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 16 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv2f32_nxv16i8(<vscale x 2 x float> %val, float* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv2f32_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv2f32.nxv16i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv2f32.nxv1i64(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv2f32.nxv1i64(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i64>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg6_nxv2f32_nxv1i64(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv2f32_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei64.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv2f32.nxv1i64(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv2f32_nxv1i64(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv2f32_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei64.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv2f32.nxv1i64(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv2f32.nxv1i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv2f32.nxv1i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg6_nxv2f32_nxv1i32(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv2f32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv2f32.nxv1i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv2f32_nxv1i32(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv2f32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv2f32.nxv1i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv2f32.nxv8i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i16>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv2f32.nxv8i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg6_nxv2f32_nxv8i16(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv2f32_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv2f32.nxv8i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv2f32_nxv8i16(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv2f32_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv2f32.nxv8i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv2f32.nxv4i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i8>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv2f32.nxv4i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg6_nxv2f32_nxv4i8(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv2f32_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv2f32.nxv4i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv2f32_nxv4i8(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv2f32_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv2f32.nxv4i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv2f32.nxv1i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv2f32.nxv1i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg6_nxv2f32_nxv1i16(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv2f32_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv2f32.nxv1i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv2f32_nxv1i16(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv2f32_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv2f32.nxv1i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv2f32.nxv2i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i32>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv2f32.nxv2i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg6_nxv2f32_nxv2i32(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv2f32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv2f32.nxv2i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv2f32_nxv2i32(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv2f32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv2f32.nxv2i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv2f32.nxv8i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i8>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv2f32.nxv8i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg6_nxv2f32_nxv8i8(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv2f32_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv2f32.nxv8i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv2f32_nxv8i8(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv2f32_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv2f32.nxv8i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv2f32.nxv4i64(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i64>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv2f32.nxv4i64(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i64>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg6_nxv2f32_nxv4i64(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv2f32_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei64.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv2f32.nxv4i64(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv2f32_nxv4i64(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv2f32_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei64.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv2f32.nxv4i64(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv2f32.nxv64i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 64 x i8>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv2f32.nxv64i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 64 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg6_nxv2f32_nxv64i8(<vscale x 2 x float> %val, float* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv2f32_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv2f32.nxv64i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 64 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv2f32_nxv64i8(<vscale x 2 x float> %val, float* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv2f32_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv2f32.nxv64i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv2f32.nxv4i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i16>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv2f32.nxv4i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg6_nxv2f32_nxv4i16(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv2f32_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv2f32.nxv4i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv2f32_nxv4i16(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv2f32_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv2f32.nxv4i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv2f32.nxv8i64(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i64>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv2f32.nxv8i64(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i64>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg6_nxv2f32_nxv8i64(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv2f32_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei64.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv2f32.nxv8i64(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv2f32_nxv8i64(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv2f32_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei64.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv2f32.nxv8i64(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv2f32.nxv1i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv2f32.nxv1i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg6_nxv2f32_nxv1i8(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv2f32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv2f32.nxv1i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv2f32_nxv1i8(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv2f32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv2f32.nxv1i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv2f32.nxv2i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i8>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv2f32.nxv2i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg6_nxv2f32_nxv2i8(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv2f32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv2f32.nxv2i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv2f32_nxv2i8(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv2f32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv2f32.nxv2i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv2f32.nxv8i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i32>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv2f32.nxv8i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg6_nxv2f32_nxv8i32(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv2f32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei32.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv2f32.nxv8i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv2f32_nxv8i32(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv2f32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei32.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv2f32.nxv8i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv2f32.nxv32i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 32 x i8>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv2f32.nxv32i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 32 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg6_nxv2f32_nxv32i8(<vscale x 2 x float> %val, float* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv2f32_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv2f32.nxv32i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 32 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv2f32_nxv32i8(<vscale x 2 x float> %val, float* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv2f32_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv2f32.nxv32i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv2f32.nxv16i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i32>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv2f32.nxv16i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg6_nxv2f32_nxv16i32(<vscale x 2 x float> %val, float* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv2f32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei32.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv2f32.nxv16i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 16 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv2f32_nxv16i32(<vscale x 2 x float> %val, float* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv2f32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei32.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv2f32.nxv16i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv2f32.nxv2i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i16>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv2f32.nxv2i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg6_nxv2f32_nxv2i16(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv2f32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv2f32.nxv2i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv2f32_nxv2i16(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv2f32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv2f32.nxv2i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv2f32.nxv2i64(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i64>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv2f32.nxv2i64(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg6_nxv2f32_nxv2i64(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv2f32_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei64.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv2f32.nxv2i64(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv2f32_nxv2i64(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv2f32_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei64.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv2f32.nxv2i64(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv2f32.nxv16i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i16>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv2f32.nxv16i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg7_nxv2f32_nxv16i16(<vscale x 2 x float> %val, float* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv2f32_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv2f32.nxv16i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 16 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv2f32_nxv16i16(<vscale x 2 x float> %val, float* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv2f32_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv2f32.nxv16i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv2f32.nxv32i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 32 x i16>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv2f32.nxv32i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 32 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg7_nxv2f32_nxv32i16(<vscale x 2 x float> %val, float* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv2f32_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv2f32.nxv32i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 32 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv2f32_nxv32i16(<vscale x 2 x float> %val, float* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv2f32_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv2f32.nxv32i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv2f32.nxv4i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i32>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv2f32.nxv4i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg7_nxv2f32_nxv4i32(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv2f32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei32.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv2f32.nxv4i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv2f32_nxv4i32(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv2f32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei32.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv2f32.nxv4i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv2f32.nxv16i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i8>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv2f32.nxv16i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg7_nxv2f32_nxv16i8(<vscale x 2 x float> %val, float* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv2f32_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv2f32.nxv16i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 16 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv2f32_nxv16i8(<vscale x 2 x float> %val, float* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv2f32_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv2f32.nxv16i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv2f32.nxv1i64(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv2f32.nxv1i64(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i64>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg7_nxv2f32_nxv1i64(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv2f32_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei64.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv2f32.nxv1i64(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv2f32_nxv1i64(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv2f32_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei64.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv2f32.nxv1i64(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv2f32.nxv1i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv2f32.nxv1i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg7_nxv2f32_nxv1i32(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv2f32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv2f32.nxv1i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv2f32_nxv1i32(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv2f32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv2f32.nxv1i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv2f32.nxv8i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i16>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv2f32.nxv8i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg7_nxv2f32_nxv8i16(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv2f32_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv2f32.nxv8i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv2f32_nxv8i16(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv2f32_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv2f32.nxv8i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv2f32.nxv4i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i8>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv2f32.nxv4i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg7_nxv2f32_nxv4i8(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv2f32_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv2f32.nxv4i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv2f32_nxv4i8(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv2f32_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv2f32.nxv4i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv2f32.nxv1i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv2f32.nxv1i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg7_nxv2f32_nxv1i16(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv2f32_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv2f32.nxv1i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv2f32_nxv1i16(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv2f32_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv2f32.nxv1i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv2f32.nxv2i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i32>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv2f32.nxv2i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg7_nxv2f32_nxv2i32(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv2f32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv2f32.nxv2i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv2f32_nxv2i32(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv2f32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv2f32.nxv2i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv2f32.nxv8i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i8>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv2f32.nxv8i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg7_nxv2f32_nxv8i8(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv2f32_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv2f32.nxv8i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv2f32_nxv8i8(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv2f32_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv2f32.nxv8i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv2f32.nxv4i64(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i64>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv2f32.nxv4i64(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i64>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg7_nxv2f32_nxv4i64(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv2f32_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei64.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv2f32.nxv4i64(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv2f32_nxv4i64(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv2f32_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei64.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv2f32.nxv4i64(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv2f32.nxv64i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 64 x i8>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv2f32.nxv64i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 64 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg7_nxv2f32_nxv64i8(<vscale x 2 x float> %val, float* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv2f32_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv2f32.nxv64i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 64 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv2f32_nxv64i8(<vscale x 2 x float> %val, float* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv2f32_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv2f32.nxv64i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv2f32.nxv4i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i16>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv2f32.nxv4i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg7_nxv2f32_nxv4i16(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv2f32_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv2f32.nxv4i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv2f32_nxv4i16(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv2f32_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv2f32.nxv4i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv2f32.nxv8i64(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i64>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv2f32.nxv8i64(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i64>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg7_nxv2f32_nxv8i64(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv2f32_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei64.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv2f32.nxv8i64(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv2f32_nxv8i64(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv2f32_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei64.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv2f32.nxv8i64(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv2f32.nxv1i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv2f32.nxv1i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg7_nxv2f32_nxv1i8(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv2f32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv2f32.nxv1i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv2f32_nxv1i8(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv2f32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv2f32.nxv1i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv2f32.nxv2i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i8>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv2f32.nxv2i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg7_nxv2f32_nxv2i8(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv2f32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv2f32.nxv2i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv2f32_nxv2i8(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv2f32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv2f32.nxv2i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv2f32.nxv8i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i32>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv2f32.nxv8i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg7_nxv2f32_nxv8i32(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv2f32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei32.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv2f32.nxv8i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv2f32_nxv8i32(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv2f32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei32.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv2f32.nxv8i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv2f32.nxv32i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 32 x i8>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv2f32.nxv32i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 32 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg7_nxv2f32_nxv32i8(<vscale x 2 x float> %val, float* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv2f32_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv2f32.nxv32i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 32 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv2f32_nxv32i8(<vscale x 2 x float> %val, float* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv2f32_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv2f32.nxv32i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv2f32.nxv16i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i32>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv2f32.nxv16i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg7_nxv2f32_nxv16i32(<vscale x 2 x float> %val, float* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv2f32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei32.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv2f32.nxv16i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 16 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv2f32_nxv16i32(<vscale x 2 x float> %val, float* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv2f32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei32.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv2f32.nxv16i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv2f32.nxv2i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i16>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv2f32.nxv2i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg7_nxv2f32_nxv2i16(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv2f32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv2f32.nxv2i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv2f32_nxv2i16(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv2f32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv2f32.nxv2i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv2f32.nxv2i64(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i64>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv2f32.nxv2i64(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg7_nxv2f32_nxv2i64(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv2f32_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei64.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv2f32.nxv2i64(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv2f32_nxv2i64(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv2f32_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei64.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv2f32.nxv2i64(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv2f32.nxv16i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i16>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv2f32.nxv16i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg8_nxv2f32_nxv16i16(<vscale x 2 x float> %val, float* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv2f32_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv2f32.nxv16i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 16 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv2f32_nxv16i16(<vscale x 2 x float> %val, float* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv2f32_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv2f32.nxv16i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv2f32.nxv32i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 32 x i16>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv2f32.nxv32i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 32 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg8_nxv2f32_nxv32i16(<vscale x 2 x float> %val, float* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv2f32_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vmv1r.v v23, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv2f32.nxv32i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 32 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv2f32_nxv32i16(<vscale x 2 x float> %val, float* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv2f32_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vmv1r.v v23, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv2f32.nxv32i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv2f32.nxv4i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i32>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv2f32.nxv4i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg8_nxv2f32_nxv4i32(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv2f32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei32.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv2f32.nxv4i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv2f32_nxv4i32(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv2f32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei32.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv2f32.nxv4i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv2f32.nxv16i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i8>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv2f32.nxv16i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg8_nxv2f32_nxv16i8(<vscale x 2 x float> %val, float* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv2f32_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv2f32.nxv16i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 16 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv2f32_nxv16i8(<vscale x 2 x float> %val, float* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv2f32_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv2f32.nxv16i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv2f32.nxv1i64(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv2f32.nxv1i64(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i64>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg8_nxv2f32_nxv1i64(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv2f32_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei64.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv2f32.nxv1i64(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv2f32_nxv1i64(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv2f32_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei64.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv2f32.nxv1i64(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv2f32.nxv1i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv2f32.nxv1i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg8_nxv2f32_nxv1i32(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv2f32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv2f32.nxv1i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv2f32_nxv1i32(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv2f32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv2f32.nxv1i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv2f32.nxv8i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i16>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv2f32.nxv8i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg8_nxv2f32_nxv8i16(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv2f32_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv2f32.nxv8i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv2f32_nxv8i16(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv2f32_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv2f32.nxv8i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv2f32.nxv4i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i8>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv2f32.nxv4i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg8_nxv2f32_nxv4i8(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv2f32_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv2f32.nxv4i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv2f32_nxv4i8(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv2f32_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv2f32.nxv4i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv2f32.nxv1i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv2f32.nxv1i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg8_nxv2f32_nxv1i16(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv2f32_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv2f32.nxv1i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv2f32_nxv1i16(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv2f32_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv2f32.nxv1i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv2f32.nxv2i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i32>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv2f32.nxv2i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg8_nxv2f32_nxv2i32(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv2f32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv2f32.nxv2i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv2f32_nxv2i32(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv2f32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv2f32.nxv2i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv2f32.nxv8i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i8>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv2f32.nxv8i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg8_nxv2f32_nxv8i8(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv2f32_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv2f32.nxv8i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv2f32_nxv8i8(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv2f32_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv2f32.nxv8i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv2f32.nxv4i64(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i64>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv2f32.nxv4i64(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i64>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg8_nxv2f32_nxv4i64(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv2f32_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei64.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv2f32.nxv4i64(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv2f32_nxv4i64(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv2f32_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei64.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv2f32.nxv4i64(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv2f32.nxv64i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 64 x i8>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv2f32.nxv64i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 64 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg8_nxv2f32_nxv64i8(<vscale x 2 x float> %val, float* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv2f32_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vmv1r.v v23, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv2f32.nxv64i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 64 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv2f32_nxv64i8(<vscale x 2 x float> %val, float* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv2f32_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vmv1r.v v23, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv2f32.nxv64i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv2f32.nxv4i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i16>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv2f32.nxv4i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 4 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg8_nxv2f32_nxv4i16(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv2f32_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv2f32.nxv4i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv2f32_nxv4i16(<vscale x 2 x float> %val, float* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv2f32_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv2f32.nxv4i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv2f32.nxv8i64(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i64>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv2f32.nxv8i64(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i64>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg8_nxv2f32_nxv8i64(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv2f32_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vmv1r.v v23, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei64.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv2f32.nxv8i64(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv2f32_nxv8i64(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv2f32_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vmv1r.v v23, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei64.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv2f32.nxv8i64(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv2f32.nxv1i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv2f32.nxv1i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 1 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg8_nxv2f32_nxv1i8(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv2f32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv2f32.nxv1i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv2f32_nxv1i8(<vscale x 2 x float> %val, float* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv2f32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv2f32.nxv1i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv2f32.nxv2i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i8>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv2f32.nxv2i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg8_nxv2f32_nxv2i8(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv2f32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv2f32.nxv2i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv2f32_nxv2i8(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv2f32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv2f32.nxv2i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv2f32.nxv8i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i32>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv2f32.nxv8i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 8 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg8_nxv2f32_nxv8i32(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv2f32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei32.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv2f32.nxv8i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv2f32_nxv8i32(<vscale x 2 x float> %val, float* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv2f32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei32.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv2f32.nxv8i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv2f32.nxv32i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 32 x i8>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv2f32.nxv32i8(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 32 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg8_nxv2f32_nxv32i8(<vscale x 2 x float> %val, float* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv2f32_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv2f32.nxv32i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 32 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv2f32_nxv32i8(<vscale x 2 x float> %val, float* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv2f32_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv2f32.nxv32i8(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv2f32.nxv16i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i32>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv2f32.nxv16i32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 16 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg8_nxv2f32_nxv16i32(<vscale x 2 x float> %val, float* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv2f32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vmv1r.v v23, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei32.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv2f32.nxv16i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 16 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv2f32_nxv16i32(<vscale x 2 x float> %val, float* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv2f32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vmv1r.v v23, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei32.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv2f32.nxv16i32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv2f32.nxv2i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i16>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv2f32.nxv2i16(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg8_nxv2f32_nxv2i16(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv2f32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv2f32.nxv2i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv2f32_nxv2i16(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv2f32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv2f32.nxv2i16(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv2f32.nxv2i64(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i64>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv2f32.nxv2i64(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg8_nxv2f32_nxv2i64(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv2f32_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei64.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv2f32.nxv2i64(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv2f32_nxv2i64(<vscale x 2 x float> %val, float* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv2f32_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei64.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv2f32.nxv2i64(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv1f16.nxv16i16(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i16>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv1f16.nxv16i16(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg2_nxv1f16_nxv16i16(<vscale x 1 x half> %val, half* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv1f16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv1f16.nxv16i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 16 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv1f16_nxv16i16(<vscale x 1 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv1f16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv1f16.nxv16i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv1f16.nxv32i16(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 32 x i16>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv1f16.nxv32i16(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 32 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg2_nxv1f16_nxv32i16(<vscale x 1 x half> %val, half* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv1f16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv1f16.nxv32i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 32 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv1f16_nxv32i16(<vscale x 1 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv1f16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv1f16.nxv32i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv1f16.nxv4i32(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i32>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv1f16.nxv4i32(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg2_nxv1f16_nxv4i32(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv1f16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv1f16.nxv4i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv1f16_nxv4i32(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv1f16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv1f16.nxv4i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv1f16.nxv16i8(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv1f16.nxv16i8(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg2_nxv1f16_nxv16i8(<vscale x 1 x half> %val, half* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv1f16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv1f16.nxv16i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 16 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv1f16_nxv16i8(<vscale x 1 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv1f16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv1f16.nxv16i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv1f16.nxv1i64(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv1f16.nxv1i64(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg2_nxv1f16_nxv1i64(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv1f16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv1f16.nxv1i64(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv1f16_nxv1i64(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv1f16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv1f16.nxv1i64(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv1f16.nxv1i32(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv1f16.nxv1i32(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg2_nxv1f16_nxv1i32(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv1f16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv1f16.nxv1i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv1f16_nxv1i32(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv1f16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv1f16.nxv1i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv1f16.nxv8i16(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i16>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv1f16.nxv8i16(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg2_nxv1f16_nxv8i16(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv1f16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv1f16.nxv8i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv1f16_nxv8i16(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv1f16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv1f16.nxv8i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv1f16.nxv4i8(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv1f16.nxv4i8(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg2_nxv1f16_nxv4i8(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv1f16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv1f16.nxv4i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv1f16_nxv4i8(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv1f16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv1f16.nxv4i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv1f16.nxv1i16(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv1f16.nxv1i16(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg2_nxv1f16_nxv1i16(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv1f16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv1f16.nxv1i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv1f16_nxv1i16(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv1f16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv1f16.nxv1i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv1f16.nxv2i32(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i32>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv1f16.nxv2i32(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg2_nxv1f16_nxv2i32(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv1f16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv1f16.nxv2i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv1f16_nxv2i32(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv1f16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv1f16.nxv2i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv1f16.nxv8i8(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv1f16.nxv8i8(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg2_nxv1f16_nxv8i8(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv1f16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv1f16.nxv8i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv1f16_nxv8i8(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv1f16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv1f16.nxv8i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv1f16.nxv4i64(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i64>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv1f16.nxv4i64(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg2_nxv1f16_nxv4i64(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv1f16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv1f16.nxv4i64(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv1f16_nxv4i64(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv1f16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv1f16.nxv4i64(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv1f16.nxv64i8(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 64 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv1f16.nxv64i8(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 64 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg2_nxv1f16_nxv64i8(<vscale x 1 x half> %val, half* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv1f16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv1f16.nxv64i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 64 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv1f16_nxv64i8(<vscale x 1 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv1f16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv1f16.nxv64i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv1f16.nxv4i16(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i16>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv1f16.nxv4i16(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg2_nxv1f16_nxv4i16(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv1f16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv1f16.nxv4i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv1f16_nxv4i16(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv1f16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv1f16.nxv4i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv1f16.nxv8i64(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i64>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv1f16.nxv8i64(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg2_nxv1f16_nxv8i64(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv1f16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv1f16.nxv8i64(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv1f16_nxv8i64(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv1f16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv1f16.nxv8i64(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv1f16.nxv1i8(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv1f16.nxv1i8(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg2_nxv1f16_nxv1i8(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv1f16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv1f16.nxv1i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv1f16_nxv1i8(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv1f16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv1f16.nxv1i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv1f16.nxv2i8(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv1f16.nxv2i8(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg2_nxv1f16_nxv2i8(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv1f16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv1f16.nxv2i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv1f16_nxv2i8(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv1f16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv1f16.nxv2i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv1f16.nxv8i32(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i32>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv1f16.nxv8i32(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg2_nxv1f16_nxv8i32(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv1f16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv1f16.nxv8i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv1f16_nxv8i32(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv1f16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv1f16.nxv8i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv1f16.nxv32i8(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 32 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv1f16.nxv32i8(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 32 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg2_nxv1f16_nxv32i8(<vscale x 1 x half> %val, half* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv1f16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv1f16.nxv32i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 32 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv1f16_nxv32i8(<vscale x 1 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv1f16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv1f16.nxv32i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv1f16.nxv16i32(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i32>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv1f16.nxv16i32(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg2_nxv1f16_nxv16i32(<vscale x 1 x half> %val, half* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv1f16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv1f16.nxv16i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 16 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv1f16_nxv16i32(<vscale x 1 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv1f16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv1f16.nxv16i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv1f16.nxv2i16(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i16>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv1f16.nxv2i16(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg2_nxv1f16_nxv2i16(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv1f16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv1f16.nxv2i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv1f16_nxv2i16(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv1f16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv1f16.nxv2i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv1f16.nxv2i64(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i64>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv1f16.nxv2i64(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg2_nxv1f16_nxv2i64(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv1f16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv1f16.nxv2i64(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv1f16_nxv2i64(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv1f16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv1f16.nxv2i64(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv1f16.nxv16i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i16>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv1f16.nxv16i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg3_nxv1f16_nxv16i16(<vscale x 1 x half> %val, half* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv1f16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv1f16.nxv16i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 16 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv1f16_nxv16i16(<vscale x 1 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv1f16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv1f16.nxv16i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv1f16.nxv32i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 32 x i16>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv1f16.nxv32i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 32 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg3_nxv1f16_nxv32i16(<vscale x 1 x half> %val, half* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv1f16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv1f16.nxv32i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 32 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv1f16_nxv32i16(<vscale x 1 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv1f16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv1f16.nxv32i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv1f16.nxv4i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i32>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv1f16.nxv4i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg3_nxv1f16_nxv4i32(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv1f16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv1f16.nxv4i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv1f16_nxv4i32(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv1f16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv1f16.nxv4i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv1f16.nxv16i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i8>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv1f16.nxv16i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg3_nxv1f16_nxv16i8(<vscale x 1 x half> %val, half* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv1f16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv1f16.nxv16i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 16 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv1f16_nxv16i8(<vscale x 1 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv1f16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv1f16.nxv16i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv1f16.nxv1i64(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv1f16.nxv1i64(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg3_nxv1f16_nxv1i64(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv1f16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg3ei64.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv1f16.nxv1i64(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv1f16_nxv1i64(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv1f16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg3ei64.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv1f16.nxv1i64(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv1f16.nxv1i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv1f16.nxv1i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg3_nxv1f16_nxv1i32(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv1f16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv1f16.nxv1i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv1f16_nxv1i32(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv1f16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv1f16.nxv1i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv1f16.nxv8i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i16>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv1f16.nxv8i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg3_nxv1f16_nxv8i16(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv1f16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv1f16.nxv8i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv1f16_nxv8i16(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv1f16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv1f16.nxv8i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv1f16.nxv4i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i8>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv1f16.nxv4i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg3_nxv1f16_nxv4i8(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv1f16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv1f16.nxv4i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv1f16_nxv4i8(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv1f16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv1f16.nxv4i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv1f16.nxv1i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv1f16.nxv1i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg3_nxv1f16_nxv1i16(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv1f16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv1f16.nxv1i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv1f16_nxv1i16(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv1f16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv1f16.nxv1i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv1f16.nxv2i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i32>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv1f16.nxv2i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg3_nxv1f16_nxv2i32(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv1f16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv1f16.nxv2i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv1f16_nxv2i32(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv1f16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv1f16.nxv2i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv1f16.nxv8i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i8>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv1f16.nxv8i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg3_nxv1f16_nxv8i8(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv1f16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv1f16.nxv8i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv1f16_nxv8i8(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv1f16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv1f16.nxv8i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv1f16.nxv4i64(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i64>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv1f16.nxv4i64(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg3_nxv1f16_nxv4i64(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv1f16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg3ei64.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv1f16.nxv4i64(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv1f16_nxv4i64(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv1f16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg3ei64.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv1f16.nxv4i64(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv1f16.nxv64i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 64 x i8>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv1f16.nxv64i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 64 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg3_nxv1f16_nxv64i8(<vscale x 1 x half> %val, half* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv1f16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv1f16.nxv64i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 64 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv1f16_nxv64i8(<vscale x 1 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv1f16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv1f16.nxv64i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv1f16.nxv4i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i16>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv1f16.nxv4i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg3_nxv1f16_nxv4i16(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv1f16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv1f16.nxv4i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv1f16_nxv4i16(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv1f16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv1f16.nxv4i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv1f16.nxv8i64(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i64>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv1f16.nxv8i64(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg3_nxv1f16_nxv8i64(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv1f16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg3ei64.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv1f16.nxv8i64(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv1f16_nxv8i64(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv1f16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg3ei64.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv1f16.nxv8i64(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv1f16.nxv1i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv1f16.nxv1i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg3_nxv1f16_nxv1i8(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv1f16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv1f16.nxv1i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv1f16_nxv1i8(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv1f16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv1f16.nxv1i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv1f16.nxv2i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i8>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv1f16.nxv2i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg3_nxv1f16_nxv2i8(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv1f16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv1f16.nxv2i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv1f16_nxv2i8(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv1f16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv1f16.nxv2i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv1f16.nxv8i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i32>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv1f16.nxv8i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg3_nxv1f16_nxv8i32(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv1f16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv1f16.nxv8i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv1f16_nxv8i32(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv1f16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv1f16.nxv8i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv1f16.nxv32i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 32 x i8>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv1f16.nxv32i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 32 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg3_nxv1f16_nxv32i8(<vscale x 1 x half> %val, half* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv1f16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv1f16.nxv32i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 32 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv1f16_nxv32i8(<vscale x 1 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv1f16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv1f16.nxv32i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv1f16.nxv16i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i32>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv1f16.nxv16i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg3_nxv1f16_nxv16i32(<vscale x 1 x half> %val, half* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv1f16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv1f16.nxv16i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 16 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv1f16_nxv16i32(<vscale x 1 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv1f16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv1f16.nxv16i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv1f16.nxv2i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i16>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv1f16.nxv2i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg3_nxv1f16_nxv2i16(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv1f16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv1f16.nxv2i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv1f16_nxv2i16(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv1f16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv1f16.nxv2i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv1f16.nxv2i64(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i64>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv1f16.nxv2i64(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg3_nxv1f16_nxv2i64(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv1f16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg3ei64.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv1f16.nxv2i64(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv1f16_nxv2i64(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv1f16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg3ei64.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv1f16.nxv2i64(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv1f16.nxv16i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i16>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv1f16.nxv16i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg4_nxv1f16_nxv16i16(<vscale x 1 x half> %val, half* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv1f16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv1f16.nxv16i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 16 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv1f16_nxv16i16(<vscale x 1 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv1f16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv1f16.nxv16i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv1f16.nxv32i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 32 x i16>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv1f16.nxv32i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 32 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg4_nxv1f16_nxv32i16(<vscale x 1 x half> %val, half* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv1f16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv1f16.nxv32i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 32 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv1f16_nxv32i16(<vscale x 1 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv1f16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv1f16.nxv32i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv1f16.nxv4i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i32>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv1f16.nxv4i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg4_nxv1f16_nxv4i32(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv1f16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv1f16.nxv4i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv1f16_nxv4i32(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv1f16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv1f16.nxv4i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv1f16.nxv16i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i8>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv1f16.nxv16i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg4_nxv1f16_nxv16i8(<vscale x 1 x half> %val, half* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv1f16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv1f16.nxv16i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 16 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv1f16_nxv16i8(<vscale x 1 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv1f16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv1f16.nxv16i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv1f16.nxv1i64(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv1f16.nxv1i64(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg4_nxv1f16_nxv1i64(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv1f16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg4ei64.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv1f16.nxv1i64(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv1f16_nxv1i64(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv1f16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg4ei64.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv1f16.nxv1i64(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv1f16.nxv1i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv1f16.nxv1i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg4_nxv1f16_nxv1i32(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv1f16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv1f16.nxv1i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv1f16_nxv1i32(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv1f16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv1f16.nxv1i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv1f16.nxv8i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i16>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv1f16.nxv8i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg4_nxv1f16_nxv8i16(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv1f16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv1f16.nxv8i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv1f16_nxv8i16(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv1f16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv1f16.nxv8i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv1f16.nxv4i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i8>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv1f16.nxv4i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg4_nxv1f16_nxv4i8(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv1f16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv1f16.nxv4i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv1f16_nxv4i8(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv1f16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv1f16.nxv4i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv1f16.nxv1i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv1f16.nxv1i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg4_nxv1f16_nxv1i16(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv1f16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv1f16.nxv1i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv1f16_nxv1i16(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv1f16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv1f16.nxv1i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv1f16.nxv2i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i32>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv1f16.nxv2i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg4_nxv1f16_nxv2i32(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv1f16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv1f16.nxv2i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv1f16_nxv2i32(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv1f16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv1f16.nxv2i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv1f16.nxv8i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i8>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv1f16.nxv8i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg4_nxv1f16_nxv8i8(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv1f16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv1f16.nxv8i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv1f16_nxv8i8(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv1f16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv1f16.nxv8i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv1f16.nxv4i64(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i64>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv1f16.nxv4i64(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg4_nxv1f16_nxv4i64(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv1f16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg4ei64.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv1f16.nxv4i64(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv1f16_nxv4i64(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv1f16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg4ei64.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv1f16.nxv4i64(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv1f16.nxv64i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 64 x i8>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv1f16.nxv64i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 64 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg4_nxv1f16_nxv64i8(<vscale x 1 x half> %val, half* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv1f16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv1f16.nxv64i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 64 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv1f16_nxv64i8(<vscale x 1 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv1f16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv1f16.nxv64i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv1f16.nxv4i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i16>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv1f16.nxv4i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg4_nxv1f16_nxv4i16(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv1f16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv1f16.nxv4i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv1f16_nxv4i16(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv1f16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv1f16.nxv4i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv1f16.nxv8i64(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i64>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv1f16.nxv8i64(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg4_nxv1f16_nxv8i64(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv1f16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg4ei64.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv1f16.nxv8i64(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv1f16_nxv8i64(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv1f16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg4ei64.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv1f16.nxv8i64(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv1f16.nxv1i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv1f16.nxv1i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg4_nxv1f16_nxv1i8(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv1f16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv1f16.nxv1i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv1f16_nxv1i8(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv1f16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv1f16.nxv1i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv1f16.nxv2i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i8>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv1f16.nxv2i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg4_nxv1f16_nxv2i8(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv1f16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv1f16.nxv2i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv1f16_nxv2i8(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv1f16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv1f16.nxv2i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv1f16.nxv8i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i32>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv1f16.nxv8i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg4_nxv1f16_nxv8i32(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv1f16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv1f16.nxv8i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv1f16_nxv8i32(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv1f16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv1f16.nxv8i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv1f16.nxv32i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 32 x i8>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv1f16.nxv32i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 32 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg4_nxv1f16_nxv32i8(<vscale x 1 x half> %val, half* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv1f16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv1f16.nxv32i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 32 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv1f16_nxv32i8(<vscale x 1 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv1f16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv1f16.nxv32i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv1f16.nxv16i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i32>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv1f16.nxv16i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg4_nxv1f16_nxv16i32(<vscale x 1 x half> %val, half* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv1f16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv1f16.nxv16i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 16 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv1f16_nxv16i32(<vscale x 1 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv1f16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv1f16.nxv16i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv1f16.nxv2i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i16>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv1f16.nxv2i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg4_nxv1f16_nxv2i16(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv1f16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv1f16.nxv2i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv1f16_nxv2i16(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv1f16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv1f16.nxv2i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv1f16.nxv2i64(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i64>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv1f16.nxv2i64(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg4_nxv1f16_nxv2i64(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv1f16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg4ei64.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv1f16.nxv2i64(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv1f16_nxv2i64(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv1f16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg4ei64.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv1f16.nxv2i64(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv1f16.nxv16i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i16>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv1f16.nxv16i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg5_nxv1f16_nxv16i16(<vscale x 1 x half> %val, half* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv1f16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv1f16.nxv16i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 16 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv1f16_nxv16i16(<vscale x 1 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv1f16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv1f16.nxv16i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv1f16.nxv32i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 32 x i16>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv1f16.nxv32i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 32 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg5_nxv1f16_nxv32i16(<vscale x 1 x half> %val, half* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv1f16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv1f16.nxv32i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 32 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv1f16_nxv32i16(<vscale x 1 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv1f16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv1f16.nxv32i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv1f16.nxv4i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i32>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv1f16.nxv4i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg5_nxv1f16_nxv4i32(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv1f16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg5ei32.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv1f16.nxv4i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv1f16_nxv4i32(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv1f16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg5ei32.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv1f16.nxv4i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv1f16.nxv16i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i8>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv1f16.nxv16i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg5_nxv1f16_nxv16i8(<vscale x 1 x half> %val, half* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv1f16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv1f16.nxv16i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 16 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv1f16_nxv16i8(<vscale x 1 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv1f16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv1f16.nxv16i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv1f16.nxv1i64(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv1f16.nxv1i64(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg5_nxv1f16_nxv1i64(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv1f16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg5ei64.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv1f16.nxv1i64(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv1f16_nxv1i64(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv1f16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg5ei64.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv1f16.nxv1i64(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv1f16.nxv1i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv1f16.nxv1i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg5_nxv1f16_nxv1i32(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv1f16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg5ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv1f16.nxv1i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv1f16_nxv1i32(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv1f16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg5ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv1f16.nxv1i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv1f16.nxv8i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i16>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv1f16.nxv8i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg5_nxv1f16_nxv8i16(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv1f16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv1f16.nxv8i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv1f16_nxv8i16(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv1f16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv1f16.nxv8i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv1f16.nxv4i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i8>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv1f16.nxv4i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg5_nxv1f16_nxv4i8(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv1f16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv1f16.nxv4i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv1f16_nxv4i8(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv1f16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv1f16.nxv4i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv1f16.nxv1i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv1f16.nxv1i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg5_nxv1f16_nxv1i16(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv1f16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv1f16.nxv1i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv1f16_nxv1i16(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv1f16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv1f16.nxv1i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv1f16.nxv2i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i32>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv1f16.nxv2i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg5_nxv1f16_nxv2i32(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv1f16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg5ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv1f16.nxv2i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv1f16_nxv2i32(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv1f16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg5ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv1f16.nxv2i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv1f16.nxv8i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i8>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv1f16.nxv8i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg5_nxv1f16_nxv8i8(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv1f16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv1f16.nxv8i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv1f16_nxv8i8(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv1f16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv1f16.nxv8i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv1f16.nxv4i64(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i64>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv1f16.nxv4i64(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg5_nxv1f16_nxv4i64(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv1f16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg5ei64.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv1f16.nxv4i64(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv1f16_nxv4i64(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv1f16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg5ei64.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv1f16.nxv4i64(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv1f16.nxv64i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 64 x i8>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv1f16.nxv64i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 64 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg5_nxv1f16_nxv64i8(<vscale x 1 x half> %val, half* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv1f16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv1f16.nxv64i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 64 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv1f16_nxv64i8(<vscale x 1 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv1f16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv1f16.nxv64i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv1f16.nxv4i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i16>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv1f16.nxv4i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg5_nxv1f16_nxv4i16(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv1f16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv1f16.nxv4i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv1f16_nxv4i16(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv1f16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv1f16.nxv4i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv1f16.nxv8i64(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i64>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv1f16.nxv8i64(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg5_nxv1f16_nxv8i64(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv1f16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg5ei64.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv1f16.nxv8i64(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv1f16_nxv8i64(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv1f16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg5ei64.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv1f16.nxv8i64(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv1f16.nxv1i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv1f16.nxv1i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg5_nxv1f16_nxv1i8(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv1f16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv1f16.nxv1i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv1f16_nxv1i8(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv1f16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv1f16.nxv1i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv1f16.nxv2i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i8>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv1f16.nxv2i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg5_nxv1f16_nxv2i8(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv1f16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv1f16.nxv2i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv1f16_nxv2i8(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv1f16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv1f16.nxv2i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv1f16.nxv8i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i32>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv1f16.nxv8i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg5_nxv1f16_nxv8i32(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv1f16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg5ei32.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv1f16.nxv8i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv1f16_nxv8i32(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv1f16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg5ei32.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv1f16.nxv8i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv1f16.nxv32i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 32 x i8>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv1f16.nxv32i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 32 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg5_nxv1f16_nxv32i8(<vscale x 1 x half> %val, half* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv1f16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv1f16.nxv32i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 32 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv1f16_nxv32i8(<vscale x 1 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv1f16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv1f16.nxv32i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv1f16.nxv16i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i32>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv1f16.nxv16i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg5_nxv1f16_nxv16i32(<vscale x 1 x half> %val, half* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv1f16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg5ei32.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv1f16.nxv16i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 16 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv1f16_nxv16i32(<vscale x 1 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv1f16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg5ei32.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv1f16.nxv16i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv1f16.nxv2i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i16>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv1f16.nxv2i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg5_nxv1f16_nxv2i16(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv1f16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv1f16.nxv2i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv1f16_nxv2i16(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv1f16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv1f16.nxv2i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv1f16.nxv2i64(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i64>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv1f16.nxv2i64(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg5_nxv1f16_nxv2i64(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv1f16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg5ei64.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv1f16.nxv2i64(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv1f16_nxv2i64(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv1f16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg5ei64.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv1f16.nxv2i64(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv1f16.nxv16i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i16>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv1f16.nxv16i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg6_nxv1f16_nxv16i16(<vscale x 1 x half> %val, half* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv1f16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv1f16.nxv16i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 16 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv1f16_nxv16i16(<vscale x 1 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv1f16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv1f16.nxv16i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv1f16.nxv32i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 32 x i16>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv1f16.nxv32i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 32 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg6_nxv1f16_nxv32i16(<vscale x 1 x half> %val, half* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv1f16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv1f16.nxv32i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 32 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv1f16_nxv32i16(<vscale x 1 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv1f16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv1f16.nxv32i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv1f16.nxv4i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i32>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv1f16.nxv4i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg6_nxv1f16_nxv4i32(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv1f16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg6ei32.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv1f16.nxv4i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv1f16_nxv4i32(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv1f16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg6ei32.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv1f16.nxv4i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv1f16.nxv16i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i8>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv1f16.nxv16i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg6_nxv1f16_nxv16i8(<vscale x 1 x half> %val, half* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv1f16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv1f16.nxv16i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 16 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv1f16_nxv16i8(<vscale x 1 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv1f16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv1f16.nxv16i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv1f16.nxv1i64(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv1f16.nxv1i64(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg6_nxv1f16_nxv1i64(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv1f16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg6ei64.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv1f16.nxv1i64(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv1f16_nxv1i64(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv1f16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg6ei64.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv1f16.nxv1i64(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv1f16.nxv1i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv1f16.nxv1i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg6_nxv1f16_nxv1i32(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv1f16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg6ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv1f16.nxv1i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv1f16_nxv1i32(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv1f16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg6ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv1f16.nxv1i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv1f16.nxv8i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i16>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv1f16.nxv8i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg6_nxv1f16_nxv8i16(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv1f16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv1f16.nxv8i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv1f16_nxv8i16(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv1f16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv1f16.nxv8i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv1f16.nxv4i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i8>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv1f16.nxv4i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg6_nxv1f16_nxv4i8(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv1f16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv1f16.nxv4i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv1f16_nxv4i8(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv1f16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv1f16.nxv4i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv1f16.nxv1i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv1f16.nxv1i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg6_nxv1f16_nxv1i16(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv1f16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv1f16.nxv1i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv1f16_nxv1i16(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv1f16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv1f16.nxv1i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv1f16.nxv2i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i32>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv1f16.nxv2i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg6_nxv1f16_nxv2i32(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv1f16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg6ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv1f16.nxv2i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv1f16_nxv2i32(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv1f16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg6ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv1f16.nxv2i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv1f16.nxv8i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i8>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv1f16.nxv8i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg6_nxv1f16_nxv8i8(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv1f16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv1f16.nxv8i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv1f16_nxv8i8(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv1f16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv1f16.nxv8i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv1f16.nxv4i64(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i64>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv1f16.nxv4i64(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg6_nxv1f16_nxv4i64(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv1f16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg6ei64.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv1f16.nxv4i64(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv1f16_nxv4i64(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv1f16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg6ei64.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv1f16.nxv4i64(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv1f16.nxv64i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 64 x i8>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv1f16.nxv64i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 64 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg6_nxv1f16_nxv64i8(<vscale x 1 x half> %val, half* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv1f16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv1f16.nxv64i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 64 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv1f16_nxv64i8(<vscale x 1 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv1f16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv1f16.nxv64i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv1f16.nxv4i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i16>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv1f16.nxv4i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg6_nxv1f16_nxv4i16(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv1f16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv1f16.nxv4i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv1f16_nxv4i16(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv1f16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv1f16.nxv4i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv1f16.nxv8i64(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i64>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv1f16.nxv8i64(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg6_nxv1f16_nxv8i64(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv1f16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg6ei64.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv1f16.nxv8i64(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv1f16_nxv8i64(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv1f16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg6ei64.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv1f16.nxv8i64(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv1f16.nxv1i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv1f16.nxv1i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg6_nxv1f16_nxv1i8(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv1f16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv1f16.nxv1i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv1f16_nxv1i8(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv1f16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv1f16.nxv1i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv1f16.nxv2i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i8>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv1f16.nxv2i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg6_nxv1f16_nxv2i8(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv1f16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv1f16.nxv2i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv1f16_nxv2i8(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv1f16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv1f16.nxv2i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv1f16.nxv8i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i32>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv1f16.nxv8i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg6_nxv1f16_nxv8i32(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv1f16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg6ei32.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv1f16.nxv8i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv1f16_nxv8i32(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv1f16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg6ei32.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv1f16.nxv8i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv1f16.nxv32i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 32 x i8>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv1f16.nxv32i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 32 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg6_nxv1f16_nxv32i8(<vscale x 1 x half> %val, half* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv1f16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv1f16.nxv32i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 32 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv1f16_nxv32i8(<vscale x 1 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv1f16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv1f16.nxv32i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv1f16.nxv16i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i32>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv1f16.nxv16i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg6_nxv1f16_nxv16i32(<vscale x 1 x half> %val, half* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv1f16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg6ei32.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv1f16.nxv16i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 16 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv1f16_nxv16i32(<vscale x 1 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv1f16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg6ei32.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv1f16.nxv16i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv1f16.nxv2i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i16>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv1f16.nxv2i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg6_nxv1f16_nxv2i16(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv1f16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv1f16.nxv2i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv1f16_nxv2i16(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv1f16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv1f16.nxv2i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv1f16.nxv2i64(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i64>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv1f16.nxv2i64(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg6_nxv1f16_nxv2i64(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv1f16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg6ei64.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv1f16.nxv2i64(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv1f16_nxv2i64(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv1f16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg6ei64.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv1f16.nxv2i64(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv1f16.nxv16i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i16>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv1f16.nxv16i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg7_nxv1f16_nxv16i16(<vscale x 1 x half> %val, half* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv1f16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv1f16.nxv16i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 16 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv1f16_nxv16i16(<vscale x 1 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv1f16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv1f16.nxv16i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv1f16.nxv32i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 32 x i16>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv1f16.nxv32i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 32 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg7_nxv1f16_nxv32i16(<vscale x 1 x half> %val, half* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv1f16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv1f16.nxv32i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 32 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv1f16_nxv32i16(<vscale x 1 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv1f16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv1f16.nxv32i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv1f16.nxv4i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i32>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv1f16.nxv4i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg7_nxv1f16_nxv4i32(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv1f16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg7ei32.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv1f16.nxv4i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv1f16_nxv4i32(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv1f16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg7ei32.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv1f16.nxv4i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv1f16.nxv16i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i8>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv1f16.nxv16i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg7_nxv1f16_nxv16i8(<vscale x 1 x half> %val, half* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv1f16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv1f16.nxv16i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 16 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv1f16_nxv16i8(<vscale x 1 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv1f16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv1f16.nxv16i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv1f16.nxv1i64(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv1f16.nxv1i64(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg7_nxv1f16_nxv1i64(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv1f16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg7ei64.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv1f16.nxv1i64(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv1f16_nxv1i64(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv1f16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg7ei64.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv1f16.nxv1i64(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv1f16.nxv1i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv1f16.nxv1i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg7_nxv1f16_nxv1i32(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv1f16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg7ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv1f16.nxv1i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv1f16_nxv1i32(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv1f16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg7ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv1f16.nxv1i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv1f16.nxv8i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i16>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv1f16.nxv8i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg7_nxv1f16_nxv8i16(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv1f16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv1f16.nxv8i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv1f16_nxv8i16(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv1f16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv1f16.nxv8i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv1f16.nxv4i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i8>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv1f16.nxv4i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg7_nxv1f16_nxv4i8(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv1f16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv1f16.nxv4i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv1f16_nxv4i8(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv1f16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv1f16.nxv4i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv1f16.nxv1i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv1f16.nxv1i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg7_nxv1f16_nxv1i16(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv1f16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv1f16.nxv1i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv1f16_nxv1i16(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv1f16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv1f16.nxv1i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv1f16.nxv2i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i32>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv1f16.nxv2i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg7_nxv1f16_nxv2i32(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv1f16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg7ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv1f16.nxv2i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv1f16_nxv2i32(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv1f16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg7ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv1f16.nxv2i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv1f16.nxv8i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i8>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv1f16.nxv8i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg7_nxv1f16_nxv8i8(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv1f16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv1f16.nxv8i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv1f16_nxv8i8(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv1f16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv1f16.nxv8i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv1f16.nxv4i64(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i64>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv1f16.nxv4i64(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg7_nxv1f16_nxv4i64(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv1f16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg7ei64.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv1f16.nxv4i64(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv1f16_nxv4i64(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv1f16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg7ei64.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv1f16.nxv4i64(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv1f16.nxv64i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 64 x i8>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv1f16.nxv64i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 64 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg7_nxv1f16_nxv64i8(<vscale x 1 x half> %val, half* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv1f16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv1f16.nxv64i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 64 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv1f16_nxv64i8(<vscale x 1 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv1f16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv1f16.nxv64i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv1f16.nxv4i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i16>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv1f16.nxv4i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg7_nxv1f16_nxv4i16(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv1f16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv1f16.nxv4i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv1f16_nxv4i16(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv1f16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv1f16.nxv4i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv1f16.nxv8i64(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i64>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv1f16.nxv8i64(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg7_nxv1f16_nxv8i64(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv1f16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg7ei64.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv1f16.nxv8i64(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv1f16_nxv8i64(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv1f16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg7ei64.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv1f16.nxv8i64(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv1f16.nxv1i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv1f16.nxv1i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg7_nxv1f16_nxv1i8(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv1f16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv1f16.nxv1i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv1f16_nxv1i8(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv1f16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv1f16.nxv1i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv1f16.nxv2i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i8>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv1f16.nxv2i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg7_nxv1f16_nxv2i8(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv1f16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv1f16.nxv2i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv1f16_nxv2i8(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv1f16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv1f16.nxv2i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv1f16.nxv8i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i32>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv1f16.nxv8i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg7_nxv1f16_nxv8i32(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv1f16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg7ei32.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv1f16.nxv8i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv1f16_nxv8i32(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv1f16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg7ei32.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv1f16.nxv8i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv1f16.nxv32i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 32 x i8>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv1f16.nxv32i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 32 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg7_nxv1f16_nxv32i8(<vscale x 1 x half> %val, half* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv1f16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv1f16.nxv32i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 32 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv1f16_nxv32i8(<vscale x 1 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv1f16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv1f16.nxv32i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv1f16.nxv16i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i32>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv1f16.nxv16i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg7_nxv1f16_nxv16i32(<vscale x 1 x half> %val, half* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv1f16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg7ei32.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv1f16.nxv16i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 16 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv1f16_nxv16i32(<vscale x 1 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv1f16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg7ei32.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv1f16.nxv16i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv1f16.nxv2i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i16>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv1f16.nxv2i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg7_nxv1f16_nxv2i16(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv1f16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv1f16.nxv2i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv1f16_nxv2i16(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv1f16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv1f16.nxv2i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv1f16.nxv2i64(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i64>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv1f16.nxv2i64(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg7_nxv1f16_nxv2i64(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv1f16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg7ei64.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv1f16.nxv2i64(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv1f16_nxv2i64(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv1f16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg7ei64.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv1f16.nxv2i64(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv1f16.nxv16i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i16>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv1f16.nxv16i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg8_nxv1f16_nxv16i16(<vscale x 1 x half> %val, half* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv1f16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv1f16.nxv16i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 16 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv1f16_nxv16i16(<vscale x 1 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv1f16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv1f16.nxv16i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv1f16.nxv32i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 32 x i16>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv1f16.nxv32i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 32 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg8_nxv1f16_nxv32i16(<vscale x 1 x half> %val, half* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv1f16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vmv1r.v v23, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv1f16.nxv32i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 32 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv1f16_nxv32i16(<vscale x 1 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv1f16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vmv1r.v v23, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv1f16.nxv32i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv1f16.nxv4i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i32>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv1f16.nxv4i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg8_nxv1f16_nxv4i32(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv1f16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg8ei32.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv1f16.nxv4i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv1f16_nxv4i32(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv1f16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg8ei32.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv1f16.nxv4i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv1f16.nxv16i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i8>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv1f16.nxv16i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg8_nxv1f16_nxv16i8(<vscale x 1 x half> %val, half* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv1f16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv1f16.nxv16i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 16 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv1f16_nxv16i8(<vscale x 1 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv1f16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv1f16.nxv16i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv1f16.nxv1i64(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv1f16.nxv1i64(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg8_nxv1f16_nxv1i64(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv1f16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg8ei64.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv1f16.nxv1i64(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv1f16_nxv1i64(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv1f16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg8ei64.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv1f16.nxv1i64(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv1f16.nxv1i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv1f16.nxv1i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg8_nxv1f16_nxv1i32(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv1f16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg8ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv1f16.nxv1i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv1f16_nxv1i32(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv1f16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg8ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv1f16.nxv1i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv1f16.nxv8i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i16>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv1f16.nxv8i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg8_nxv1f16_nxv8i16(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv1f16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv1f16.nxv8i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv1f16_nxv8i16(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv1f16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv1f16.nxv8i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv1f16.nxv4i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i8>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv1f16.nxv4i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg8_nxv1f16_nxv4i8(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv1f16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv1f16.nxv4i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv1f16_nxv4i8(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv1f16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv1f16.nxv4i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv1f16.nxv1i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv1f16.nxv1i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg8_nxv1f16_nxv1i16(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv1f16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv1f16.nxv1i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv1f16_nxv1i16(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv1f16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv1f16.nxv1i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv1f16.nxv2i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i32>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv1f16.nxv2i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg8_nxv1f16_nxv2i32(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv1f16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg8ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv1f16.nxv2i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv1f16_nxv2i32(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv1f16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg8ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv1f16.nxv2i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv1f16.nxv8i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i8>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv1f16.nxv8i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg8_nxv1f16_nxv8i8(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv1f16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv1f16.nxv8i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv1f16_nxv8i8(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv1f16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv1f16.nxv8i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv1f16.nxv4i64(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i64>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv1f16.nxv4i64(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg8_nxv1f16_nxv4i64(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv1f16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg8ei64.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv1f16.nxv4i64(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv1f16_nxv4i64(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv1f16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg8ei64.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv1f16.nxv4i64(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv1f16.nxv64i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 64 x i8>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv1f16.nxv64i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 64 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg8_nxv1f16_nxv64i8(<vscale x 1 x half> %val, half* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv1f16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vmv1r.v v23, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv1f16.nxv64i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 64 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv1f16_nxv64i8(<vscale x 1 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv1f16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vmv1r.v v23, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv1f16.nxv64i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv1f16.nxv4i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i16>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv1f16.nxv4i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 4 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg8_nxv1f16_nxv4i16(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv1f16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv1f16.nxv4i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv1f16_nxv4i16(<vscale x 1 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv1f16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv1f16.nxv4i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv1f16.nxv8i64(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i64>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv1f16.nxv8i64(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg8_nxv1f16_nxv8i64(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv1f16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vmv1r.v v23, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg8ei64.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv1f16.nxv8i64(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv1f16_nxv8i64(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv1f16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vmv1r.v v23, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg8ei64.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv1f16.nxv8i64(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv1f16.nxv1i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv1f16.nxv1i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg8_nxv1f16_nxv1i8(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv1f16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv1f16.nxv1i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv1f16_nxv1i8(<vscale x 1 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv1f16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv1f16.nxv1i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv1f16.nxv2i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i8>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv1f16.nxv2i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg8_nxv1f16_nxv2i8(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv1f16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv1f16.nxv2i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv1f16_nxv2i8(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv1f16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv1f16.nxv2i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv1f16.nxv8i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i32>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv1f16.nxv8i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 8 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg8_nxv1f16_nxv8i32(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv1f16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg8ei32.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv1f16.nxv8i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv1f16_nxv8i32(<vscale x 1 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv1f16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg8ei32.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv1f16.nxv8i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv1f16.nxv32i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 32 x i8>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv1f16.nxv32i8(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 32 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg8_nxv1f16_nxv32i8(<vscale x 1 x half> %val, half* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv1f16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv1f16.nxv32i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 32 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv1f16_nxv32i8(<vscale x 1 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv1f16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv1f16.nxv32i8(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv1f16.nxv16i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i32>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv1f16.nxv16i32(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 16 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg8_nxv1f16_nxv16i32(<vscale x 1 x half> %val, half* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv1f16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vmv1r.v v23, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg8ei32.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv1f16.nxv16i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 16 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv1f16_nxv16i32(<vscale x 1 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv1f16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vmv1r.v v23, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg8ei32.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv1f16.nxv16i32(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv1f16.nxv2i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i16>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv1f16.nxv2i16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg8_nxv1f16_nxv2i16(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv1f16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv1f16.nxv2i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv1f16_nxv2i16(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv1f16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv1f16.nxv2i16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv1f16.nxv2i64(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i64>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv1f16.nxv2i64(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 2 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg8_nxv1f16_nxv2i64(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv1f16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg8ei64.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv1f16.nxv2i64(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv1f16_nxv2i64(<vscale x 1 x half> %val, half* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv1f16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vsxseg8ei64.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv1f16.nxv2i64(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv1f32.nxv16i16(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i16>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv1f32.nxv16i16(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg2_nxv1f32_nxv16i16(<vscale x 1 x float> %val, float* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv1f32_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv1f32.nxv16i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 16 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv1f32_nxv16i16(<vscale x 1 x float> %val, float* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv1f32_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv1f32.nxv16i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv1f32.nxv32i16(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 32 x i16>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv1f32.nxv32i16(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 32 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg2_nxv1f32_nxv32i16(<vscale x 1 x float> %val, float* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv1f32_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv1f32.nxv32i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 32 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv1f32_nxv32i16(<vscale x 1 x float> %val, float* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv1f32_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv1f32.nxv32i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv1f32.nxv4i32(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i32>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv1f32.nxv4i32(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg2_nxv1f32_nxv4i32(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv1f32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv1f32.nxv4i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv1f32_nxv4i32(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv1f32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv1f32.nxv4i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv1f32.nxv16i8(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv1f32.nxv16i8(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg2_nxv1f32_nxv16i8(<vscale x 1 x float> %val, float* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv1f32_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv1f32.nxv16i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 16 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv1f32_nxv16i8(<vscale x 1 x float> %val, float* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv1f32_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv1f32.nxv16i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv1f32.nxv1i64(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv1f32.nxv1i64(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg2_nxv1f32_nxv1i64(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv1f32_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv1f32.nxv1i64(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv1f32_nxv1i64(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv1f32_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv1f32.nxv1i64(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv1f32.nxv1i32(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv1f32.nxv1i32(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg2_nxv1f32_nxv1i32(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv1f32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv1f32.nxv1i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv1f32_nxv1i32(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv1f32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv1f32.nxv1i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv1f32.nxv8i16(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i16>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv1f32.nxv8i16(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg2_nxv1f32_nxv8i16(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv1f32_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv1f32.nxv8i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv1f32_nxv8i16(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv1f32_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv1f32.nxv8i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv1f32.nxv4i8(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv1f32.nxv4i8(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg2_nxv1f32_nxv4i8(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv1f32_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv1f32.nxv4i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv1f32_nxv4i8(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv1f32_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv1f32.nxv4i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv1f32.nxv1i16(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv1f32.nxv1i16(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg2_nxv1f32_nxv1i16(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv1f32_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv1f32.nxv1i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv1f32_nxv1i16(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv1f32_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv1f32.nxv1i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv1f32.nxv2i32(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i32>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv1f32.nxv2i32(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg2_nxv1f32_nxv2i32(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv1f32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv1f32.nxv2i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv1f32_nxv2i32(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv1f32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv1f32.nxv2i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv1f32.nxv8i8(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv1f32.nxv8i8(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg2_nxv1f32_nxv8i8(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv1f32_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv1f32.nxv8i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv1f32_nxv8i8(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv1f32_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv1f32.nxv8i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv1f32.nxv4i64(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i64>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv1f32.nxv4i64(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg2_nxv1f32_nxv4i64(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv1f32_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv1f32.nxv4i64(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv1f32_nxv4i64(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv1f32_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv1f32.nxv4i64(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv1f32.nxv64i8(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 64 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv1f32.nxv64i8(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 64 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg2_nxv1f32_nxv64i8(<vscale x 1 x float> %val, float* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv1f32_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv1f32.nxv64i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 64 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv1f32_nxv64i8(<vscale x 1 x float> %val, float* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv1f32_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv1f32.nxv64i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv1f32.nxv4i16(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i16>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv1f32.nxv4i16(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg2_nxv1f32_nxv4i16(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv1f32_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv1f32.nxv4i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv1f32_nxv4i16(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv1f32_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv1f32.nxv4i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv1f32.nxv8i64(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i64>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv1f32.nxv8i64(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg2_nxv1f32_nxv8i64(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv1f32_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv1f32.nxv8i64(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv1f32_nxv8i64(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv1f32_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv1f32.nxv8i64(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv1f32.nxv1i8(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv1f32.nxv1i8(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg2_nxv1f32_nxv1i8(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv1f32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv1f32.nxv1i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv1f32_nxv1i8(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv1f32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv1f32.nxv1i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv1f32.nxv2i8(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv1f32.nxv2i8(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg2_nxv1f32_nxv2i8(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv1f32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv1f32.nxv2i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv1f32_nxv2i8(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv1f32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv1f32.nxv2i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv1f32.nxv8i32(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i32>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv1f32.nxv8i32(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg2_nxv1f32_nxv8i32(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv1f32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv1f32.nxv8i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv1f32_nxv8i32(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv1f32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv1f32.nxv8i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv1f32.nxv32i8(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 32 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv1f32.nxv32i8(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 32 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg2_nxv1f32_nxv32i8(<vscale x 1 x float> %val, float* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv1f32_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv1f32.nxv32i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 32 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv1f32_nxv32i8(<vscale x 1 x float> %val, float* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv1f32_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv1f32.nxv32i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv1f32.nxv16i32(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i32>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv1f32.nxv16i32(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg2_nxv1f32_nxv16i32(<vscale x 1 x float> %val, float* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv1f32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv1f32.nxv16i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 16 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv1f32_nxv16i32(<vscale x 1 x float> %val, float* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv1f32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv1f32.nxv16i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv1f32.nxv2i16(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i16>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv1f32.nxv2i16(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg2_nxv1f32_nxv2i16(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv1f32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv1f32.nxv2i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv1f32_nxv2i16(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv1f32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv1f32.nxv2i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv1f32.nxv2i64(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i64>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv1f32.nxv2i64(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg2_nxv1f32_nxv2i64(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv1f32_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv1f32.nxv2i64(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv1f32_nxv2i64(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv1f32_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv1f32.nxv2i64(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv1f32.nxv16i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i16>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv1f32.nxv16i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg3_nxv1f32_nxv16i16(<vscale x 1 x float> %val, float* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv1f32_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv1f32.nxv16i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 16 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv1f32_nxv16i16(<vscale x 1 x float> %val, float* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv1f32_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv1f32.nxv16i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv1f32.nxv32i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 32 x i16>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv1f32.nxv32i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 32 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg3_nxv1f32_nxv32i16(<vscale x 1 x float> %val, float* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv1f32_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv1f32.nxv32i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 32 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv1f32_nxv32i16(<vscale x 1 x float> %val, float* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv1f32_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv1f32.nxv32i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv1f32.nxv4i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i32>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv1f32.nxv4i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg3_nxv1f32_nxv4i32(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv1f32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv1f32.nxv4i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv1f32_nxv4i32(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv1f32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv1f32.nxv4i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv1f32.nxv16i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i8>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv1f32.nxv16i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg3_nxv1f32_nxv16i8(<vscale x 1 x float> %val, float* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv1f32_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv1f32.nxv16i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 16 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv1f32_nxv16i8(<vscale x 1 x float> %val, float* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv1f32_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv1f32.nxv16i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv1f32.nxv1i64(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv1f32.nxv1i64(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg3_nxv1f32_nxv1i64(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv1f32_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei64.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv1f32.nxv1i64(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv1f32_nxv1i64(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv1f32_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei64.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv1f32.nxv1i64(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv1f32.nxv1i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv1f32.nxv1i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg3_nxv1f32_nxv1i32(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv1f32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv1f32.nxv1i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv1f32_nxv1i32(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv1f32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv1f32.nxv1i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv1f32.nxv8i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i16>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv1f32.nxv8i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg3_nxv1f32_nxv8i16(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv1f32_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv1f32.nxv8i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv1f32_nxv8i16(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv1f32_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv1f32.nxv8i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv1f32.nxv4i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i8>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv1f32.nxv4i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg3_nxv1f32_nxv4i8(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv1f32_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv1f32.nxv4i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv1f32_nxv4i8(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv1f32_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv1f32.nxv4i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv1f32.nxv1i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv1f32.nxv1i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg3_nxv1f32_nxv1i16(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv1f32_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv1f32.nxv1i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv1f32_nxv1i16(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv1f32_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv1f32.nxv1i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv1f32.nxv2i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i32>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv1f32.nxv2i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg3_nxv1f32_nxv2i32(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv1f32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv1f32.nxv2i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv1f32_nxv2i32(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv1f32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv1f32.nxv2i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv1f32.nxv8i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i8>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv1f32.nxv8i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg3_nxv1f32_nxv8i8(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv1f32_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv1f32.nxv8i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv1f32_nxv8i8(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv1f32_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv1f32.nxv8i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv1f32.nxv4i64(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i64>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv1f32.nxv4i64(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg3_nxv1f32_nxv4i64(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv1f32_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei64.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv1f32.nxv4i64(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv1f32_nxv4i64(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv1f32_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei64.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv1f32.nxv4i64(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv1f32.nxv64i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 64 x i8>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv1f32.nxv64i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 64 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg3_nxv1f32_nxv64i8(<vscale x 1 x float> %val, float* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv1f32_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv1f32.nxv64i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 64 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv1f32_nxv64i8(<vscale x 1 x float> %val, float* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv1f32_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv1f32.nxv64i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv1f32.nxv4i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i16>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv1f32.nxv4i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg3_nxv1f32_nxv4i16(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv1f32_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv1f32.nxv4i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv1f32_nxv4i16(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv1f32_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv1f32.nxv4i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv1f32.nxv8i64(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i64>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv1f32.nxv8i64(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg3_nxv1f32_nxv8i64(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv1f32_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei64.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv1f32.nxv8i64(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv1f32_nxv8i64(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv1f32_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei64.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv1f32.nxv8i64(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv1f32.nxv1i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv1f32.nxv1i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg3_nxv1f32_nxv1i8(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv1f32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv1f32.nxv1i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv1f32_nxv1i8(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv1f32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv1f32.nxv1i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv1f32.nxv2i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i8>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv1f32.nxv2i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg3_nxv1f32_nxv2i8(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv1f32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv1f32.nxv2i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv1f32_nxv2i8(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv1f32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv1f32.nxv2i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv1f32.nxv8i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i32>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv1f32.nxv8i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg3_nxv1f32_nxv8i32(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv1f32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv1f32.nxv8i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv1f32_nxv8i32(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv1f32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv1f32.nxv8i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv1f32.nxv32i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 32 x i8>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv1f32.nxv32i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 32 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg3_nxv1f32_nxv32i8(<vscale x 1 x float> %val, float* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv1f32_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv1f32.nxv32i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 32 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv1f32_nxv32i8(<vscale x 1 x float> %val, float* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv1f32_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv1f32.nxv32i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv1f32.nxv16i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i32>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv1f32.nxv16i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg3_nxv1f32_nxv16i32(<vscale x 1 x float> %val, float* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv1f32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv1f32.nxv16i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 16 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv1f32_nxv16i32(<vscale x 1 x float> %val, float* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv1f32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv1f32.nxv16i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv1f32.nxv2i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i16>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv1f32.nxv2i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg3_nxv1f32_nxv2i16(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv1f32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv1f32.nxv2i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv1f32_nxv2i16(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv1f32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv1f32.nxv2i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv1f32.nxv2i64(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i64>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv1f32.nxv2i64(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg3_nxv1f32_nxv2i64(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv1f32_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei64.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv1f32.nxv2i64(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv1f32_nxv2i64(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv1f32_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei64.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv1f32.nxv2i64(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv1f32.nxv16i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i16>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv1f32.nxv16i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg4_nxv1f32_nxv16i16(<vscale x 1 x float> %val, float* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv1f32_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv1f32.nxv16i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 16 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv1f32_nxv16i16(<vscale x 1 x float> %val, float* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv1f32_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv1f32.nxv16i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv1f32.nxv32i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 32 x i16>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv1f32.nxv32i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 32 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg4_nxv1f32_nxv32i16(<vscale x 1 x float> %val, float* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv1f32_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv1f32.nxv32i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 32 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv1f32_nxv32i16(<vscale x 1 x float> %val, float* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv1f32_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv1f32.nxv32i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv1f32.nxv4i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i32>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv1f32.nxv4i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg4_nxv1f32_nxv4i32(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv1f32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv1f32.nxv4i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv1f32_nxv4i32(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv1f32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv1f32.nxv4i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv1f32.nxv16i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i8>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv1f32.nxv16i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg4_nxv1f32_nxv16i8(<vscale x 1 x float> %val, float* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv1f32_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv1f32.nxv16i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 16 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv1f32_nxv16i8(<vscale x 1 x float> %val, float* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv1f32_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv1f32.nxv16i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv1f32.nxv1i64(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv1f32.nxv1i64(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg4_nxv1f32_nxv1i64(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv1f32_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei64.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv1f32.nxv1i64(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv1f32_nxv1i64(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv1f32_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei64.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv1f32.nxv1i64(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv1f32.nxv1i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv1f32.nxv1i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg4_nxv1f32_nxv1i32(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv1f32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv1f32.nxv1i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv1f32_nxv1i32(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv1f32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv1f32.nxv1i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv1f32.nxv8i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i16>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv1f32.nxv8i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg4_nxv1f32_nxv8i16(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv1f32_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv1f32.nxv8i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv1f32_nxv8i16(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv1f32_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv1f32.nxv8i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv1f32.nxv4i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i8>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv1f32.nxv4i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg4_nxv1f32_nxv4i8(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv1f32_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv1f32.nxv4i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv1f32_nxv4i8(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv1f32_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv1f32.nxv4i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv1f32.nxv1i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv1f32.nxv1i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg4_nxv1f32_nxv1i16(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv1f32_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv1f32.nxv1i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv1f32_nxv1i16(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv1f32_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv1f32.nxv1i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv1f32.nxv2i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i32>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv1f32.nxv2i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg4_nxv1f32_nxv2i32(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv1f32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv1f32.nxv2i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv1f32_nxv2i32(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv1f32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv1f32.nxv2i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv1f32.nxv8i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i8>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv1f32.nxv8i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg4_nxv1f32_nxv8i8(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv1f32_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv1f32.nxv8i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv1f32_nxv8i8(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv1f32_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv1f32.nxv8i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv1f32.nxv4i64(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i64>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv1f32.nxv4i64(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg4_nxv1f32_nxv4i64(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv1f32_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei64.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv1f32.nxv4i64(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv1f32_nxv4i64(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv1f32_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei64.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv1f32.nxv4i64(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv1f32.nxv64i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 64 x i8>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv1f32.nxv64i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 64 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg4_nxv1f32_nxv64i8(<vscale x 1 x float> %val, float* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv1f32_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv1f32.nxv64i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 64 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv1f32_nxv64i8(<vscale x 1 x float> %val, float* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv1f32_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv1f32.nxv64i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv1f32.nxv4i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i16>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv1f32.nxv4i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg4_nxv1f32_nxv4i16(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv1f32_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv1f32.nxv4i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv1f32_nxv4i16(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv1f32_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv1f32.nxv4i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv1f32.nxv8i64(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i64>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv1f32.nxv8i64(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg4_nxv1f32_nxv8i64(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv1f32_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei64.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv1f32.nxv8i64(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv1f32_nxv8i64(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv1f32_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei64.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv1f32.nxv8i64(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv1f32.nxv1i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv1f32.nxv1i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg4_nxv1f32_nxv1i8(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv1f32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv1f32.nxv1i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv1f32_nxv1i8(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv1f32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv1f32.nxv1i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv1f32.nxv2i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i8>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv1f32.nxv2i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg4_nxv1f32_nxv2i8(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv1f32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv1f32.nxv2i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv1f32_nxv2i8(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv1f32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv1f32.nxv2i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv1f32.nxv8i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i32>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv1f32.nxv8i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg4_nxv1f32_nxv8i32(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv1f32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv1f32.nxv8i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv1f32_nxv8i32(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv1f32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv1f32.nxv8i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv1f32.nxv32i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 32 x i8>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv1f32.nxv32i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 32 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg4_nxv1f32_nxv32i8(<vscale x 1 x float> %val, float* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv1f32_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv1f32.nxv32i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 32 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv1f32_nxv32i8(<vscale x 1 x float> %val, float* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv1f32_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv1f32.nxv32i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv1f32.nxv16i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i32>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv1f32.nxv16i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg4_nxv1f32_nxv16i32(<vscale x 1 x float> %val, float* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv1f32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv1f32.nxv16i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 16 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv1f32_nxv16i32(<vscale x 1 x float> %val, float* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv1f32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv1f32.nxv16i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv1f32.nxv2i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i16>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv1f32.nxv2i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg4_nxv1f32_nxv2i16(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv1f32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv1f32.nxv2i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv1f32_nxv2i16(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv1f32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv1f32.nxv2i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv1f32.nxv2i64(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i64>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv1f32.nxv2i64(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg4_nxv1f32_nxv2i64(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv1f32_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei64.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv1f32.nxv2i64(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv1f32_nxv2i64(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv1f32_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei64.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv1f32.nxv2i64(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv1f32.nxv16i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i16>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv1f32.nxv16i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg5_nxv1f32_nxv16i16(<vscale x 1 x float> %val, float* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv1f32_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv1f32.nxv16i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 16 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv1f32_nxv16i16(<vscale x 1 x float> %val, float* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv1f32_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv1f32.nxv16i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv1f32.nxv32i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 32 x i16>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv1f32.nxv32i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 32 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg5_nxv1f32_nxv32i16(<vscale x 1 x float> %val, float* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv1f32_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv1f32.nxv32i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 32 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv1f32_nxv32i16(<vscale x 1 x float> %val, float* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv1f32_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv1f32.nxv32i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv1f32.nxv4i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i32>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv1f32.nxv4i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg5_nxv1f32_nxv4i32(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv1f32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei32.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv1f32.nxv4i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv1f32_nxv4i32(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv1f32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei32.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv1f32.nxv4i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv1f32.nxv16i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i8>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv1f32.nxv16i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg5_nxv1f32_nxv16i8(<vscale x 1 x float> %val, float* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv1f32_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv1f32.nxv16i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 16 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv1f32_nxv16i8(<vscale x 1 x float> %val, float* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv1f32_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv1f32.nxv16i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv1f32.nxv1i64(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv1f32.nxv1i64(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg5_nxv1f32_nxv1i64(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv1f32_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei64.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv1f32.nxv1i64(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv1f32_nxv1i64(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv1f32_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei64.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv1f32.nxv1i64(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv1f32.nxv1i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv1f32.nxv1i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg5_nxv1f32_nxv1i32(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv1f32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv1f32.nxv1i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv1f32_nxv1i32(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv1f32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv1f32.nxv1i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv1f32.nxv8i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i16>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv1f32.nxv8i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg5_nxv1f32_nxv8i16(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv1f32_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv1f32.nxv8i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv1f32_nxv8i16(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv1f32_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv1f32.nxv8i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv1f32.nxv4i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i8>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv1f32.nxv4i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg5_nxv1f32_nxv4i8(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv1f32_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv1f32.nxv4i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv1f32_nxv4i8(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv1f32_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv1f32.nxv4i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv1f32.nxv1i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv1f32.nxv1i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg5_nxv1f32_nxv1i16(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv1f32_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv1f32.nxv1i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv1f32_nxv1i16(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv1f32_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv1f32.nxv1i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv1f32.nxv2i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i32>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv1f32.nxv2i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg5_nxv1f32_nxv2i32(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv1f32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv1f32.nxv2i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv1f32_nxv2i32(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv1f32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv1f32.nxv2i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv1f32.nxv8i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i8>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv1f32.nxv8i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg5_nxv1f32_nxv8i8(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv1f32_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv1f32.nxv8i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv1f32_nxv8i8(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv1f32_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv1f32.nxv8i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv1f32.nxv4i64(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i64>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv1f32.nxv4i64(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg5_nxv1f32_nxv4i64(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv1f32_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei64.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv1f32.nxv4i64(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv1f32_nxv4i64(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv1f32_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei64.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv1f32.nxv4i64(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv1f32.nxv64i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 64 x i8>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv1f32.nxv64i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 64 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg5_nxv1f32_nxv64i8(<vscale x 1 x float> %val, float* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv1f32_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv1f32.nxv64i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 64 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv1f32_nxv64i8(<vscale x 1 x float> %val, float* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv1f32_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv1f32.nxv64i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv1f32.nxv4i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i16>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv1f32.nxv4i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg5_nxv1f32_nxv4i16(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv1f32_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv1f32.nxv4i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv1f32_nxv4i16(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv1f32_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv1f32.nxv4i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv1f32.nxv8i64(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i64>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv1f32.nxv8i64(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg5_nxv1f32_nxv8i64(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv1f32_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei64.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv1f32.nxv8i64(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv1f32_nxv8i64(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv1f32_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei64.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv1f32.nxv8i64(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv1f32.nxv1i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv1f32.nxv1i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg5_nxv1f32_nxv1i8(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv1f32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv1f32.nxv1i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv1f32_nxv1i8(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv1f32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv1f32.nxv1i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv1f32.nxv2i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i8>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv1f32.nxv2i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg5_nxv1f32_nxv2i8(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv1f32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv1f32.nxv2i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv1f32_nxv2i8(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv1f32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv1f32.nxv2i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv1f32.nxv8i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i32>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv1f32.nxv8i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg5_nxv1f32_nxv8i32(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv1f32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei32.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv1f32.nxv8i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv1f32_nxv8i32(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv1f32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei32.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv1f32.nxv8i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv1f32.nxv32i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 32 x i8>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv1f32.nxv32i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 32 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg5_nxv1f32_nxv32i8(<vscale x 1 x float> %val, float* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv1f32_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv1f32.nxv32i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 32 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv1f32_nxv32i8(<vscale x 1 x float> %val, float* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv1f32_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv1f32.nxv32i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv1f32.nxv16i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i32>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv1f32.nxv16i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg5_nxv1f32_nxv16i32(<vscale x 1 x float> %val, float* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv1f32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei32.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv1f32.nxv16i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 16 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv1f32_nxv16i32(<vscale x 1 x float> %val, float* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv1f32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei32.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv1f32.nxv16i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv1f32.nxv2i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i16>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv1f32.nxv2i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg5_nxv1f32_nxv2i16(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv1f32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv1f32.nxv2i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv1f32_nxv2i16(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv1f32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv1f32.nxv2i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv1f32.nxv2i64(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i64>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv1f32.nxv2i64(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg5_nxv1f32_nxv2i64(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv1f32_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei64.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv1f32.nxv2i64(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv1f32_nxv2i64(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv1f32_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei64.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv1f32.nxv2i64(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv1f32.nxv16i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i16>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv1f32.nxv16i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg6_nxv1f32_nxv16i16(<vscale x 1 x float> %val, float* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv1f32_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv1f32.nxv16i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 16 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv1f32_nxv16i16(<vscale x 1 x float> %val, float* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv1f32_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv1f32.nxv16i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv1f32.nxv32i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 32 x i16>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv1f32.nxv32i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 32 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg6_nxv1f32_nxv32i16(<vscale x 1 x float> %val, float* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv1f32_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv1f32.nxv32i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 32 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv1f32_nxv32i16(<vscale x 1 x float> %val, float* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv1f32_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv1f32.nxv32i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv1f32.nxv4i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i32>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv1f32.nxv4i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg6_nxv1f32_nxv4i32(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv1f32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei32.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv1f32.nxv4i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv1f32_nxv4i32(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv1f32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei32.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv1f32.nxv4i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv1f32.nxv16i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i8>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv1f32.nxv16i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg6_nxv1f32_nxv16i8(<vscale x 1 x float> %val, float* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv1f32_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv1f32.nxv16i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 16 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv1f32_nxv16i8(<vscale x 1 x float> %val, float* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv1f32_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv1f32.nxv16i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv1f32.nxv1i64(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv1f32.nxv1i64(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg6_nxv1f32_nxv1i64(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv1f32_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei64.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv1f32.nxv1i64(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv1f32_nxv1i64(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv1f32_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei64.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv1f32.nxv1i64(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv1f32.nxv1i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv1f32.nxv1i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg6_nxv1f32_nxv1i32(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv1f32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv1f32.nxv1i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv1f32_nxv1i32(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv1f32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv1f32.nxv1i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv1f32.nxv8i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i16>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv1f32.nxv8i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg6_nxv1f32_nxv8i16(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv1f32_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv1f32.nxv8i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv1f32_nxv8i16(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv1f32_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv1f32.nxv8i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv1f32.nxv4i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i8>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv1f32.nxv4i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg6_nxv1f32_nxv4i8(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv1f32_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv1f32.nxv4i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv1f32_nxv4i8(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv1f32_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv1f32.nxv4i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv1f32.nxv1i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv1f32.nxv1i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg6_nxv1f32_nxv1i16(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv1f32_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv1f32.nxv1i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv1f32_nxv1i16(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv1f32_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv1f32.nxv1i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv1f32.nxv2i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i32>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv1f32.nxv2i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg6_nxv1f32_nxv2i32(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv1f32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv1f32.nxv2i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv1f32_nxv2i32(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv1f32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv1f32.nxv2i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv1f32.nxv8i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i8>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv1f32.nxv8i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg6_nxv1f32_nxv8i8(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv1f32_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv1f32.nxv8i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv1f32_nxv8i8(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv1f32_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv1f32.nxv8i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv1f32.nxv4i64(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i64>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv1f32.nxv4i64(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg6_nxv1f32_nxv4i64(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv1f32_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei64.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv1f32.nxv4i64(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv1f32_nxv4i64(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv1f32_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei64.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv1f32.nxv4i64(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv1f32.nxv64i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 64 x i8>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv1f32.nxv64i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 64 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg6_nxv1f32_nxv64i8(<vscale x 1 x float> %val, float* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv1f32_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv1f32.nxv64i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 64 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv1f32_nxv64i8(<vscale x 1 x float> %val, float* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv1f32_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv1f32.nxv64i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv1f32.nxv4i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i16>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv1f32.nxv4i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg6_nxv1f32_nxv4i16(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv1f32_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv1f32.nxv4i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv1f32_nxv4i16(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv1f32_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv1f32.nxv4i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv1f32.nxv8i64(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i64>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv1f32.nxv8i64(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg6_nxv1f32_nxv8i64(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv1f32_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei64.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv1f32.nxv8i64(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv1f32_nxv8i64(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv1f32_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei64.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv1f32.nxv8i64(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv1f32.nxv1i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv1f32.nxv1i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg6_nxv1f32_nxv1i8(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv1f32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv1f32.nxv1i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv1f32_nxv1i8(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv1f32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv1f32.nxv1i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv1f32.nxv2i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i8>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv1f32.nxv2i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg6_nxv1f32_nxv2i8(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv1f32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv1f32.nxv2i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv1f32_nxv2i8(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv1f32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv1f32.nxv2i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv1f32.nxv8i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i32>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv1f32.nxv8i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg6_nxv1f32_nxv8i32(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv1f32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei32.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv1f32.nxv8i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv1f32_nxv8i32(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv1f32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei32.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv1f32.nxv8i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv1f32.nxv32i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 32 x i8>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv1f32.nxv32i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 32 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg6_nxv1f32_nxv32i8(<vscale x 1 x float> %val, float* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv1f32_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv1f32.nxv32i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 32 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv1f32_nxv32i8(<vscale x 1 x float> %val, float* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv1f32_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv1f32.nxv32i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv1f32.nxv16i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i32>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv1f32.nxv16i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg6_nxv1f32_nxv16i32(<vscale x 1 x float> %val, float* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv1f32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei32.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv1f32.nxv16i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 16 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv1f32_nxv16i32(<vscale x 1 x float> %val, float* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv1f32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei32.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv1f32.nxv16i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv1f32.nxv2i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i16>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv1f32.nxv2i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg6_nxv1f32_nxv2i16(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv1f32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv1f32.nxv2i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv1f32_nxv2i16(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv1f32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv1f32.nxv2i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv1f32.nxv2i64(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i64>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv1f32.nxv2i64(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg6_nxv1f32_nxv2i64(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv1f32_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei64.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv1f32.nxv2i64(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv1f32_nxv2i64(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv1f32_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei64.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv1f32.nxv2i64(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv1f32.nxv16i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i16>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv1f32.nxv16i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg7_nxv1f32_nxv16i16(<vscale x 1 x float> %val, float* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv1f32_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv1f32.nxv16i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 16 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv1f32_nxv16i16(<vscale x 1 x float> %val, float* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv1f32_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv1f32.nxv16i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv1f32.nxv32i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 32 x i16>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv1f32.nxv32i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 32 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg7_nxv1f32_nxv32i16(<vscale x 1 x float> %val, float* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv1f32_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv1f32.nxv32i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 32 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv1f32_nxv32i16(<vscale x 1 x float> %val, float* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv1f32_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv1f32.nxv32i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv1f32.nxv4i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i32>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv1f32.nxv4i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg7_nxv1f32_nxv4i32(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv1f32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei32.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv1f32.nxv4i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv1f32_nxv4i32(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv1f32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei32.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv1f32.nxv4i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv1f32.nxv16i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i8>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv1f32.nxv16i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg7_nxv1f32_nxv16i8(<vscale x 1 x float> %val, float* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv1f32_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv1f32.nxv16i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 16 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv1f32_nxv16i8(<vscale x 1 x float> %val, float* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv1f32_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv1f32.nxv16i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv1f32.nxv1i64(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv1f32.nxv1i64(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg7_nxv1f32_nxv1i64(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv1f32_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei64.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv1f32.nxv1i64(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv1f32_nxv1i64(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv1f32_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei64.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv1f32.nxv1i64(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv1f32.nxv1i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv1f32.nxv1i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg7_nxv1f32_nxv1i32(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv1f32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv1f32.nxv1i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv1f32_nxv1i32(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv1f32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv1f32.nxv1i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv1f32.nxv8i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i16>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv1f32.nxv8i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg7_nxv1f32_nxv8i16(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv1f32_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv1f32.nxv8i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv1f32_nxv8i16(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv1f32_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv1f32.nxv8i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv1f32.nxv4i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i8>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv1f32.nxv4i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg7_nxv1f32_nxv4i8(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv1f32_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv1f32.nxv4i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv1f32_nxv4i8(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv1f32_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv1f32.nxv4i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv1f32.nxv1i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv1f32.nxv1i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg7_nxv1f32_nxv1i16(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv1f32_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv1f32.nxv1i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv1f32_nxv1i16(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv1f32_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv1f32.nxv1i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv1f32.nxv2i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i32>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv1f32.nxv2i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg7_nxv1f32_nxv2i32(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv1f32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv1f32.nxv2i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv1f32_nxv2i32(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv1f32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv1f32.nxv2i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv1f32.nxv8i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i8>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv1f32.nxv8i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg7_nxv1f32_nxv8i8(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv1f32_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv1f32.nxv8i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv1f32_nxv8i8(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv1f32_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv1f32.nxv8i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv1f32.nxv4i64(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i64>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv1f32.nxv4i64(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg7_nxv1f32_nxv4i64(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv1f32_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei64.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv1f32.nxv4i64(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv1f32_nxv4i64(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv1f32_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei64.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv1f32.nxv4i64(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv1f32.nxv64i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 64 x i8>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv1f32.nxv64i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 64 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg7_nxv1f32_nxv64i8(<vscale x 1 x float> %val, float* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv1f32_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv1f32.nxv64i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 64 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv1f32_nxv64i8(<vscale x 1 x float> %val, float* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv1f32_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv1f32.nxv64i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv1f32.nxv4i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i16>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv1f32.nxv4i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg7_nxv1f32_nxv4i16(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv1f32_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv1f32.nxv4i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv1f32_nxv4i16(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv1f32_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv1f32.nxv4i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv1f32.nxv8i64(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i64>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv1f32.nxv8i64(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg7_nxv1f32_nxv8i64(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv1f32_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei64.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv1f32.nxv8i64(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv1f32_nxv8i64(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv1f32_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei64.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv1f32.nxv8i64(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv1f32.nxv1i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv1f32.nxv1i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg7_nxv1f32_nxv1i8(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv1f32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv1f32.nxv1i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv1f32_nxv1i8(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv1f32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv1f32.nxv1i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv1f32.nxv2i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i8>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv1f32.nxv2i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg7_nxv1f32_nxv2i8(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv1f32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv1f32.nxv2i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv1f32_nxv2i8(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv1f32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv1f32.nxv2i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv1f32.nxv8i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i32>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv1f32.nxv8i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg7_nxv1f32_nxv8i32(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv1f32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei32.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv1f32.nxv8i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv1f32_nxv8i32(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv1f32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei32.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv1f32.nxv8i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv1f32.nxv32i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 32 x i8>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv1f32.nxv32i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 32 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg7_nxv1f32_nxv32i8(<vscale x 1 x float> %val, float* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv1f32_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv1f32.nxv32i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 32 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv1f32_nxv32i8(<vscale x 1 x float> %val, float* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv1f32_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv1f32.nxv32i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv1f32.nxv16i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i32>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv1f32.nxv16i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg7_nxv1f32_nxv16i32(<vscale x 1 x float> %val, float* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv1f32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei32.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv1f32.nxv16i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 16 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv1f32_nxv16i32(<vscale x 1 x float> %val, float* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv1f32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei32.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv1f32.nxv16i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv1f32.nxv2i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i16>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv1f32.nxv2i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg7_nxv1f32_nxv2i16(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv1f32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv1f32.nxv2i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv1f32_nxv2i16(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv1f32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv1f32.nxv2i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv1f32.nxv2i64(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i64>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv1f32.nxv2i64(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg7_nxv1f32_nxv2i64(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv1f32_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei64.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv1f32.nxv2i64(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv1f32_nxv2i64(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv1f32_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei64.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv1f32.nxv2i64(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv1f32.nxv16i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i16>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv1f32.nxv16i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg8_nxv1f32_nxv16i16(<vscale x 1 x float> %val, float* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv1f32_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv1f32.nxv16i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 16 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv1f32_nxv16i16(<vscale x 1 x float> %val, float* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv1f32_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv1f32.nxv16i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 16 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv1f32.nxv32i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 32 x i16>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv1f32.nxv32i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 32 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg8_nxv1f32_nxv32i16(<vscale x 1 x float> %val, float* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv1f32_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vmv1r.v v23, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv1f32.nxv32i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 32 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv1f32_nxv32i16(<vscale x 1 x float> %val, float* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv1f32_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vmv1r.v v23, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv1f32.nxv32i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 32 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv1f32.nxv4i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i32>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv1f32.nxv4i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg8_nxv1f32_nxv4i32(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv1f32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei32.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv1f32.nxv4i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv1f32_nxv4i32(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv1f32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei32.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv1f32.nxv4i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv1f32.nxv16i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i8>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv1f32.nxv16i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg8_nxv1f32_nxv16i8(<vscale x 1 x float> %val, float* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv1f32_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv1f32.nxv16i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 16 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv1f32_nxv16i8(<vscale x 1 x float> %val, float* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv1f32_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv1f32.nxv16i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 16 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv1f32.nxv1i64(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv1f32.nxv1i64(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg8_nxv1f32_nxv1i64(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv1f32_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei64.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv1f32.nxv1i64(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv1f32_nxv1i64(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv1f32_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei64.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv1f32.nxv1i64(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv1f32.nxv1i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv1f32.nxv1i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg8_nxv1f32_nxv1i32(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv1f32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv1f32.nxv1i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv1f32_nxv1i32(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv1f32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv1f32.nxv1i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv1f32.nxv8i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i16>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv1f32.nxv8i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg8_nxv1f32_nxv8i16(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv1f32_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv1f32.nxv8i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv1f32_nxv8i16(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv1f32_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv1f32.nxv8i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv1f32.nxv4i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i8>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv1f32.nxv4i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg8_nxv1f32_nxv4i8(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv1f32_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv1f32.nxv4i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv1f32_nxv4i8(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv1f32_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv1f32.nxv4i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv1f32.nxv1i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv1f32.nxv1i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg8_nxv1f32_nxv1i16(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv1f32_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv1f32.nxv1i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv1f32_nxv1i16(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv1f32_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv1f32.nxv1i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv1f32.nxv2i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i32>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv1f32.nxv2i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg8_nxv1f32_nxv2i32(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv1f32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv1f32.nxv2i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv1f32_nxv2i32(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv1f32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv1f32.nxv2i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv1f32.nxv8i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i8>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv1f32.nxv8i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg8_nxv1f32_nxv8i8(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv1f32_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv1f32.nxv8i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv1f32_nxv8i8(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv1f32_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv1f32.nxv8i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv1f32.nxv4i64(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i64>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv1f32.nxv4i64(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg8_nxv1f32_nxv4i64(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv1f32_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei64.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv1f32.nxv4i64(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv1f32_nxv4i64(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv1f32_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei64.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv1f32.nxv4i64(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv1f32.nxv64i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 64 x i8>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv1f32.nxv64i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 64 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg8_nxv1f32_nxv64i8(<vscale x 1 x float> %val, float* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv1f32_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vmv1r.v v23, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv1f32.nxv64i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 64 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv1f32_nxv64i8(<vscale x 1 x float> %val, float* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv1f32_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vmv1r.v v23, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv1f32.nxv64i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 64 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv1f32.nxv4i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i16>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv1f32.nxv4i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 4 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg8_nxv1f32_nxv4i16(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv1f32_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv1f32.nxv4i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv1f32_nxv4i16(<vscale x 1 x float> %val, float* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv1f32_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv1f32.nxv4i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 4 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv1f32.nxv8i64(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i64>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv1f32.nxv8i64(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg8_nxv1f32_nxv8i64(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv1f32_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vmv1r.v v23, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei64.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv1f32.nxv8i64(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv1f32_nxv8i64(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv1f32_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vmv1r.v v23, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei64.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv1f32.nxv8i64(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv1f32.nxv1i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv1f32.nxv1i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg8_nxv1f32_nxv1i8(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv1f32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv1f32.nxv1i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv1f32_nxv1i8(<vscale x 1 x float> %val, float* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv1f32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv1f32.nxv1i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv1f32.nxv2i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i8>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv1f32.nxv2i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg8_nxv1f32_nxv2i8(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv1f32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv1f32.nxv2i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv1f32_nxv2i8(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv1f32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv1f32.nxv2i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv1f32.nxv8i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i32>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv1f32.nxv8i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 8 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg8_nxv1f32_nxv8i32(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv1f32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei32.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv1f32.nxv8i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv1f32_nxv8i32(<vscale x 1 x float> %val, float* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv1f32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei32.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv1f32.nxv8i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 8 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv1f32.nxv32i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 32 x i8>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv1f32.nxv32i8(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 32 x i8>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg8_nxv1f32_nxv32i8(<vscale x 1 x float> %val, float* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv1f32_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv1f32.nxv32i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 32 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv1f32_nxv32i8(<vscale x 1 x float> %val, float* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv1f32_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv1f32.nxv32i8(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 32 x i8> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv1f32.nxv16i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i32>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv1f32.nxv16i32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 16 x i32>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg8_nxv1f32_nxv16i32(<vscale x 1 x float> %val, float* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv1f32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vmv1r.v v23, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei32.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv1f32.nxv16i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 16 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv1f32_nxv16i32(<vscale x 1 x float> %val, float* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv1f32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vmv1r.v v23, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei32.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv1f32.nxv16i32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 16 x i32> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv1f32.nxv2i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i16>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv1f32.nxv2i16(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i16>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg8_nxv1f32_nxv2i16(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv1f32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv1f32.nxv2i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv1f32_nxv2i16(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv1f32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv1f32.nxv2i16(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv1f32.nxv2i64(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i64>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv1f32.nxv2i64(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 2 x i64>, <vscale x 1 x i1>, i64)
+
+define void @test_vsxseg8_nxv1f32_nxv2i64(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv1f32_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei64.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv1f32.nxv2i64(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv1f32_nxv2i64(<vscale x 1 x float> %val, float* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv1f32_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei64.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv1f32.nxv2i64(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 2 x i64> %index, <vscale x 1 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv8f16.nxv16i16(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 16 x i16>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv8f16.nxv16i16(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 16 x i16>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg2_nxv8f16_nxv16i16(<vscale x 8 x half> %val, half* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv8f16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv8f16.nxv16i16(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 16 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv8f16_nxv16i16(<vscale x 8 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv8f16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv8f16.nxv16i16(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv8f16.nxv32i16(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 32 x i16>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv8f16.nxv32i16(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 32 x i16>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg2_nxv8f16_nxv32i16(<vscale x 8 x half> %val, half* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv8f16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv8f16.nxv32i16(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 32 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv8f16_nxv32i16(<vscale x 8 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv8f16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv8f16.nxv32i16(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv8f16.nxv4i32(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 4 x i32>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv8f16.nxv4i32(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 4 x i32>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg2_nxv8f16_nxv4i32(<vscale x 8 x half> %val, half* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv8f16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv2r.v v26, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v26
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv8f16.nxv4i32(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 4 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv8f16_nxv4i32(<vscale x 8 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv8f16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv2r.v v26, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v26, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv8f16.nxv4i32(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv8f16.nxv16i8(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 16 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv8f16.nxv16i8(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 16 x i8>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg2_nxv8f16_nxv16i8(<vscale x 8 x half> %val, half* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv8f16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv2r.v v26, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v26
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv8f16.nxv16i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 16 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv8f16_nxv16i8(<vscale x 8 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv8f16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv2r.v v26, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v26, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv8f16.nxv16i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv8f16.nxv1i64(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv8f16.nxv1i64(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 1 x i64>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg2_nxv8f16_nxv1i64(<vscale x 8 x half> %val, half* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv8f16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv1r.v v25, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv8f16.nxv1i64(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 1 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv8f16_nxv1i64(<vscale x 8 x half> %val, half* %base, <vscale x 1 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv8f16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv1r.v v25, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv8f16.nxv1i64(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 1 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv8f16.nxv1i32(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv8f16.nxv1i32(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 1 x i32>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg2_nxv8f16_nxv1i32(<vscale x 8 x half> %val, half* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv8f16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv1r.v v25, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv8f16.nxv1i32(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 1 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv8f16_nxv1i32(<vscale x 8 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv8f16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv1r.v v25, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv8f16.nxv1i32(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv8f16.nxv8i16(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 8 x i16>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv8f16.nxv8i16(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 8 x i16>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg2_nxv8f16_nxv8i16(<vscale x 8 x half> %val, half* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv8f16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv2r.v v26, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v26
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv8f16.nxv8i16(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 8 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv8f16_nxv8i16(<vscale x 8 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv8f16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv2r.v v26, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v26, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv8f16.nxv8i16(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv8f16.nxv4i8(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 4 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv8f16.nxv4i8(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 4 x i8>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg2_nxv8f16_nxv4i8(<vscale x 8 x half> %val, half* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv8f16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv1r.v v25, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv8f16.nxv4i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 4 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv8f16_nxv4i8(<vscale x 8 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv8f16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv1r.v v25, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv8f16.nxv4i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv8f16.nxv1i16(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv8f16.nxv1i16(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 1 x i16>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg2_nxv8f16_nxv1i16(<vscale x 8 x half> %val, half* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv8f16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv1r.v v25, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv8f16.nxv1i16(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 1 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv8f16_nxv1i16(<vscale x 8 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv8f16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv1r.v v25, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv8f16.nxv1i16(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv8f16.nxv2i32(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 2 x i32>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv8f16.nxv2i32(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 2 x i32>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg2_nxv8f16_nxv2i32(<vscale x 8 x half> %val, half* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv8f16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv1r.v v25, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv8f16.nxv2i32(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 2 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv8f16_nxv2i32(<vscale x 8 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv8f16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv1r.v v25, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv8f16.nxv2i32(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv8f16.nxv8i8(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 8 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv8f16.nxv8i8(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 8 x i8>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg2_nxv8f16_nxv8i8(<vscale x 8 x half> %val, half* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv8f16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv1r.v v25, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv8f16.nxv8i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 8 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv8f16_nxv8i8(<vscale x 8 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv8f16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv1r.v v25, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv8f16.nxv8i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv8f16.nxv4i64(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 4 x i64>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv8f16.nxv4i64(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 4 x i64>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg2_nxv8f16_nxv4i64(<vscale x 8 x half> %val, half* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv8f16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv8f16.nxv4i64(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 4 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv8f16_nxv4i64(<vscale x 8 x half> %val, half* %base, <vscale x 4 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv8f16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv8f16.nxv4i64(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 4 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv8f16.nxv64i8(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 64 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv8f16.nxv64i8(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 64 x i8>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg2_nxv8f16_nxv64i8(<vscale x 8 x half> %val, half* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv8f16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv8f16.nxv64i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 64 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv8f16_nxv64i8(<vscale x 8 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv8f16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv8f16.nxv64i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv8f16.nxv4i16(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 4 x i16>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv8f16.nxv4i16(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 4 x i16>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg2_nxv8f16_nxv4i16(<vscale x 8 x half> %val, half* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv8f16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv1r.v v25, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv8f16.nxv4i16(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 4 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv8f16_nxv4i16(<vscale x 8 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv8f16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv1r.v v25, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv8f16.nxv4i16(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv8f16.nxv8i64(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 8 x i64>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv8f16.nxv8i64(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 8 x i64>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg2_nxv8f16_nxv8i64(<vscale x 8 x half> %val, half* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv8f16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv8f16.nxv8i64(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 8 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv8f16_nxv8i64(<vscale x 8 x half> %val, half* %base, <vscale x 8 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv8f16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv8f16.nxv8i64(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 8 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv8f16.nxv1i8(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv8f16.nxv1i8(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 1 x i8>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg2_nxv8f16_nxv1i8(<vscale x 8 x half> %val, half* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv8f16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv1r.v v25, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv8f16.nxv1i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 1 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv8f16_nxv1i8(<vscale x 8 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv8f16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv1r.v v25, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv8f16.nxv1i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv8f16.nxv2i8(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 2 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv8f16.nxv2i8(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 2 x i8>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg2_nxv8f16_nxv2i8(<vscale x 8 x half> %val, half* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv8f16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv1r.v v25, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv8f16.nxv2i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 2 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv8f16_nxv2i8(<vscale x 8 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv8f16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv1r.v v25, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv8f16.nxv2i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv8f16.nxv8i32(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 8 x i32>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv8f16.nxv8i32(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 8 x i32>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg2_nxv8f16_nxv8i32(<vscale x 8 x half> %val, half* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv8f16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv8f16.nxv8i32(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 8 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv8f16_nxv8i32(<vscale x 8 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv8f16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv8f16.nxv8i32(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv8f16.nxv32i8(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 32 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv8f16.nxv32i8(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 32 x i8>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg2_nxv8f16_nxv32i8(<vscale x 8 x half> %val, half* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv8f16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv8f16.nxv32i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 32 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv8f16_nxv32i8(<vscale x 8 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv8f16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv8f16.nxv32i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv8f16.nxv16i32(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 16 x i32>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv8f16.nxv16i32(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 16 x i32>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg2_nxv8f16_nxv16i32(<vscale x 8 x half> %val, half* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv8f16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv8f16.nxv16i32(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 16 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv8f16_nxv16i32(<vscale x 8 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv8f16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv8f16.nxv16i32(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv8f16.nxv2i16(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 2 x i16>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv8f16.nxv2i16(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 2 x i16>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg2_nxv8f16_nxv2i16(<vscale x 8 x half> %val, half* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv8f16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv1r.v v25, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv8f16.nxv2i16(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 2 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv8f16_nxv2i16(<vscale x 8 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv8f16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv1r.v v25, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv8f16.nxv2i16(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv8f16.nxv2i64(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 2 x i64>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv8f16.nxv2i64(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 2 x i64>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg2_nxv8f16_nxv2i64(<vscale x 8 x half> %val, half* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv8f16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv2r.v v26, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v26
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv8f16.nxv2i64(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 2 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv8f16_nxv2i64(<vscale x 8 x half> %val, half* %base, <vscale x 2 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv8f16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv2r.v v26, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v26, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv8f16.nxv2i64(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 2 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv8f16.nxv16i16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 16 x i16>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv8f16.nxv16i16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 16 x i16>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg3_nxv8f16_nxv16i16(<vscale x 8 x half> %val, half* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv8f16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv8f16.nxv16i16(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 16 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv8f16_nxv16i16(<vscale x 8 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv8f16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v2, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv8f16.nxv16i16(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv8f16.nxv32i16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 32 x i16>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv8f16.nxv32i16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 32 x i16>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg3_nxv8f16_nxv32i16(<vscale x 8 x half> %val, half* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv8f16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vmv2r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv8f16.nxv32i16(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 32 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv8f16_nxv32i16(<vscale x 8 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv8f16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vmv2r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv8f16.nxv32i16(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv8f16.nxv4i32(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 4 x i32>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv8f16.nxv4i32(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 4 x i32>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg3_nxv8f16_nxv4i32(<vscale x 8 x half> %val, half* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv8f16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv8f16.nxv4i32(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 4 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv8f16_nxv4i32(<vscale x 8 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv8f16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv8f16.nxv4i32(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv8f16.nxv16i8(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 16 x i8>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv8f16.nxv16i8(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 16 x i8>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg3_nxv8f16_nxv16i8(<vscale x 8 x half> %val, half* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv8f16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv8f16.nxv16i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 16 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv8f16_nxv16i8(<vscale x 8 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv8f16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv8f16.nxv16i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv8f16.nxv1i64(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv8f16.nxv1i64(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 1 x i64>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg3_nxv8f16_nxv1i64(<vscale x 8 x half> %val, half* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv8f16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei64.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv8f16.nxv1i64(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 1 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv8f16_nxv1i64(<vscale x 8 x half> %val, half* %base, <vscale x 1 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv8f16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei64.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv8f16.nxv1i64(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 1 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv8f16.nxv1i32(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv8f16.nxv1i32(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 1 x i32>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg3_nxv8f16_nxv1i32(<vscale x 8 x half> %val, half* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv8f16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv8f16.nxv1i32(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 1 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv8f16_nxv1i32(<vscale x 8 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv8f16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv8f16.nxv1i32(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv8f16.nxv8i16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 8 x i16>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv8f16.nxv8i16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 8 x i16>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg3_nxv8f16_nxv8i16(<vscale x 8 x half> %val, half* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv8f16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv8f16.nxv8i16(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 8 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv8f16_nxv8i16(<vscale x 8 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv8f16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv8f16.nxv8i16(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv8f16.nxv4i8(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 4 x i8>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv8f16.nxv4i8(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 4 x i8>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg3_nxv8f16_nxv4i8(<vscale x 8 x half> %val, half* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv8f16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv8f16.nxv4i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 4 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv8f16_nxv4i8(<vscale x 8 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv8f16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv8f16.nxv4i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv8f16.nxv1i16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv8f16.nxv1i16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 1 x i16>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg3_nxv8f16_nxv1i16(<vscale x 8 x half> %val, half* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv8f16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv8f16.nxv1i16(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 1 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv8f16_nxv1i16(<vscale x 8 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv8f16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv8f16.nxv1i16(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv8f16.nxv2i32(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 2 x i32>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv8f16.nxv2i32(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 2 x i32>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg3_nxv8f16_nxv2i32(<vscale x 8 x half> %val, half* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv8f16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv8f16.nxv2i32(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 2 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv8f16_nxv2i32(<vscale x 8 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv8f16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv8f16.nxv2i32(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv8f16.nxv8i8(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 8 x i8>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv8f16.nxv8i8(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 8 x i8>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg3_nxv8f16_nxv8i8(<vscale x 8 x half> %val, half* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv8f16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv8f16.nxv8i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 8 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv8f16_nxv8i8(<vscale x 8 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv8f16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv8f16.nxv8i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv8f16.nxv4i64(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 4 x i64>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv8f16.nxv4i64(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 4 x i64>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg3_nxv8f16_nxv4i64(<vscale x 8 x half> %val, half* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv8f16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei64.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv8f16.nxv4i64(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 4 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv8f16_nxv4i64(<vscale x 8 x half> %val, half* %base, <vscale x 4 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv8f16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei64.v v2, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv8f16.nxv4i64(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 4 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv8f16.nxv64i8(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 64 x i8>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv8f16.nxv64i8(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 64 x i8>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg3_nxv8f16_nxv64i8(<vscale x 8 x half> %val, half* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv8f16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vmv2r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv8f16.nxv64i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 64 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv8f16_nxv64i8(<vscale x 8 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv8f16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vmv2r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv8f16.nxv64i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv8f16.nxv4i16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 4 x i16>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv8f16.nxv4i16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 4 x i16>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg3_nxv8f16_nxv4i16(<vscale x 8 x half> %val, half* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv8f16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv8f16.nxv4i16(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 4 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv8f16_nxv4i16(<vscale x 8 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv8f16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv8f16.nxv4i16(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv8f16.nxv8i64(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 8 x i64>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv8f16.nxv8i64(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 8 x i64>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg3_nxv8f16_nxv8i64(<vscale x 8 x half> %val, half* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv8f16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vmv2r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei64.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv8f16.nxv8i64(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 8 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv8f16_nxv8i64(<vscale x 8 x half> %val, half* %base, <vscale x 8 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv8f16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vmv2r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei64.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv8f16.nxv8i64(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 8 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv8f16.nxv1i8(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv8f16.nxv1i8(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 1 x i8>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg3_nxv8f16_nxv1i8(<vscale x 8 x half> %val, half* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv8f16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv8f16.nxv1i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 1 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv8f16_nxv1i8(<vscale x 8 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv8f16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv8f16.nxv1i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv8f16.nxv2i8(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 2 x i8>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv8f16.nxv2i8(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 2 x i8>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg3_nxv8f16_nxv2i8(<vscale x 8 x half> %val, half* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv8f16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv8f16.nxv2i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 2 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv8f16_nxv2i8(<vscale x 8 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv8f16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv8f16.nxv2i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv8f16.nxv8i32(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 8 x i32>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv8f16.nxv8i32(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 8 x i32>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg3_nxv8f16_nxv8i32(<vscale x 8 x half> %val, half* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv8f16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv8f16.nxv8i32(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 8 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv8f16_nxv8i32(<vscale x 8 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv8f16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v2, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv8f16.nxv8i32(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv8f16.nxv32i8(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 32 x i8>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv8f16.nxv32i8(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 32 x i8>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg3_nxv8f16_nxv32i8(<vscale x 8 x half> %val, half* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv8f16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv8f16.nxv32i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 32 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv8f16_nxv32i8(<vscale x 8 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv8f16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v2, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv8f16.nxv32i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv8f16.nxv16i32(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 16 x i32>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv8f16.nxv16i32(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 16 x i32>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg3_nxv8f16_nxv16i32(<vscale x 8 x half> %val, half* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv8f16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vmv2r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv8f16.nxv16i32(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 16 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv8f16_nxv16i32(<vscale x 8 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv8f16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vmv2r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv8f16.nxv16i32(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv8f16.nxv2i16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 2 x i16>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv8f16.nxv2i16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 2 x i16>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg3_nxv8f16_nxv2i16(<vscale x 8 x half> %val, half* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv8f16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv8f16.nxv2i16(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 2 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv8f16_nxv2i16(<vscale x 8 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv8f16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv8f16.nxv2i16(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv8f16.nxv2i64(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 2 x i64>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv8f16.nxv2i64(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 2 x i64>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg3_nxv8f16_nxv2i64(<vscale x 8 x half> %val, half* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv8f16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei64.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv8f16.nxv2i64(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 2 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv8f16_nxv2i64(<vscale x 8 x half> %val, half* %base, <vscale x 2 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv8f16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei64.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv8f16.nxv2i64(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 2 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv8f16.nxv16i16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 16 x i16>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv8f16.nxv16i16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 16 x i16>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg4_nxv8f16_nxv16i16(<vscale x 8 x half> %val, half* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv8f16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vmv2r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv8f16.nxv16i16(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 16 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv8f16_nxv16i16(<vscale x 8 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv8f16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v2, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv8f16.nxv16i16(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv8f16.nxv32i16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 32 x i16>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv8f16.nxv32i16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 32 x i16>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg4_nxv8f16_nxv32i16(<vscale x 8 x half> %val, half* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv8f16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2_v22m2
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vmv2r.v v20, v16
+; CHECK-NEXT:    vmv2r.v v22, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv8f16.nxv32i16(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 32 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv8f16_nxv32i16(<vscale x 8 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv8f16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2_v22m2
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vmv2r.v v20, v16
+; CHECK-NEXT:    vmv2r.v v22, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv8f16.nxv32i16(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv8f16.nxv4i32(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 4 x i32>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv8f16.nxv4i32(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 4 x i32>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg4_nxv8f16_nxv4i32(<vscale x 8 x half> %val, half* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv8f16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vmv2r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv8f16.nxv4i32(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 4 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv8f16_nxv4i32(<vscale x 8 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv8f16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv8f16.nxv4i32(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv8f16.nxv16i8(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 16 x i8>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv8f16.nxv16i8(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 16 x i8>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg4_nxv8f16_nxv16i8(<vscale x 8 x half> %val, half* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv8f16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vmv2r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv8f16.nxv16i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 16 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv8f16_nxv16i8(<vscale x 8 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv8f16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv8f16.nxv16i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv8f16.nxv1i64(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv8f16.nxv1i64(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 1 x i64>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg4_nxv8f16_nxv1i64(<vscale x 8 x half> %val, half* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv8f16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vmv2r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei64.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv8f16.nxv1i64(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 1 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv8f16_nxv1i64(<vscale x 8 x half> %val, half* %base, <vscale x 1 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv8f16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei64.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv8f16.nxv1i64(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 1 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv8f16.nxv1i32(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv8f16.nxv1i32(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 1 x i32>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg4_nxv8f16_nxv1i32(<vscale x 8 x half> %val, half* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv8f16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vmv2r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv8f16.nxv1i32(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 1 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv8f16_nxv1i32(<vscale x 8 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv8f16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv8f16.nxv1i32(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv8f16.nxv8i16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 8 x i16>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv8f16.nxv8i16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 8 x i16>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg4_nxv8f16_nxv8i16(<vscale x 8 x half> %val, half* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv8f16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vmv2r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv8f16.nxv8i16(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 8 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv8f16_nxv8i16(<vscale x 8 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv8f16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv8f16.nxv8i16(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv8f16.nxv4i8(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 4 x i8>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv8f16.nxv4i8(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 4 x i8>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg4_nxv8f16_nxv4i8(<vscale x 8 x half> %val, half* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv8f16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vmv2r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv8f16.nxv4i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 4 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv8f16_nxv4i8(<vscale x 8 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv8f16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv8f16.nxv4i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv8f16.nxv1i16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv8f16.nxv1i16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 1 x i16>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg4_nxv8f16_nxv1i16(<vscale x 8 x half> %val, half* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv8f16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vmv2r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv8f16.nxv1i16(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 1 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv8f16_nxv1i16(<vscale x 8 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv8f16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv8f16.nxv1i16(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv8f16.nxv2i32(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 2 x i32>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv8f16.nxv2i32(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 2 x i32>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg4_nxv8f16_nxv2i32(<vscale x 8 x half> %val, half* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv8f16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vmv2r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv8f16.nxv2i32(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 2 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv8f16_nxv2i32(<vscale x 8 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv8f16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv8f16.nxv2i32(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv8f16.nxv8i8(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 8 x i8>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv8f16.nxv8i8(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 8 x i8>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg4_nxv8f16_nxv8i8(<vscale x 8 x half> %val, half* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv8f16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vmv2r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv8f16.nxv8i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 8 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv8f16_nxv8i8(<vscale x 8 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv8f16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv8f16.nxv8i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv8f16.nxv4i64(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 4 x i64>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv8f16.nxv4i64(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 4 x i64>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg4_nxv8f16_nxv4i64(<vscale x 8 x half> %val, half* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv8f16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vmv2r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei64.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv8f16.nxv4i64(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 4 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv8f16_nxv4i64(<vscale x 8 x half> %val, half* %base, <vscale x 4 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv8f16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei64.v v2, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv8f16.nxv4i64(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 4 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv8f16.nxv64i8(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 64 x i8>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv8f16.nxv64i8(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 64 x i8>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg4_nxv8f16_nxv64i8(<vscale x 8 x half> %val, half* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv8f16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2_v22m2
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vmv2r.v v20, v16
+; CHECK-NEXT:    vmv2r.v v22, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv8f16.nxv64i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 64 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv8f16_nxv64i8(<vscale x 8 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv8f16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2_v22m2
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vmv2r.v v20, v16
+; CHECK-NEXT:    vmv2r.v v22, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv8f16.nxv64i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv8f16.nxv4i16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 4 x i16>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv8f16.nxv4i16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 4 x i16>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg4_nxv8f16_nxv4i16(<vscale x 8 x half> %val, half* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv8f16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vmv2r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv8f16.nxv4i16(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 4 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv8f16_nxv4i16(<vscale x 8 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv8f16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv8f16.nxv4i16(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv8f16.nxv8i64(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 8 x i64>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv8f16.nxv8i64(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 8 x i64>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg4_nxv8f16_nxv8i64(<vscale x 8 x half> %val, half* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv8f16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2_v22m2
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vmv2r.v v20, v16
+; CHECK-NEXT:    vmv2r.v v22, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei64.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv8f16.nxv8i64(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 8 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv8f16_nxv8i64(<vscale x 8 x half> %val, half* %base, <vscale x 8 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv8f16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2_v22m2
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vmv2r.v v20, v16
+; CHECK-NEXT:    vmv2r.v v22, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei64.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv8f16.nxv8i64(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 8 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv8f16.nxv1i8(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv8f16.nxv1i8(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 1 x i8>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg4_nxv8f16_nxv1i8(<vscale x 8 x half> %val, half* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv8f16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vmv2r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv8f16.nxv1i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 1 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv8f16_nxv1i8(<vscale x 8 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv8f16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv8f16.nxv1i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv8f16.nxv2i8(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 2 x i8>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv8f16.nxv2i8(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 2 x i8>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg4_nxv8f16_nxv2i8(<vscale x 8 x half> %val, half* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv8f16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vmv2r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv8f16.nxv2i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 2 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv8f16_nxv2i8(<vscale x 8 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv8f16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv8f16.nxv2i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv8f16.nxv8i32(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 8 x i32>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv8f16.nxv8i32(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 8 x i32>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg4_nxv8f16_nxv8i32(<vscale x 8 x half> %val, half* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv8f16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vmv2r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv8f16.nxv8i32(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 8 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv8f16_nxv8i32(<vscale x 8 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv8f16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v2, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv8f16.nxv8i32(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv8f16.nxv32i8(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 32 x i8>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv8f16.nxv32i8(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 32 x i8>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg4_nxv8f16_nxv32i8(<vscale x 8 x half> %val, half* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv8f16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vmv2r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv8f16.nxv32i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 32 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv8f16_nxv32i8(<vscale x 8 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv8f16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v2, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv8f16.nxv32i8(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv8f16.nxv16i32(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 16 x i32>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv8f16.nxv16i32(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 16 x i32>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg4_nxv8f16_nxv16i32(<vscale x 8 x half> %val, half* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv8f16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2_v22m2
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vmv2r.v v20, v16
+; CHECK-NEXT:    vmv2r.v v22, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv8f16.nxv16i32(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 16 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv8f16_nxv16i32(<vscale x 8 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv8f16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2_v22m2
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vmv2r.v v20, v16
+; CHECK-NEXT:    vmv2r.v v22, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv8f16.nxv16i32(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv8f16.nxv2i16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 2 x i16>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv8f16.nxv2i16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 2 x i16>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg4_nxv8f16_nxv2i16(<vscale x 8 x half> %val, half* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv8f16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vmv2r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv8f16.nxv2i16(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 2 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv8f16_nxv2i16(<vscale x 8 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv8f16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv8f16.nxv2i16(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv8f16.nxv2i64(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 2 x i64>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv8f16.nxv2i64(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 2 x i64>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg4_nxv8f16_nxv2i64(<vscale x 8 x half> %val, half* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv8f16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vmv2r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei64.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv8f16.nxv2i64(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 2 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv8f16_nxv2i64(<vscale x 8 x half> %val, half* %base, <vscale x 2 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv8f16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei64.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv8f16.nxv2i64(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 2 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv8f32.nxv16i16(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 16 x i16>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv8f32.nxv16i16(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 16 x i16>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg2_nxv8f32_nxv16i16(<vscale x 8 x float> %val, float* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv8f32_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv4r.v v28, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v28
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv8f32.nxv16i16(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 16 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv8f32_nxv16i16(<vscale x 8 x float> %val, float* %base, <vscale x 16 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv8f32_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv4r.v v28, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v28, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv8f32.nxv16i16(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 16 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv8f32.nxv32i16(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 32 x i16>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv8f32.nxv32i16(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 32 x i16>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg2_nxv8f32_nxv32i16(<vscale x 8 x float> %val, float* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv8f32_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv8f32.nxv32i16(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 32 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv8f32_nxv32i16(<vscale x 8 x float> %val, float* %base, <vscale x 32 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv8f32_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv8f32.nxv32i16(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 32 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv8f32.nxv4i32(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 4 x i32>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv8f32.nxv4i32(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 4 x i32>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg2_nxv8f32_nxv4i32(<vscale x 8 x float> %val, float* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv8f32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv2r.v v26, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v26
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv8f32.nxv4i32(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 4 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv8f32_nxv4i32(<vscale x 8 x float> %val, float* %base, <vscale x 4 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv8f32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv2r.v v26, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v26, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv8f32.nxv4i32(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 4 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv8f32.nxv16i8(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 16 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv8f32.nxv16i8(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 16 x i8>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg2_nxv8f32_nxv16i8(<vscale x 8 x float> %val, float* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv8f32_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv2r.v v26, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v26
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv8f32.nxv16i8(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 16 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv8f32_nxv16i8(<vscale x 8 x float> %val, float* %base, <vscale x 16 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv8f32_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv2r.v v26, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v26, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv8f32.nxv16i8(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 16 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv8f32.nxv1i64(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv8f32.nxv1i64(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 1 x i64>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg2_nxv8f32_nxv1i64(<vscale x 8 x float> %val, float* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv8f32_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv1r.v v25, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv8f32.nxv1i64(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 1 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv8f32_nxv1i64(<vscale x 8 x float> %val, float* %base, <vscale x 1 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv8f32_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv1r.v v25, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv8f32.nxv1i64(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 1 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv8f32.nxv1i32(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv8f32.nxv1i32(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 1 x i32>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg2_nxv8f32_nxv1i32(<vscale x 8 x float> %val, float* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv8f32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv1r.v v25, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv8f32.nxv1i32(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 1 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv8f32_nxv1i32(<vscale x 8 x float> %val, float* %base, <vscale x 1 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv8f32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv1r.v v25, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv8f32.nxv1i32(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 1 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv8f32.nxv8i16(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 8 x i16>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv8f32.nxv8i16(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 8 x i16>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg2_nxv8f32_nxv8i16(<vscale x 8 x float> %val, float* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv8f32_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv2r.v v26, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v26
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv8f32.nxv8i16(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 8 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv8f32_nxv8i16(<vscale x 8 x float> %val, float* %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv8f32_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv2r.v v26, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v26, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv8f32.nxv8i16(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 8 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv8f32.nxv4i8(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 4 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv8f32.nxv4i8(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 4 x i8>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg2_nxv8f32_nxv4i8(<vscale x 8 x float> %val, float* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv8f32_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv1r.v v25, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv8f32.nxv4i8(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 4 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv8f32_nxv4i8(<vscale x 8 x float> %val, float* %base, <vscale x 4 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv8f32_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv1r.v v25, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv8f32.nxv4i8(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 4 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv8f32.nxv1i16(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv8f32.nxv1i16(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 1 x i16>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg2_nxv8f32_nxv1i16(<vscale x 8 x float> %val, float* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv8f32_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv1r.v v25, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv8f32.nxv1i16(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 1 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv8f32_nxv1i16(<vscale x 8 x float> %val, float* %base, <vscale x 1 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv8f32_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv1r.v v25, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv8f32.nxv1i16(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 1 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv8f32.nxv2i32(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 2 x i32>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv8f32.nxv2i32(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 2 x i32>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg2_nxv8f32_nxv2i32(<vscale x 8 x float> %val, float* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv8f32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv1r.v v25, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv8f32.nxv2i32(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 2 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv8f32_nxv2i32(<vscale x 8 x float> %val, float* %base, <vscale x 2 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv8f32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv1r.v v25, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv8f32.nxv2i32(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 2 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv8f32.nxv8i8(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 8 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv8f32.nxv8i8(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 8 x i8>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg2_nxv8f32_nxv8i8(<vscale x 8 x float> %val, float* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv8f32_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv1r.v v25, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv8f32.nxv8i8(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 8 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv8f32_nxv8i8(<vscale x 8 x float> %val, float* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv8f32_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv1r.v v25, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv8f32.nxv8i8(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 8 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv8f32.nxv4i64(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 4 x i64>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv8f32.nxv4i64(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 4 x i64>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg2_nxv8f32_nxv4i64(<vscale x 8 x float> %val, float* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv8f32_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv4r.v v28, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v28
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv8f32.nxv4i64(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 4 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv8f32_nxv4i64(<vscale x 8 x float> %val, float* %base, <vscale x 4 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv8f32_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv4r.v v28, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v28, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv8f32.nxv4i64(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 4 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv8f32.nxv64i8(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 64 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv8f32.nxv64i8(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 64 x i8>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg2_nxv8f32_nxv64i8(<vscale x 8 x float> %val, float* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv8f32_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv8f32.nxv64i8(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 64 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv8f32_nxv64i8(<vscale x 8 x float> %val, float* %base, <vscale x 64 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv8f32_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv8f32.nxv64i8(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 64 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv8f32.nxv4i16(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 4 x i16>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv8f32.nxv4i16(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 4 x i16>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg2_nxv8f32_nxv4i16(<vscale x 8 x float> %val, float* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv8f32_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv1r.v v25, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv8f32.nxv4i16(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 4 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv8f32_nxv4i16(<vscale x 8 x float> %val, float* %base, <vscale x 4 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv8f32_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv1r.v v25, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv8f32.nxv4i16(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 4 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv8f32.nxv8i64(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 8 x i64>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv8f32.nxv8i64(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 8 x i64>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg2_nxv8f32_nxv8i64(<vscale x 8 x float> %val, float* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv8f32_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv8f32.nxv8i64(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 8 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv8f32_nxv8i64(<vscale x 8 x float> %val, float* %base, <vscale x 8 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv8f32_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv8f32.nxv8i64(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 8 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv8f32.nxv1i8(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv8f32.nxv1i8(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 1 x i8>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg2_nxv8f32_nxv1i8(<vscale x 8 x float> %val, float* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv8f32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv1r.v v25, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv8f32.nxv1i8(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 1 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv8f32_nxv1i8(<vscale x 8 x float> %val, float* %base, <vscale x 1 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv8f32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv1r.v v25, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv8f32.nxv1i8(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 1 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv8f32.nxv2i8(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 2 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv8f32.nxv2i8(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 2 x i8>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg2_nxv8f32_nxv2i8(<vscale x 8 x float> %val, float* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv8f32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv1r.v v25, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv8f32.nxv2i8(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 2 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv8f32_nxv2i8(<vscale x 8 x float> %val, float* %base, <vscale x 2 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv8f32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv1r.v v25, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv8f32.nxv2i8(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 2 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv8f32.nxv8i32(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 8 x i32>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv8f32.nxv8i32(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 8 x i32>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg2_nxv8f32_nxv8i32(<vscale x 8 x float> %val, float* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv8f32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv4r.v v28, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v28
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv8f32.nxv8i32(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 8 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv8f32_nxv8i32(<vscale x 8 x float> %val, float* %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv8f32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv4r.v v28, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v28, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv8f32.nxv8i32(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 8 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv8f32.nxv32i8(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 32 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv8f32.nxv32i8(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 32 x i8>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg2_nxv8f32_nxv32i8(<vscale x 8 x float> %val, float* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv8f32_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv4r.v v28, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v28
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv8f32.nxv32i8(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 32 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv8f32_nxv32i8(<vscale x 8 x float> %val, float* %base, <vscale x 32 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv8f32_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv4r.v v28, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v28, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv8f32.nxv32i8(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 32 x i8> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv8f32.nxv16i32(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 16 x i32>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv8f32.nxv16i32(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 16 x i32>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg2_nxv8f32_nxv16i32(<vscale x 8 x float> %val, float* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv8f32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv8f32.nxv16i32(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 16 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv8f32_nxv16i32(<vscale x 8 x float> %val, float* %base, <vscale x 16 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv8f32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv8f32.nxv16i32(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 16 x i32> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv8f32.nxv2i16(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 2 x i16>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv8f32.nxv2i16(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 2 x i16>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg2_nxv8f32_nxv2i16(<vscale x 8 x float> %val, float* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv8f32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv1r.v v25, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv8f32.nxv2i16(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 2 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv8f32_nxv2i16(<vscale x 8 x float> %val, float* %base, <vscale x 2 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv8f32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv1r.v v25, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv8f32.nxv2i16(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 2 x i16> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv8f32.nxv2i64(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 2 x i64>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv8f32.nxv2i64(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 2 x i64>, <vscale x 8 x i1>, i64)
+
+define void @test_vsxseg2_nxv8f32_nxv2i64(<vscale x 8 x float> %val, float* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv8f32_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv2r.v v26, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v26
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv8f32.nxv2i64(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 2 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv8f32_nxv2i64(<vscale x 8 x float> %val, float* %base, <vscale x 2 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv8f32_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m4 killed $v16m4 killed $v16m4_v20m4 def $v16m4_v20m4
+; CHECK-NEXT:    vmv2r.v v26, v20
+; CHECK-NEXT:    vmv4r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v26, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv8f32.nxv2i64(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 2 x i64> %index, <vscale x 8 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv2f64.nxv16i16(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 16 x i16>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv2f64.nxv16i16(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 16 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg2_nxv2f64_nxv16i16(<vscale x 2 x double> %val, double* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv2f64_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv2f64.nxv16i16(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 16 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv2f64_nxv16i16(<vscale x 2 x double> %val, double* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv2f64_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv2f64.nxv16i16(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv2f64.nxv32i16(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 32 x i16>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv2f64.nxv32i16(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 32 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg2_nxv2f64_nxv32i16(<vscale x 2 x double> %val, double* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv2f64_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a2, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv2f64.nxv32i16(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 32 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv2f64_nxv32i16(<vscale x 2 x double> %val, double* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv2f64_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a2, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv2f64.nxv32i16(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv2f64.nxv4i32(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 4 x i32>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv2f64.nxv4i32(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 4 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg2_nxv2f64_nxv4i32(<vscale x 2 x double> %val, double* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv2f64_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv2r.v v26, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v26
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv2f64.nxv4i32(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 4 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv2f64_nxv4i32(<vscale x 2 x double> %val, double* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv2f64_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv2r.v v26, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v26, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv2f64.nxv4i32(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv2f64.nxv16i8(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 16 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv2f64.nxv16i8(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 16 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg2_nxv2f64_nxv16i8(<vscale x 2 x double> %val, double* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv2f64_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv2r.v v26, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v26
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv2f64.nxv16i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 16 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv2f64_nxv16i8(<vscale x 2 x double> %val, double* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv2f64_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv2r.v v26, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v26, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv2f64.nxv16i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv2f64.nxv1i64(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv2f64.nxv1i64(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 1 x i64>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg2_nxv2f64_nxv1i64(<vscale x 2 x double> %val, double* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv2f64_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv1r.v v25, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv2f64.nxv1i64(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 1 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv2f64_nxv1i64(<vscale x 2 x double> %val, double* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv2f64_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv1r.v v25, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv2f64.nxv1i64(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv2f64.nxv1i32(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv2f64.nxv1i32(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 1 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg2_nxv2f64_nxv1i32(<vscale x 2 x double> %val, double* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv2f64_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv1r.v v25, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv2f64.nxv1i32(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 1 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv2f64_nxv1i32(<vscale x 2 x double> %val, double* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv2f64_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv1r.v v25, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv2f64.nxv1i32(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv2f64.nxv8i16(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 8 x i16>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv2f64.nxv8i16(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 8 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg2_nxv2f64_nxv8i16(<vscale x 2 x double> %val, double* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv2f64_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv2r.v v26, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v26
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv2f64.nxv8i16(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 8 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv2f64_nxv8i16(<vscale x 2 x double> %val, double* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv2f64_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv2r.v v26, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v26, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv2f64.nxv8i16(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv2f64.nxv4i8(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 4 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv2f64.nxv4i8(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 4 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg2_nxv2f64_nxv4i8(<vscale x 2 x double> %val, double* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv2f64_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv1r.v v25, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv2f64.nxv4i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 4 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv2f64_nxv4i8(<vscale x 2 x double> %val, double* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv2f64_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv1r.v v25, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv2f64.nxv4i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv2f64.nxv1i16(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv2f64.nxv1i16(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 1 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg2_nxv2f64_nxv1i16(<vscale x 2 x double> %val, double* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv2f64_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv1r.v v25, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv2f64.nxv1i16(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 1 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv2f64_nxv1i16(<vscale x 2 x double> %val, double* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv2f64_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv1r.v v25, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv2f64.nxv1i16(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv2f64.nxv2i32(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i32>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv2f64.nxv2i32(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg2_nxv2f64_nxv2i32(<vscale x 2 x double> %val, double* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv2f64_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv1r.v v25, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv2f64.nxv2i32(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 2 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv2f64_nxv2i32(<vscale x 2 x double> %val, double* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv2f64_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv1r.v v25, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv2f64.nxv2i32(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv2f64.nxv8i8(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 8 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv2f64.nxv8i8(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 8 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg2_nxv2f64_nxv8i8(<vscale x 2 x double> %val, double* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv2f64_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv1r.v v25, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv2f64.nxv8i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 8 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv2f64_nxv8i8(<vscale x 2 x double> %val, double* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv2f64_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv1r.v v25, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv2f64.nxv8i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv2f64.nxv4i64(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 4 x i64>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv2f64.nxv4i64(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 4 x i64>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg2_nxv2f64_nxv4i64(<vscale x 2 x double> %val, double* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv2f64_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv2f64.nxv4i64(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 4 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv2f64_nxv4i64(<vscale x 2 x double> %val, double* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv2f64_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv2f64.nxv4i64(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv2f64.nxv64i8(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 64 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv2f64.nxv64i8(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 64 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg2_nxv2f64_nxv64i8(<vscale x 2 x double> %val, double* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv2f64_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a2, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv2f64.nxv64i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 64 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv2f64_nxv64i8(<vscale x 2 x double> %val, double* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv2f64_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a2, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv2f64.nxv64i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv2f64.nxv4i16(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 4 x i16>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv2f64.nxv4i16(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 4 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg2_nxv2f64_nxv4i16(<vscale x 2 x double> %val, double* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv2f64_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv1r.v v25, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv2f64.nxv4i16(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 4 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv2f64_nxv4i16(<vscale x 2 x double> %val, double* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv2f64_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv1r.v v25, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv2f64.nxv4i16(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv2f64.nxv8i64(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 8 x i64>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv2f64.nxv8i64(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 8 x i64>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg2_nxv2f64_nxv8i64(<vscale x 2 x double> %val, double* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv2f64_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a2, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv2f64.nxv8i64(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 8 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv2f64_nxv8i64(<vscale x 2 x double> %val, double* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv2f64_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a2, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv2f64.nxv8i64(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv2f64.nxv1i8(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv2f64.nxv1i8(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 1 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg2_nxv2f64_nxv1i8(<vscale x 2 x double> %val, double* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv2f64_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv1r.v v25, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv2f64.nxv1i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 1 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv2f64_nxv1i8(<vscale x 2 x double> %val, double* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv2f64_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv1r.v v25, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv2f64.nxv1i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv2f64.nxv2i8(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv2f64.nxv2i8(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg2_nxv2f64_nxv2i8(<vscale x 2 x double> %val, double* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv2f64_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv1r.v v25, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv2f64.nxv2i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 2 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv2f64_nxv2i8(<vscale x 2 x double> %val, double* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv2f64_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv1r.v v25, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv2f64.nxv2i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv2f64.nxv8i32(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 8 x i32>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv2f64.nxv8i32(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 8 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg2_nxv2f64_nxv8i32(<vscale x 2 x double> %val, double* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv2f64_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv2f64.nxv8i32(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 8 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv2f64_nxv8i32(<vscale x 2 x double> %val, double* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv2f64_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv2f64.nxv8i32(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv2f64.nxv32i8(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 32 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv2f64.nxv32i8(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 32 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg2_nxv2f64_nxv32i8(<vscale x 2 x double> %val, double* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv2f64_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv2f64.nxv32i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 32 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv2f64_nxv32i8(<vscale x 2 x double> %val, double* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv2f64_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv2f64.nxv32i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv2f64.nxv16i32(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 16 x i32>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv2f64.nxv16i32(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 16 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg2_nxv2f64_nxv16i32(<vscale x 2 x double> %val, double* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv2f64_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a2, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv2f64.nxv16i32(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 16 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv2f64_nxv16i32(<vscale x 2 x double> %val, double* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv2f64_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a2, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv2f64.nxv16i32(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv2f64.nxv2i16(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i16>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv2f64.nxv2i16(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg2_nxv2f64_nxv2i16(<vscale x 2 x double> %val, double* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv2f64_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv1r.v v25, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv2f64.nxv2i16(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 2 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv2f64_nxv2i16(<vscale x 2 x double> %val, double* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv2f64_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv1r.v v25, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv2f64.nxv2i16(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv2f64.nxv2i64(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i64>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv2f64.nxv2i64(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg2_nxv2f64_nxv2i64(<vscale x 2 x double> %val, double* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv2f64_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv2r.v v26, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v26
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv2f64.nxv2i64(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 2 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv2f64_nxv2i64(<vscale x 2 x double> %val, double* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv2f64_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv2r.v v26, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v26, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv2f64.nxv2i64(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv2f64.nxv16i16(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 16 x i16>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv2f64.nxv16i16(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 16 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg3_nxv2f64_nxv16i16(<vscale x 2 x double> %val, double* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv2f64_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv2f64.nxv16i16(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 16 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv2f64_nxv16i16(<vscale x 2 x double> %val, double* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv2f64_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v2, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv2f64.nxv16i16(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv2f64.nxv32i16(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 32 x i16>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv2f64.nxv32i16(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 32 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg3_nxv2f64_nxv32i16(<vscale x 2 x double> %val, double* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv2f64_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vmv2r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv2f64.nxv32i16(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 32 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv2f64_nxv32i16(<vscale x 2 x double> %val, double* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv2f64_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vmv2r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv2f64.nxv32i16(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv2f64.nxv4i32(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 4 x i32>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv2f64.nxv4i32(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 4 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg3_nxv2f64_nxv4i32(<vscale x 2 x double> %val, double* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv2f64_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv2f64.nxv4i32(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 4 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv2f64_nxv4i32(<vscale x 2 x double> %val, double* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv2f64_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv2f64.nxv4i32(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv2f64.nxv16i8(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 16 x i8>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv2f64.nxv16i8(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 16 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg3_nxv2f64_nxv16i8(<vscale x 2 x double> %val, double* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv2f64_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv2f64.nxv16i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 16 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv2f64_nxv16i8(<vscale x 2 x double> %val, double* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv2f64_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv2f64.nxv16i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv2f64.nxv1i64(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv2f64.nxv1i64(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 1 x i64>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg3_nxv2f64_nxv1i64(<vscale x 2 x double> %val, double* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv2f64_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei64.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv2f64.nxv1i64(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 1 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv2f64_nxv1i64(<vscale x 2 x double> %val, double* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv2f64_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei64.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv2f64.nxv1i64(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv2f64.nxv1i32(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv2f64.nxv1i32(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 1 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg3_nxv2f64_nxv1i32(<vscale x 2 x double> %val, double* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv2f64_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv2f64.nxv1i32(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 1 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv2f64_nxv1i32(<vscale x 2 x double> %val, double* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv2f64_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv2f64.nxv1i32(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv2f64.nxv8i16(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 8 x i16>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv2f64.nxv8i16(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 8 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg3_nxv2f64_nxv8i16(<vscale x 2 x double> %val, double* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv2f64_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv2f64.nxv8i16(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 8 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv2f64_nxv8i16(<vscale x 2 x double> %val, double* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv2f64_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv2f64.nxv8i16(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv2f64.nxv4i8(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 4 x i8>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv2f64.nxv4i8(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 4 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg3_nxv2f64_nxv4i8(<vscale x 2 x double> %val, double* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv2f64_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv2f64.nxv4i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 4 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv2f64_nxv4i8(<vscale x 2 x double> %val, double* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv2f64_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv2f64.nxv4i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv2f64.nxv1i16(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv2f64.nxv1i16(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 1 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg3_nxv2f64_nxv1i16(<vscale x 2 x double> %val, double* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv2f64_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv2f64.nxv1i16(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 1 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv2f64_nxv1i16(<vscale x 2 x double> %val, double* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv2f64_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv2f64.nxv1i16(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv2f64.nxv2i32(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i32>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv2f64.nxv2i32(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg3_nxv2f64_nxv2i32(<vscale x 2 x double> %val, double* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv2f64_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv2f64.nxv2i32(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 2 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv2f64_nxv2i32(<vscale x 2 x double> %val, double* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv2f64_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv2f64.nxv2i32(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv2f64.nxv8i8(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 8 x i8>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv2f64.nxv8i8(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 8 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg3_nxv2f64_nxv8i8(<vscale x 2 x double> %val, double* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv2f64_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv2f64.nxv8i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 8 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv2f64_nxv8i8(<vscale x 2 x double> %val, double* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv2f64_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv2f64.nxv8i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv2f64.nxv4i64(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 4 x i64>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv2f64.nxv4i64(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 4 x i64>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg3_nxv2f64_nxv4i64(<vscale x 2 x double> %val, double* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv2f64_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei64.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv2f64.nxv4i64(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 4 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv2f64_nxv4i64(<vscale x 2 x double> %val, double* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv2f64_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei64.v v2, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv2f64.nxv4i64(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv2f64.nxv64i8(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 64 x i8>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv2f64.nxv64i8(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 64 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg3_nxv2f64_nxv64i8(<vscale x 2 x double> %val, double* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv2f64_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vmv2r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv2f64.nxv64i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 64 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv2f64_nxv64i8(<vscale x 2 x double> %val, double* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv2f64_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vmv2r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv2f64.nxv64i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv2f64.nxv4i16(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 4 x i16>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv2f64.nxv4i16(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 4 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg3_nxv2f64_nxv4i16(<vscale x 2 x double> %val, double* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv2f64_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv2f64.nxv4i16(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 4 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv2f64_nxv4i16(<vscale x 2 x double> %val, double* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv2f64_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv2f64.nxv4i16(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv2f64.nxv8i64(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 8 x i64>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv2f64.nxv8i64(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 8 x i64>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg3_nxv2f64_nxv8i64(<vscale x 2 x double> %val, double* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv2f64_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vmv2r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei64.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv2f64.nxv8i64(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 8 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv2f64_nxv8i64(<vscale x 2 x double> %val, double* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv2f64_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vmv2r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei64.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv2f64.nxv8i64(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv2f64.nxv1i8(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv2f64.nxv1i8(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 1 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg3_nxv2f64_nxv1i8(<vscale x 2 x double> %val, double* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv2f64_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv2f64.nxv1i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 1 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv2f64_nxv1i8(<vscale x 2 x double> %val, double* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv2f64_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv2f64.nxv1i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv2f64.nxv2i8(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i8>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv2f64.nxv2i8(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg3_nxv2f64_nxv2i8(<vscale x 2 x double> %val, double* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv2f64_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv2f64.nxv2i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 2 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv2f64_nxv2i8(<vscale x 2 x double> %val, double* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv2f64_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv2f64.nxv2i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv2f64.nxv8i32(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 8 x i32>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv2f64.nxv8i32(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 8 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg3_nxv2f64_nxv8i32(<vscale x 2 x double> %val, double* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv2f64_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv2f64.nxv8i32(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 8 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv2f64_nxv8i32(<vscale x 2 x double> %val, double* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv2f64_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v2, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv2f64.nxv8i32(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv2f64.nxv32i8(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 32 x i8>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv2f64.nxv32i8(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 32 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg3_nxv2f64_nxv32i8(<vscale x 2 x double> %val, double* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv2f64_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv2f64.nxv32i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 32 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv2f64_nxv32i8(<vscale x 2 x double> %val, double* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv2f64_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v2, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv2f64.nxv32i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv2f64.nxv16i32(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 16 x i32>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv2f64.nxv16i32(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 16 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg3_nxv2f64_nxv16i32(<vscale x 2 x double> %val, double* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv2f64_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vmv2r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv2f64.nxv16i32(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 16 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv2f64_nxv16i32(<vscale x 2 x double> %val, double* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv2f64_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vmv2r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv2f64.nxv16i32(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv2f64.nxv2i16(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i16>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv2f64.nxv2i16(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg3_nxv2f64_nxv2i16(<vscale x 2 x double> %val, double* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv2f64_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv2f64.nxv2i16(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 2 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv2f64_nxv2i16(<vscale x 2 x double> %val, double* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv2f64_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv2f64.nxv2i16(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv2f64.nxv2i64(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i64>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv2f64.nxv2i64(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg3_nxv2f64_nxv2i64(<vscale x 2 x double> %val, double* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv2f64_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei64.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv2f64.nxv2i64(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 2 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv2f64_nxv2i64(<vscale x 2 x double> %val, double* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv2f64_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei64.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv2f64.nxv2i64(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv2f64.nxv16i16(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 16 x i16>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv2f64.nxv16i16(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 16 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg4_nxv2f64_nxv16i16(<vscale x 2 x double> %val, double* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv2f64_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vmv2r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv2f64.nxv16i16(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 16 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv2f64_nxv16i16(<vscale x 2 x double> %val, double* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv2f64_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v2, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv2f64.nxv16i16(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv2f64.nxv32i16(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 32 x i16>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv2f64.nxv32i16(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 32 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg4_nxv2f64_nxv32i16(<vscale x 2 x double> %val, double* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv2f64_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2_v22m2
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vmv2r.v v20, v16
+; CHECK-NEXT:    vmv2r.v v22, v16
+; CHECK-NEXT:    vsetvli a1, a2, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv2f64.nxv32i16(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 32 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv2f64_nxv32i16(<vscale x 2 x double> %val, double* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv2f64_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2_v22m2
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vmv2r.v v20, v16
+; CHECK-NEXT:    vmv2r.v v22, v16
+; CHECK-NEXT:    vsetvli a1, a2, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv2f64.nxv32i16(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv2f64.nxv4i32(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 4 x i32>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv2f64.nxv4i32(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 4 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg4_nxv2f64_nxv4i32(<vscale x 2 x double> %val, double* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv2f64_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vmv2r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv2f64.nxv4i32(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 4 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv2f64_nxv4i32(<vscale x 2 x double> %val, double* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv2f64_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv2f64.nxv4i32(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv2f64.nxv16i8(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 16 x i8>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv2f64.nxv16i8(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 16 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg4_nxv2f64_nxv16i8(<vscale x 2 x double> %val, double* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv2f64_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vmv2r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv2f64.nxv16i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 16 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv2f64_nxv16i8(<vscale x 2 x double> %val, double* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv2f64_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv2f64.nxv16i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv2f64.nxv1i64(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv2f64.nxv1i64(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 1 x i64>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg4_nxv2f64_nxv1i64(<vscale x 2 x double> %val, double* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv2f64_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vmv2r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei64.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv2f64.nxv1i64(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 1 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv2f64_nxv1i64(<vscale x 2 x double> %val, double* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv2f64_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei64.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv2f64.nxv1i64(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv2f64.nxv1i32(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv2f64.nxv1i32(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 1 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg4_nxv2f64_nxv1i32(<vscale x 2 x double> %val, double* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv2f64_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vmv2r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv2f64.nxv1i32(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 1 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv2f64_nxv1i32(<vscale x 2 x double> %val, double* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv2f64_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv2f64.nxv1i32(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv2f64.nxv8i16(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 8 x i16>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv2f64.nxv8i16(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 8 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg4_nxv2f64_nxv8i16(<vscale x 2 x double> %val, double* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv2f64_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vmv2r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv2f64.nxv8i16(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 8 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv2f64_nxv8i16(<vscale x 2 x double> %val, double* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv2f64_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv2f64.nxv8i16(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv2f64.nxv4i8(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 4 x i8>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv2f64.nxv4i8(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 4 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg4_nxv2f64_nxv4i8(<vscale x 2 x double> %val, double* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv2f64_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vmv2r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv2f64.nxv4i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 4 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv2f64_nxv4i8(<vscale x 2 x double> %val, double* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv2f64_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv2f64.nxv4i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv2f64.nxv1i16(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv2f64.nxv1i16(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 1 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg4_nxv2f64_nxv1i16(<vscale x 2 x double> %val, double* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv2f64_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vmv2r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv2f64.nxv1i16(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 1 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv2f64_nxv1i16(<vscale x 2 x double> %val, double* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv2f64_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv2f64.nxv1i16(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv2f64.nxv2i32(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i32>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv2f64.nxv2i32(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg4_nxv2f64_nxv2i32(<vscale x 2 x double> %val, double* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv2f64_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vmv2r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv2f64.nxv2i32(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 2 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv2f64_nxv2i32(<vscale x 2 x double> %val, double* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv2f64_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv2f64.nxv2i32(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv2f64.nxv8i8(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 8 x i8>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv2f64.nxv8i8(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 8 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg4_nxv2f64_nxv8i8(<vscale x 2 x double> %val, double* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv2f64_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vmv2r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv2f64.nxv8i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 8 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv2f64_nxv8i8(<vscale x 2 x double> %val, double* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv2f64_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv2f64.nxv8i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv2f64.nxv4i64(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 4 x i64>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv2f64.nxv4i64(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 4 x i64>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg4_nxv2f64_nxv4i64(<vscale x 2 x double> %val, double* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv2f64_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vmv2r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei64.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv2f64.nxv4i64(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 4 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv2f64_nxv4i64(<vscale x 2 x double> %val, double* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv2f64_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei64.v v2, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv2f64.nxv4i64(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv2f64.nxv64i8(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 64 x i8>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv2f64.nxv64i8(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 64 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg4_nxv2f64_nxv64i8(<vscale x 2 x double> %val, double* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv2f64_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2_v22m2
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vmv2r.v v20, v16
+; CHECK-NEXT:    vmv2r.v v22, v16
+; CHECK-NEXT:    vsetvli a1, a2, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv2f64.nxv64i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 64 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv2f64_nxv64i8(<vscale x 2 x double> %val, double* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv2f64_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2_v22m2
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vmv2r.v v20, v16
+; CHECK-NEXT:    vmv2r.v v22, v16
+; CHECK-NEXT:    vsetvli a1, a2, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv2f64.nxv64i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv2f64.nxv4i16(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 4 x i16>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv2f64.nxv4i16(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 4 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg4_nxv2f64_nxv4i16(<vscale x 2 x double> %val, double* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv2f64_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vmv2r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv2f64.nxv4i16(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 4 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv2f64_nxv4i16(<vscale x 2 x double> %val, double* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv2f64_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv2f64.nxv4i16(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv2f64.nxv8i64(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 8 x i64>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv2f64.nxv8i64(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 8 x i64>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg4_nxv2f64_nxv8i64(<vscale x 2 x double> %val, double* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv2f64_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2_v22m2
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vmv2r.v v20, v16
+; CHECK-NEXT:    vmv2r.v v22, v16
+; CHECK-NEXT:    vsetvli a1, a2, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei64.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv2f64.nxv8i64(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 8 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv2f64_nxv8i64(<vscale x 2 x double> %val, double* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv2f64_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2_v22m2
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vmv2r.v v20, v16
+; CHECK-NEXT:    vmv2r.v v22, v16
+; CHECK-NEXT:    vsetvli a1, a2, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei64.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv2f64.nxv8i64(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv2f64.nxv1i8(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv2f64.nxv1i8(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 1 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg4_nxv2f64_nxv1i8(<vscale x 2 x double> %val, double* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv2f64_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vmv2r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv2f64.nxv1i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 1 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv2f64_nxv1i8(<vscale x 2 x double> %val, double* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv2f64_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv2f64.nxv1i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv2f64.nxv2i8(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i8>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv2f64.nxv2i8(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg4_nxv2f64_nxv2i8(<vscale x 2 x double> %val, double* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv2f64_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vmv2r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv2f64.nxv2i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 2 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv2f64_nxv2i8(<vscale x 2 x double> %val, double* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv2f64_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv2f64.nxv2i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv2f64.nxv8i32(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 8 x i32>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv2f64.nxv8i32(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 8 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg4_nxv2f64_nxv8i32(<vscale x 2 x double> %val, double* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv2f64_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vmv2r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv2f64.nxv8i32(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 8 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv2f64_nxv8i32(<vscale x 2 x double> %val, double* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv2f64_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v2, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv2f64.nxv8i32(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv2f64.nxv32i8(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 32 x i8>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv2f64.nxv32i8(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 32 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg4_nxv2f64_nxv32i8(<vscale x 2 x double> %val, double* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv2f64_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vmv2r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv2f64.nxv32i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 32 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv2f64_nxv32i8(<vscale x 2 x double> %val, double* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv2f64_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v2, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv2f64.nxv32i8(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv2f64.nxv16i32(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 16 x i32>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv2f64.nxv16i32(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 16 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg4_nxv2f64_nxv16i32(<vscale x 2 x double> %val, double* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv2f64_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2_v22m2
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vmv2r.v v20, v16
+; CHECK-NEXT:    vmv2r.v v22, v16
+; CHECK-NEXT:    vsetvli a1, a2, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv2f64.nxv16i32(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 16 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv2f64_nxv16i32(<vscale x 2 x double> %val, double* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv2f64_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2_v22m2
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vmv2r.v v20, v16
+; CHECK-NEXT:    vmv2r.v v22, v16
+; CHECK-NEXT:    vsetvli a1, a2, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv2f64.nxv16i32(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv2f64.nxv2i16(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i16>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv2f64.nxv2i16(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg4_nxv2f64_nxv2i16(<vscale x 2 x double> %val, double* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv2f64_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vmv2r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv2f64.nxv2i16(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 2 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv2f64_nxv2i16(<vscale x 2 x double> %val, double* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv2f64_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv2f64.nxv2i16(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv2f64.nxv2i64(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i64>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv2f64.nxv2i64(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg4_nxv2f64_nxv2i64(<vscale x 2 x double> %val, double* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv2f64_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vmv2r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei64.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv2f64.nxv2i64(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 2 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv2f64_nxv2i64(<vscale x 2 x double> %val, double* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv2f64_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei64.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv2f64.nxv2i64(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv4f16.nxv16i16(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i16>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv4f16.nxv16i16(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i16>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg2_nxv4f16_nxv16i16(<vscale x 4 x half> %val, half* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv4f16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv4f16.nxv16i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 16 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv4f16_nxv16i16(<vscale x 4 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv4f16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv4f16.nxv16i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv4f16.nxv32i16(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 32 x i16>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv4f16.nxv32i16(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 32 x i16>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg2_nxv4f16_nxv32i16(<vscale x 4 x half> %val, half* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv4f16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv4f16.nxv32i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 32 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv4f16_nxv32i16(<vscale x 4 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv4f16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv4f16.nxv32i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv4f16.nxv4i32(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i32>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv4f16.nxv4i32(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i32>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg2_nxv4f16_nxv4i32(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv4f16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv4f16.nxv4i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv4f16_nxv4i32(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv4f16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv4f16.nxv4i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv4f16.nxv16i8(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv4f16.nxv16i8(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg2_nxv4f16_nxv16i8(<vscale x 4 x half> %val, half* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv4f16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv4f16.nxv16i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 16 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv4f16_nxv16i8(<vscale x 4 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv4f16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv4f16.nxv16i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv4f16.nxv1i64(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv4f16.nxv1i64(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i64>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg2_nxv4f16_nxv1i64(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv4f16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv4f16.nxv1i64(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv4f16_nxv1i64(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv4f16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv4f16.nxv1i64(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv4f16.nxv1i32(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv4f16.nxv1i32(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i32>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg2_nxv4f16_nxv1i32(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv4f16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv4f16.nxv1i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv4f16_nxv1i32(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv4f16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv4f16.nxv1i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv4f16.nxv8i16(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i16>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv4f16.nxv8i16(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i16>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg2_nxv4f16_nxv8i16(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv4f16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv4f16.nxv8i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv4f16_nxv8i16(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv4f16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv4f16.nxv8i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv4f16.nxv4i8(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv4f16.nxv4i8(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg2_nxv4f16_nxv4i8(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv4f16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv4f16.nxv4i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv4f16_nxv4i8(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv4f16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv4f16.nxv4i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv4f16.nxv1i16(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv4f16.nxv1i16(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i16>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg2_nxv4f16_nxv1i16(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv4f16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv4f16.nxv1i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv4f16_nxv1i16(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv4f16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv4f16.nxv1i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv4f16.nxv2i32(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i32>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv4f16.nxv2i32(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i32>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg2_nxv4f16_nxv2i32(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv4f16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv4f16.nxv2i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv4f16_nxv2i32(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv4f16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv4f16.nxv2i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv4f16.nxv8i8(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv4f16.nxv8i8(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg2_nxv4f16_nxv8i8(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv4f16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv4f16.nxv8i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv4f16_nxv8i8(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv4f16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv4f16.nxv8i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv4f16.nxv4i64(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i64>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv4f16.nxv4i64(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i64>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg2_nxv4f16_nxv4i64(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv4f16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv4f16.nxv4i64(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv4f16_nxv4i64(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv4f16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv4f16.nxv4i64(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv4f16.nxv64i8(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 64 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv4f16.nxv64i8(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 64 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg2_nxv4f16_nxv64i8(<vscale x 4 x half> %val, half* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv4f16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv4f16.nxv64i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 64 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv4f16_nxv64i8(<vscale x 4 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv4f16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv4f16.nxv64i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv4f16.nxv4i16(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i16>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv4f16.nxv4i16(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i16>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg2_nxv4f16_nxv4i16(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv4f16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv4f16.nxv4i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv4f16_nxv4i16(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv4f16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv4f16.nxv4i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv4f16.nxv8i64(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i64>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv4f16.nxv8i64(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i64>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg2_nxv4f16_nxv8i64(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv4f16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv4f16.nxv8i64(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv4f16_nxv8i64(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv4f16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv4f16.nxv8i64(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv4f16.nxv1i8(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv4f16.nxv1i8(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg2_nxv4f16_nxv1i8(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv4f16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv4f16.nxv1i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv4f16_nxv1i8(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv4f16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv4f16.nxv1i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv4f16.nxv2i8(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv4f16.nxv2i8(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg2_nxv4f16_nxv2i8(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv4f16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv4f16.nxv2i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv4f16_nxv2i8(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv4f16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv4f16.nxv2i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv4f16.nxv8i32(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i32>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv4f16.nxv8i32(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i32>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg2_nxv4f16_nxv8i32(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv4f16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv4f16.nxv8i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv4f16_nxv8i32(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv4f16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv4f16.nxv8i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv4f16.nxv32i8(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 32 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv4f16.nxv32i8(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 32 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg2_nxv4f16_nxv32i8(<vscale x 4 x half> %val, half* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv4f16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv4f16.nxv32i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 32 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv4f16_nxv32i8(<vscale x 4 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv4f16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv4f16.nxv32i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv4f16.nxv16i32(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i32>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv4f16.nxv16i32(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i32>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg2_nxv4f16_nxv16i32(<vscale x 4 x half> %val, half* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv4f16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv4f16.nxv16i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 16 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv4f16_nxv16i32(<vscale x 4 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv4f16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv4f16.nxv16i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv4f16.nxv2i16(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i16>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv4f16.nxv2i16(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i16>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg2_nxv4f16_nxv2i16(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv4f16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv4f16.nxv2i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv4f16_nxv2i16(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv4f16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv4f16.nxv2i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv4f16.nxv2i64(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i64>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv4f16.nxv2i64(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i64>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg2_nxv4f16_nxv2i64(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv4f16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv4f16.nxv2i64(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv4f16_nxv2i64(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv4f16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv4f16.nxv2i64(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv4f16.nxv16i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i16>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv4f16.nxv16i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i16>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg3_nxv4f16_nxv16i16(<vscale x 4 x half> %val, half* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv4f16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv4f16.nxv16i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 16 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv4f16_nxv16i16(<vscale x 4 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv4f16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv4f16.nxv16i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv4f16.nxv32i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 32 x i16>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv4f16.nxv32i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 32 x i16>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg3_nxv4f16_nxv32i16(<vscale x 4 x half> %val, half* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv4f16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv4f16.nxv32i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 32 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv4f16_nxv32i16(<vscale x 4 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv4f16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv4f16.nxv32i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv4f16.nxv4i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i32>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv4f16.nxv4i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i32>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg3_nxv4f16_nxv4i32(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv4f16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv4f16.nxv4i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv4f16_nxv4i32(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv4f16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv4f16.nxv4i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv4f16.nxv16i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i8>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv4f16.nxv16i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg3_nxv4f16_nxv16i8(<vscale x 4 x half> %val, half* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv4f16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv4f16.nxv16i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 16 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv4f16_nxv16i8(<vscale x 4 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv4f16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv4f16.nxv16i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv4f16.nxv1i64(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv4f16.nxv1i64(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i64>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg3_nxv4f16_nxv1i64(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv4f16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei64.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv4f16.nxv1i64(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv4f16_nxv1i64(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv4f16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei64.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv4f16.nxv1i64(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv4f16.nxv1i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv4f16.nxv1i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i32>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg3_nxv4f16_nxv1i32(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv4f16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv4f16.nxv1i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv4f16_nxv1i32(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv4f16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv4f16.nxv1i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv4f16.nxv8i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i16>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv4f16.nxv8i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i16>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg3_nxv4f16_nxv8i16(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv4f16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv4f16.nxv8i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv4f16_nxv8i16(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv4f16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv4f16.nxv8i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv4f16.nxv4i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i8>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv4f16.nxv4i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg3_nxv4f16_nxv4i8(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv4f16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv4f16.nxv4i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv4f16_nxv4i8(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv4f16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv4f16.nxv4i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv4f16.nxv1i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv4f16.nxv1i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i16>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg3_nxv4f16_nxv1i16(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv4f16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv4f16.nxv1i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv4f16_nxv1i16(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv4f16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv4f16.nxv1i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv4f16.nxv2i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i32>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv4f16.nxv2i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i32>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg3_nxv4f16_nxv2i32(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv4f16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv4f16.nxv2i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv4f16_nxv2i32(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv4f16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv4f16.nxv2i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv4f16.nxv8i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i8>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv4f16.nxv8i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg3_nxv4f16_nxv8i8(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv4f16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv4f16.nxv8i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv4f16_nxv8i8(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv4f16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv4f16.nxv8i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv4f16.nxv4i64(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i64>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv4f16.nxv4i64(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i64>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg3_nxv4f16_nxv4i64(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv4f16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei64.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv4f16.nxv4i64(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv4f16_nxv4i64(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv4f16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei64.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv4f16.nxv4i64(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv4f16.nxv64i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 64 x i8>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv4f16.nxv64i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 64 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg3_nxv4f16_nxv64i8(<vscale x 4 x half> %val, half* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv4f16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv4f16.nxv64i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 64 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv4f16_nxv64i8(<vscale x 4 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv4f16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv4f16.nxv64i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv4f16.nxv4i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i16>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv4f16.nxv4i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i16>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg3_nxv4f16_nxv4i16(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv4f16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv4f16.nxv4i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv4f16_nxv4i16(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv4f16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv4f16.nxv4i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv4f16.nxv8i64(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i64>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv4f16.nxv8i64(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i64>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg3_nxv4f16_nxv8i64(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv4f16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei64.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv4f16.nxv8i64(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv4f16_nxv8i64(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv4f16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei64.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv4f16.nxv8i64(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv4f16.nxv1i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv4f16.nxv1i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg3_nxv4f16_nxv1i8(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv4f16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv4f16.nxv1i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv4f16_nxv1i8(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv4f16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv4f16.nxv1i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv4f16.nxv2i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i8>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv4f16.nxv2i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg3_nxv4f16_nxv2i8(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv4f16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv4f16.nxv2i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv4f16_nxv2i8(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv4f16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv4f16.nxv2i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv4f16.nxv8i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i32>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv4f16.nxv8i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i32>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg3_nxv4f16_nxv8i32(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv4f16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv4f16.nxv8i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv4f16_nxv8i32(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv4f16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv4f16.nxv8i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv4f16.nxv32i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 32 x i8>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv4f16.nxv32i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 32 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg3_nxv4f16_nxv32i8(<vscale x 4 x half> %val, half* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv4f16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv4f16.nxv32i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 32 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv4f16_nxv32i8(<vscale x 4 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv4f16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv4f16.nxv32i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv4f16.nxv16i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i32>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv4f16.nxv16i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i32>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg3_nxv4f16_nxv16i32(<vscale x 4 x half> %val, half* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv4f16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv4f16.nxv16i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 16 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv4f16_nxv16i32(<vscale x 4 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv4f16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv4f16.nxv16i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv4f16.nxv2i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i16>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv4f16.nxv2i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i16>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg3_nxv4f16_nxv2i16(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv4f16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv4f16.nxv2i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv4f16_nxv2i16(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv4f16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv4f16.nxv2i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv4f16.nxv2i64(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i64>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv4f16.nxv2i64(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i64>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg3_nxv4f16_nxv2i64(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv4f16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei64.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv4f16.nxv2i64(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv4f16_nxv2i64(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv4f16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg3ei64.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv4f16.nxv2i64(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv4f16.nxv16i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i16>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv4f16.nxv16i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i16>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg4_nxv4f16_nxv16i16(<vscale x 4 x half> %val, half* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv4f16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv4f16.nxv16i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 16 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv4f16_nxv16i16(<vscale x 4 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv4f16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv4f16.nxv16i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv4f16.nxv32i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 32 x i16>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv4f16.nxv32i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 32 x i16>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg4_nxv4f16_nxv32i16(<vscale x 4 x half> %val, half* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv4f16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv4f16.nxv32i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 32 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv4f16_nxv32i16(<vscale x 4 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv4f16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv4f16.nxv32i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv4f16.nxv4i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i32>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv4f16.nxv4i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i32>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg4_nxv4f16_nxv4i32(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv4f16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv4f16.nxv4i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv4f16_nxv4i32(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv4f16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv4f16.nxv4i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv4f16.nxv16i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i8>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv4f16.nxv16i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg4_nxv4f16_nxv16i8(<vscale x 4 x half> %val, half* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv4f16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv4f16.nxv16i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 16 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv4f16_nxv16i8(<vscale x 4 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv4f16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv4f16.nxv16i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv4f16.nxv1i64(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv4f16.nxv1i64(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i64>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg4_nxv4f16_nxv1i64(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv4f16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei64.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv4f16.nxv1i64(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv4f16_nxv1i64(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv4f16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei64.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv4f16.nxv1i64(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv4f16.nxv1i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv4f16.nxv1i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i32>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg4_nxv4f16_nxv1i32(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv4f16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv4f16.nxv1i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv4f16_nxv1i32(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv4f16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv4f16.nxv1i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv4f16.nxv8i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i16>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv4f16.nxv8i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i16>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg4_nxv4f16_nxv8i16(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv4f16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv4f16.nxv8i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv4f16_nxv8i16(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv4f16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv4f16.nxv8i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv4f16.nxv4i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i8>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv4f16.nxv4i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg4_nxv4f16_nxv4i8(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv4f16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv4f16.nxv4i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv4f16_nxv4i8(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv4f16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv4f16.nxv4i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv4f16.nxv1i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv4f16.nxv1i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i16>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg4_nxv4f16_nxv1i16(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv4f16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv4f16.nxv1i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv4f16_nxv1i16(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv4f16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv4f16.nxv1i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv4f16.nxv2i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i32>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv4f16.nxv2i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i32>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg4_nxv4f16_nxv2i32(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv4f16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv4f16.nxv2i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv4f16_nxv2i32(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv4f16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv4f16.nxv2i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv4f16.nxv8i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i8>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv4f16.nxv8i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg4_nxv4f16_nxv8i8(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv4f16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv4f16.nxv8i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv4f16_nxv8i8(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv4f16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv4f16.nxv8i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv4f16.nxv4i64(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i64>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv4f16.nxv4i64(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i64>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg4_nxv4f16_nxv4i64(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv4f16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei64.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv4f16.nxv4i64(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv4f16_nxv4i64(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv4f16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei64.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv4f16.nxv4i64(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv4f16.nxv64i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 64 x i8>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv4f16.nxv64i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 64 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg4_nxv4f16_nxv64i8(<vscale x 4 x half> %val, half* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv4f16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv4f16.nxv64i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 64 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv4f16_nxv64i8(<vscale x 4 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv4f16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv4f16.nxv64i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv4f16.nxv4i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i16>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv4f16.nxv4i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i16>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg4_nxv4f16_nxv4i16(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv4f16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv4f16.nxv4i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv4f16_nxv4i16(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv4f16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv4f16.nxv4i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv4f16.nxv8i64(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i64>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv4f16.nxv8i64(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i64>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg4_nxv4f16_nxv8i64(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv4f16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei64.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv4f16.nxv8i64(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv4f16_nxv8i64(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv4f16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei64.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv4f16.nxv8i64(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv4f16.nxv1i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv4f16.nxv1i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg4_nxv4f16_nxv1i8(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv4f16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv4f16.nxv1i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv4f16_nxv1i8(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv4f16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv4f16.nxv1i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv4f16.nxv2i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i8>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv4f16.nxv2i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg4_nxv4f16_nxv2i8(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv4f16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv4f16.nxv2i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv4f16_nxv2i8(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv4f16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv4f16.nxv2i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv4f16.nxv8i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i32>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv4f16.nxv8i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i32>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg4_nxv4f16_nxv8i32(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv4f16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv4f16.nxv8i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv4f16_nxv8i32(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv4f16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv4f16.nxv8i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv4f16.nxv32i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 32 x i8>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv4f16.nxv32i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 32 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg4_nxv4f16_nxv32i8(<vscale x 4 x half> %val, half* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv4f16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv4f16.nxv32i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 32 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv4f16_nxv32i8(<vscale x 4 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv4f16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv4f16.nxv32i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv4f16.nxv16i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i32>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv4f16.nxv16i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i32>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg4_nxv4f16_nxv16i32(<vscale x 4 x half> %val, half* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv4f16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv4f16.nxv16i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 16 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv4f16_nxv16i32(<vscale x 4 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv4f16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv4f16.nxv16i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv4f16.nxv2i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i16>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv4f16.nxv2i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i16>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg4_nxv4f16_nxv2i16(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv4f16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv4f16.nxv2i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv4f16_nxv2i16(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv4f16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv4f16.nxv2i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv4f16.nxv2i64(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i64>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv4f16.nxv2i64(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i64>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg4_nxv4f16_nxv2i64(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv4f16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei64.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv4f16.nxv2i64(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv4f16_nxv2i64(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv4f16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg4ei64.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv4f16.nxv2i64(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv4f16.nxv16i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i16>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv4f16.nxv16i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i16>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg5_nxv4f16_nxv16i16(<vscale x 4 x half> %val, half* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv4f16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv4f16.nxv16i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 16 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv4f16_nxv16i16(<vscale x 4 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv4f16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv4f16.nxv16i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv4f16.nxv32i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 32 x i16>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv4f16.nxv32i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 32 x i16>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg5_nxv4f16_nxv32i16(<vscale x 4 x half> %val, half* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv4f16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv4f16.nxv32i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 32 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv4f16_nxv32i16(<vscale x 4 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv4f16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv4f16.nxv32i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv4f16.nxv4i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i32>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv4f16.nxv4i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i32>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg5_nxv4f16_nxv4i32(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv4f16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei32.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv4f16.nxv4i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv4f16_nxv4i32(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv4f16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei32.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv4f16.nxv4i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv4f16.nxv16i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i8>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv4f16.nxv16i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg5_nxv4f16_nxv16i8(<vscale x 4 x half> %val, half* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv4f16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv4f16.nxv16i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 16 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv4f16_nxv16i8(<vscale x 4 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv4f16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv4f16.nxv16i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv4f16.nxv1i64(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv4f16.nxv1i64(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i64>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg5_nxv4f16_nxv1i64(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv4f16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei64.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv4f16.nxv1i64(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv4f16_nxv1i64(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv4f16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei64.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv4f16.nxv1i64(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv4f16.nxv1i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv4f16.nxv1i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i32>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg5_nxv4f16_nxv1i32(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv4f16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv4f16.nxv1i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv4f16_nxv1i32(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv4f16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv4f16.nxv1i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv4f16.nxv8i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i16>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv4f16.nxv8i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i16>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg5_nxv4f16_nxv8i16(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv4f16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv4f16.nxv8i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv4f16_nxv8i16(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv4f16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv4f16.nxv8i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv4f16.nxv4i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i8>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv4f16.nxv4i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg5_nxv4f16_nxv4i8(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv4f16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv4f16.nxv4i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv4f16_nxv4i8(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv4f16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv4f16.nxv4i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv4f16.nxv1i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv4f16.nxv1i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i16>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg5_nxv4f16_nxv1i16(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv4f16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv4f16.nxv1i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv4f16_nxv1i16(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv4f16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv4f16.nxv1i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv4f16.nxv2i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i32>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv4f16.nxv2i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i32>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg5_nxv4f16_nxv2i32(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv4f16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv4f16.nxv2i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv4f16_nxv2i32(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv4f16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv4f16.nxv2i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv4f16.nxv8i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i8>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv4f16.nxv8i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg5_nxv4f16_nxv8i8(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv4f16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv4f16.nxv8i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv4f16_nxv8i8(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv4f16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv4f16.nxv8i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv4f16.nxv4i64(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i64>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv4f16.nxv4i64(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i64>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg5_nxv4f16_nxv4i64(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv4f16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei64.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv4f16.nxv4i64(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv4f16_nxv4i64(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv4f16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei64.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv4f16.nxv4i64(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv4f16.nxv64i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 64 x i8>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv4f16.nxv64i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 64 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg5_nxv4f16_nxv64i8(<vscale x 4 x half> %val, half* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv4f16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv4f16.nxv64i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 64 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv4f16_nxv64i8(<vscale x 4 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv4f16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv4f16.nxv64i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv4f16.nxv4i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i16>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv4f16.nxv4i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i16>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg5_nxv4f16_nxv4i16(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv4f16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv4f16.nxv4i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv4f16_nxv4i16(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv4f16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv4f16.nxv4i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv4f16.nxv8i64(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i64>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv4f16.nxv8i64(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i64>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg5_nxv4f16_nxv8i64(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv4f16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei64.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv4f16.nxv8i64(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv4f16_nxv8i64(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv4f16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei64.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv4f16.nxv8i64(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv4f16.nxv1i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv4f16.nxv1i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg5_nxv4f16_nxv1i8(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv4f16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv4f16.nxv1i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv4f16_nxv1i8(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv4f16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv4f16.nxv1i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv4f16.nxv2i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i8>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv4f16.nxv2i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg5_nxv4f16_nxv2i8(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv4f16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv4f16.nxv2i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv4f16_nxv2i8(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv4f16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv4f16.nxv2i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv4f16.nxv8i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i32>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv4f16.nxv8i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i32>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg5_nxv4f16_nxv8i32(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv4f16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei32.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv4f16.nxv8i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv4f16_nxv8i32(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv4f16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei32.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv4f16.nxv8i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv4f16.nxv32i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 32 x i8>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv4f16.nxv32i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 32 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg5_nxv4f16_nxv32i8(<vscale x 4 x half> %val, half* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv4f16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv4f16.nxv32i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 32 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv4f16_nxv32i8(<vscale x 4 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv4f16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv4f16.nxv32i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv4f16.nxv16i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i32>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv4f16.nxv16i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i32>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg5_nxv4f16_nxv16i32(<vscale x 4 x half> %val, half* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv4f16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei32.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv4f16.nxv16i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 16 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv4f16_nxv16i32(<vscale x 4 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv4f16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei32.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv4f16.nxv16i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv4f16.nxv2i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i16>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv4f16.nxv2i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i16>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg5_nxv4f16_nxv2i16(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv4f16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv4f16.nxv2i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv4f16_nxv2i16(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv4f16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv4f16.nxv2i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv4f16.nxv2i64(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i64>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv4f16.nxv2i64(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i64>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg5_nxv4f16_nxv2i64(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv4f16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei64.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv4f16.nxv2i64(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv4f16_nxv2i64(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv4f16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg5ei64.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv4f16.nxv2i64(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv4f16.nxv16i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i16>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv4f16.nxv16i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i16>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg6_nxv4f16_nxv16i16(<vscale x 4 x half> %val, half* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv4f16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv4f16.nxv16i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 16 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv4f16_nxv16i16(<vscale x 4 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv4f16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv4f16.nxv16i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv4f16.nxv32i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 32 x i16>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv4f16.nxv32i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 32 x i16>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg6_nxv4f16_nxv32i16(<vscale x 4 x half> %val, half* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv4f16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv4f16.nxv32i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 32 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv4f16_nxv32i16(<vscale x 4 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv4f16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv4f16.nxv32i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv4f16.nxv4i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i32>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv4f16.nxv4i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i32>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg6_nxv4f16_nxv4i32(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv4f16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei32.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv4f16.nxv4i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv4f16_nxv4i32(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv4f16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei32.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv4f16.nxv4i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv4f16.nxv16i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i8>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv4f16.nxv16i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg6_nxv4f16_nxv16i8(<vscale x 4 x half> %val, half* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv4f16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv4f16.nxv16i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 16 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv4f16_nxv16i8(<vscale x 4 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv4f16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv4f16.nxv16i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv4f16.nxv1i64(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv4f16.nxv1i64(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i64>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg6_nxv4f16_nxv1i64(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv4f16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei64.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv4f16.nxv1i64(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv4f16_nxv1i64(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv4f16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei64.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv4f16.nxv1i64(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv4f16.nxv1i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv4f16.nxv1i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i32>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg6_nxv4f16_nxv1i32(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv4f16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv4f16.nxv1i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv4f16_nxv1i32(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv4f16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv4f16.nxv1i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv4f16.nxv8i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i16>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv4f16.nxv8i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i16>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg6_nxv4f16_nxv8i16(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv4f16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv4f16.nxv8i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv4f16_nxv8i16(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv4f16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv4f16.nxv8i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv4f16.nxv4i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i8>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv4f16.nxv4i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg6_nxv4f16_nxv4i8(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv4f16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv4f16.nxv4i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv4f16_nxv4i8(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv4f16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv4f16.nxv4i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv4f16.nxv1i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv4f16.nxv1i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i16>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg6_nxv4f16_nxv1i16(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv4f16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv4f16.nxv1i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv4f16_nxv1i16(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv4f16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv4f16.nxv1i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv4f16.nxv2i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i32>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv4f16.nxv2i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i32>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg6_nxv4f16_nxv2i32(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv4f16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv4f16.nxv2i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv4f16_nxv2i32(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv4f16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv4f16.nxv2i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv4f16.nxv8i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i8>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv4f16.nxv8i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg6_nxv4f16_nxv8i8(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv4f16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv4f16.nxv8i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv4f16_nxv8i8(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv4f16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv4f16.nxv8i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv4f16.nxv4i64(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i64>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv4f16.nxv4i64(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i64>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg6_nxv4f16_nxv4i64(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv4f16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei64.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv4f16.nxv4i64(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv4f16_nxv4i64(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv4f16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei64.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv4f16.nxv4i64(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv4f16.nxv64i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 64 x i8>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv4f16.nxv64i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 64 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg6_nxv4f16_nxv64i8(<vscale x 4 x half> %val, half* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv4f16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv4f16.nxv64i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 64 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv4f16_nxv64i8(<vscale x 4 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv4f16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv4f16.nxv64i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv4f16.nxv4i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i16>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv4f16.nxv4i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i16>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg6_nxv4f16_nxv4i16(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv4f16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv4f16.nxv4i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv4f16_nxv4i16(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv4f16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv4f16.nxv4i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv4f16.nxv8i64(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i64>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv4f16.nxv8i64(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i64>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg6_nxv4f16_nxv8i64(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv4f16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei64.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv4f16.nxv8i64(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv4f16_nxv8i64(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv4f16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei64.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv4f16.nxv8i64(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv4f16.nxv1i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv4f16.nxv1i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg6_nxv4f16_nxv1i8(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv4f16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv4f16.nxv1i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv4f16_nxv1i8(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv4f16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv4f16.nxv1i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv4f16.nxv2i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i8>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv4f16.nxv2i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg6_nxv4f16_nxv2i8(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv4f16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv4f16.nxv2i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv4f16_nxv2i8(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv4f16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv4f16.nxv2i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv4f16.nxv8i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i32>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv4f16.nxv8i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i32>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg6_nxv4f16_nxv8i32(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv4f16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei32.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv4f16.nxv8i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv4f16_nxv8i32(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv4f16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei32.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv4f16.nxv8i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv4f16.nxv32i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 32 x i8>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv4f16.nxv32i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 32 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg6_nxv4f16_nxv32i8(<vscale x 4 x half> %val, half* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv4f16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv4f16.nxv32i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 32 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv4f16_nxv32i8(<vscale x 4 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv4f16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv4f16.nxv32i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv4f16.nxv16i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i32>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv4f16.nxv16i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i32>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg6_nxv4f16_nxv16i32(<vscale x 4 x half> %val, half* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv4f16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei32.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv4f16.nxv16i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 16 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv4f16_nxv16i32(<vscale x 4 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv4f16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei32.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv4f16.nxv16i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv4f16.nxv2i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i16>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv4f16.nxv2i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i16>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg6_nxv4f16_nxv2i16(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv4f16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv4f16.nxv2i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv4f16_nxv2i16(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv4f16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv4f16.nxv2i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv4f16.nxv2i64(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i64>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv4f16.nxv2i64(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i64>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg6_nxv4f16_nxv2i64(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv4f16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei64.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv4f16.nxv2i64(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv4f16_nxv2i64(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv4f16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg6ei64.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv4f16.nxv2i64(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv4f16.nxv16i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i16>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv4f16.nxv16i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i16>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg7_nxv4f16_nxv16i16(<vscale x 4 x half> %val, half* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv4f16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv4f16.nxv16i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 16 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv4f16_nxv16i16(<vscale x 4 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv4f16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv4f16.nxv16i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv4f16.nxv32i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 32 x i16>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv4f16.nxv32i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 32 x i16>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg7_nxv4f16_nxv32i16(<vscale x 4 x half> %val, half* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv4f16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv4f16.nxv32i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 32 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv4f16_nxv32i16(<vscale x 4 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv4f16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv4f16.nxv32i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv4f16.nxv4i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i32>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv4f16.nxv4i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i32>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg7_nxv4f16_nxv4i32(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv4f16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei32.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv4f16.nxv4i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv4f16_nxv4i32(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv4f16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei32.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv4f16.nxv4i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv4f16.nxv16i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i8>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv4f16.nxv16i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg7_nxv4f16_nxv16i8(<vscale x 4 x half> %val, half* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv4f16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv4f16.nxv16i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 16 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv4f16_nxv16i8(<vscale x 4 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv4f16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv4f16.nxv16i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv4f16.nxv1i64(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv4f16.nxv1i64(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i64>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg7_nxv4f16_nxv1i64(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv4f16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei64.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv4f16.nxv1i64(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv4f16_nxv1i64(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv4f16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei64.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv4f16.nxv1i64(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv4f16.nxv1i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv4f16.nxv1i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i32>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg7_nxv4f16_nxv1i32(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv4f16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv4f16.nxv1i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv4f16_nxv1i32(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv4f16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv4f16.nxv1i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv4f16.nxv8i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i16>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv4f16.nxv8i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i16>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg7_nxv4f16_nxv8i16(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv4f16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv4f16.nxv8i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv4f16_nxv8i16(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv4f16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv4f16.nxv8i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv4f16.nxv4i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i8>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv4f16.nxv4i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg7_nxv4f16_nxv4i8(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv4f16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv4f16.nxv4i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv4f16_nxv4i8(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv4f16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv4f16.nxv4i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv4f16.nxv1i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv4f16.nxv1i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i16>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg7_nxv4f16_nxv1i16(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv4f16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv4f16.nxv1i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv4f16_nxv1i16(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv4f16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv4f16.nxv1i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv4f16.nxv2i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i32>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv4f16.nxv2i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i32>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg7_nxv4f16_nxv2i32(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv4f16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv4f16.nxv2i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv4f16_nxv2i32(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv4f16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv4f16.nxv2i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv4f16.nxv8i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i8>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv4f16.nxv8i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg7_nxv4f16_nxv8i8(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv4f16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv4f16.nxv8i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv4f16_nxv8i8(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv4f16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv4f16.nxv8i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv4f16.nxv4i64(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i64>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv4f16.nxv4i64(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i64>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg7_nxv4f16_nxv4i64(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv4f16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei64.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv4f16.nxv4i64(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv4f16_nxv4i64(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv4f16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei64.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv4f16.nxv4i64(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv4f16.nxv64i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 64 x i8>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv4f16.nxv64i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 64 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg7_nxv4f16_nxv64i8(<vscale x 4 x half> %val, half* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv4f16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv4f16.nxv64i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 64 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv4f16_nxv64i8(<vscale x 4 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv4f16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv4f16.nxv64i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv4f16.nxv4i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i16>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv4f16.nxv4i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i16>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg7_nxv4f16_nxv4i16(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv4f16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv4f16.nxv4i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv4f16_nxv4i16(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv4f16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv4f16.nxv4i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv4f16.nxv8i64(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i64>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv4f16.nxv8i64(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i64>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg7_nxv4f16_nxv8i64(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv4f16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei64.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv4f16.nxv8i64(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv4f16_nxv8i64(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv4f16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei64.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv4f16.nxv8i64(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv4f16.nxv1i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv4f16.nxv1i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg7_nxv4f16_nxv1i8(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv4f16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv4f16.nxv1i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv4f16_nxv1i8(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv4f16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv4f16.nxv1i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv4f16.nxv2i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i8>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv4f16.nxv2i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg7_nxv4f16_nxv2i8(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv4f16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv4f16.nxv2i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv4f16_nxv2i8(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv4f16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv4f16.nxv2i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv4f16.nxv8i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i32>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv4f16.nxv8i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i32>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg7_nxv4f16_nxv8i32(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv4f16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei32.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv4f16.nxv8i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv4f16_nxv8i32(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv4f16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei32.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv4f16.nxv8i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv4f16.nxv32i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 32 x i8>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv4f16.nxv32i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 32 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg7_nxv4f16_nxv32i8(<vscale x 4 x half> %val, half* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv4f16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv4f16.nxv32i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 32 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv4f16_nxv32i8(<vscale x 4 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv4f16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv4f16.nxv32i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv4f16.nxv16i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i32>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv4f16.nxv16i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i32>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg7_nxv4f16_nxv16i32(<vscale x 4 x half> %val, half* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv4f16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei32.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv4f16.nxv16i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 16 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv4f16_nxv16i32(<vscale x 4 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv4f16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei32.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv4f16.nxv16i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv4f16.nxv2i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i16>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv4f16.nxv2i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i16>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg7_nxv4f16_nxv2i16(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv4f16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv4f16.nxv2i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv4f16_nxv2i16(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv4f16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv4f16.nxv2i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv4f16.nxv2i64(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i64>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv4f16.nxv2i64(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i64>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg7_nxv4f16_nxv2i64(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv4f16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei64.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv4f16.nxv2i64(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv4f16_nxv2i64(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv4f16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg7ei64.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv4f16.nxv2i64(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv4f16.nxv16i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i16>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv4f16.nxv16i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i16>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg8_nxv4f16_nxv16i16(<vscale x 4 x half> %val, half* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv4f16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv4f16.nxv16i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 16 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv4f16_nxv16i16(<vscale x 4 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv4f16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv4f16.nxv16i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv4f16.nxv32i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 32 x i16>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv4f16.nxv32i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 32 x i16>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg8_nxv4f16_nxv32i16(<vscale x 4 x half> %val, half* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv4f16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vmv1r.v v23, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv4f16.nxv32i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 32 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv4f16_nxv32i16(<vscale x 4 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv4f16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vmv1r.v v23, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv4f16.nxv32i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv4f16.nxv4i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i32>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv4f16.nxv4i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i32>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg8_nxv4f16_nxv4i32(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv4f16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei32.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv4f16.nxv4i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv4f16_nxv4i32(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv4f16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei32.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv4f16.nxv4i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv4f16.nxv16i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i8>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv4f16.nxv16i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg8_nxv4f16_nxv16i8(<vscale x 4 x half> %val, half* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv4f16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv4f16.nxv16i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 16 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv4f16_nxv16i8(<vscale x 4 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv4f16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv4f16.nxv16i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv4f16.nxv1i64(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv4f16.nxv1i64(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i64>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg8_nxv4f16_nxv1i64(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv4f16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei64.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv4f16.nxv1i64(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv4f16_nxv1i64(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv4f16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei64.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv4f16.nxv1i64(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv4f16.nxv1i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv4f16.nxv1i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i32>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg8_nxv4f16_nxv1i32(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv4f16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv4f16.nxv1i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv4f16_nxv1i32(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv4f16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv4f16.nxv1i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv4f16.nxv8i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i16>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv4f16.nxv8i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i16>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg8_nxv4f16_nxv8i16(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv4f16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv4f16.nxv8i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv4f16_nxv8i16(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv4f16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv4f16.nxv8i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv4f16.nxv4i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i8>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv4f16.nxv4i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg8_nxv4f16_nxv4i8(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv4f16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv4f16.nxv4i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv4f16_nxv4i8(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv4f16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv4f16.nxv4i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv4f16.nxv1i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv4f16.nxv1i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i16>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg8_nxv4f16_nxv1i16(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv4f16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv4f16.nxv1i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv4f16_nxv1i16(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv4f16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv4f16.nxv1i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv4f16.nxv2i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i32>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv4f16.nxv2i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i32>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg8_nxv4f16_nxv2i32(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv4f16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv4f16.nxv2i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv4f16_nxv2i32(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv4f16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv4f16.nxv2i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv4f16.nxv8i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i8>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv4f16.nxv8i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg8_nxv4f16_nxv8i8(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv4f16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv4f16.nxv8i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv4f16_nxv8i8(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv4f16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv4f16.nxv8i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv4f16.nxv4i64(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i64>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv4f16.nxv4i64(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i64>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg8_nxv4f16_nxv4i64(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv4f16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei64.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv4f16.nxv4i64(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv4f16_nxv4i64(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv4f16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei64.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv4f16.nxv4i64(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv4f16.nxv64i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 64 x i8>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv4f16.nxv64i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 64 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg8_nxv4f16_nxv64i8(<vscale x 4 x half> %val, half* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv4f16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vmv1r.v v23, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv4f16.nxv64i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 64 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv4f16_nxv64i8(<vscale x 4 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv4f16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vmv1r.v v23, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv4f16.nxv64i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv4f16.nxv4i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i16>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv4f16.nxv4i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i16>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg8_nxv4f16_nxv4i16(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv4f16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv4f16.nxv4i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv4f16_nxv4i16(<vscale x 4 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv4f16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv4f16.nxv4i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv4f16.nxv8i64(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i64>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv4f16.nxv8i64(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i64>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg8_nxv4f16_nxv8i64(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv4f16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vmv1r.v v23, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei64.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv4f16.nxv8i64(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv4f16_nxv8i64(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv4f16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vmv1r.v v23, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei64.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv4f16.nxv8i64(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv4f16.nxv1i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv4f16.nxv1i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 1 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg8_nxv4f16_nxv1i8(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv4f16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv4f16.nxv1i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv4f16_nxv1i8(<vscale x 4 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv4f16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv4f16.nxv1i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv4f16.nxv2i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i8>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv4f16.nxv2i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg8_nxv4f16_nxv2i8(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv4f16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv4f16.nxv2i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv4f16_nxv2i8(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv4f16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv4f16.nxv2i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv4f16.nxv8i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i32>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv4f16.nxv8i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 8 x i32>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg8_nxv4f16_nxv8i32(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv4f16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei32.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv4f16.nxv8i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv4f16_nxv8i32(<vscale x 4 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv4f16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei32.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv4f16.nxv8i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv4f16.nxv32i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 32 x i8>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv4f16.nxv32i8(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 32 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg8_nxv4f16_nxv32i8(<vscale x 4 x half> %val, half* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv4f16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv4f16.nxv32i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 32 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv4f16_nxv32i8(<vscale x 4 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv4f16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv4f16.nxv32i8(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv4f16.nxv16i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i32>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv4f16.nxv16i32(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 16 x i32>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg8_nxv4f16_nxv16i32(<vscale x 4 x half> %val, half* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv4f16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vmv1r.v v23, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei32.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv4f16.nxv16i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 16 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv4f16_nxv16i32(<vscale x 4 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv4f16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vmv1r.v v23, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei32.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv4f16.nxv16i32(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv4f16.nxv2i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i16>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv4f16.nxv2i16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i16>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg8_nxv4f16_nxv2i16(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv4f16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv4f16.nxv2i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv4f16_nxv2i16(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv4f16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv4f16.nxv2i16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv4f16.nxv2i64(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i64>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv4f16.nxv2i64(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 2 x i64>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg8_nxv4f16_nxv2i64(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv4f16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei64.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv4f16.nxv2i64(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv4f16_nxv2i64(<vscale x 4 x half> %val, half* %base, <vscale x 2 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv4f16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vsxseg8ei64.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv4f16.nxv2i64(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 2 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv2f16.nxv16i16(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i16>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv2f16.nxv16i16(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg2_nxv2f16_nxv16i16(<vscale x 2 x half> %val, half* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv2f16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv2f16.nxv16i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 16 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv2f16_nxv16i16(<vscale x 2 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv2f16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv2f16.nxv16i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv2f16.nxv32i16(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 32 x i16>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv2f16.nxv32i16(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 32 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg2_nxv2f16_nxv32i16(<vscale x 2 x half> %val, half* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv2f16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv2f16.nxv32i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 32 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv2f16_nxv32i16(<vscale x 2 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv2f16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv2f16.nxv32i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv2f16.nxv4i32(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i32>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv2f16.nxv4i32(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg2_nxv2f16_nxv4i32(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv2f16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv2f16.nxv4i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv2f16_nxv4i32(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv2f16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv2f16.nxv4i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv2f16.nxv16i8(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv2f16.nxv16i8(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg2_nxv2f16_nxv16i8(<vscale x 2 x half> %val, half* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv2f16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv2f16.nxv16i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 16 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv2f16_nxv16i8(<vscale x 2 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv2f16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv2f16.nxv16i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv2f16.nxv1i64(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv2f16.nxv1i64(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i64>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg2_nxv2f16_nxv1i64(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv2f16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv2f16.nxv1i64(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv2f16_nxv1i64(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv2f16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv2f16.nxv1i64(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv2f16.nxv1i32(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv2f16.nxv1i32(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg2_nxv2f16_nxv1i32(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv2f16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv2f16.nxv1i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv2f16_nxv1i32(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv2f16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv2f16.nxv1i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv2f16.nxv8i16(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i16>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv2f16.nxv8i16(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg2_nxv2f16_nxv8i16(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv2f16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv2f16.nxv8i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv2f16_nxv8i16(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv2f16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv2f16.nxv8i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv2f16.nxv4i8(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv2f16.nxv4i8(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg2_nxv2f16_nxv4i8(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv2f16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv2f16.nxv4i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv2f16_nxv4i8(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv2f16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv2f16.nxv4i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv2f16.nxv1i16(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv2f16.nxv1i16(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg2_nxv2f16_nxv1i16(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv2f16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv2f16.nxv1i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv2f16_nxv1i16(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv2f16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv2f16.nxv1i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv2f16.nxv2i32(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i32>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv2f16.nxv2i32(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg2_nxv2f16_nxv2i32(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv2f16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv2f16.nxv2i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv2f16_nxv2i32(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv2f16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv2f16.nxv2i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv2f16.nxv8i8(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv2f16.nxv8i8(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg2_nxv2f16_nxv8i8(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv2f16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv2f16.nxv8i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv2f16_nxv8i8(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv2f16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv2f16.nxv8i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv2f16.nxv4i64(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i64>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv2f16.nxv4i64(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i64>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg2_nxv2f16_nxv4i64(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv2f16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv2f16.nxv4i64(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv2f16_nxv4i64(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv2f16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv2f16.nxv4i64(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv2f16.nxv64i8(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 64 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv2f16.nxv64i8(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 64 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg2_nxv2f16_nxv64i8(<vscale x 2 x half> %val, half* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv2f16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv2f16.nxv64i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 64 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv2f16_nxv64i8(<vscale x 2 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv2f16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv2f16.nxv64i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv2f16.nxv4i16(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i16>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv2f16.nxv4i16(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg2_nxv2f16_nxv4i16(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv2f16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv2f16.nxv4i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv2f16_nxv4i16(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv2f16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv2f16.nxv4i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv2f16.nxv8i64(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i64>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv2f16.nxv8i64(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i64>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg2_nxv2f16_nxv8i64(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv2f16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv2f16.nxv8i64(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv2f16_nxv8i64(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv2f16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv2f16.nxv8i64(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv2f16.nxv1i8(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv2f16.nxv1i8(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg2_nxv2f16_nxv1i8(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv2f16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv2f16.nxv1i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv2f16_nxv1i8(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv2f16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv2f16.nxv1i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv2f16.nxv2i8(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv2f16.nxv2i8(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg2_nxv2f16_nxv2i8(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv2f16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv2f16.nxv2i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv2f16_nxv2i8(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv2f16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv2f16.nxv2i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv2f16.nxv8i32(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i32>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv2f16.nxv8i32(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg2_nxv2f16_nxv8i32(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv2f16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv2f16.nxv8i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv2f16_nxv8i32(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv2f16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv2f16.nxv8i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv2f16.nxv32i8(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 32 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv2f16.nxv32i8(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 32 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg2_nxv2f16_nxv32i8(<vscale x 2 x half> %val, half* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv2f16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv2f16.nxv32i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 32 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv2f16_nxv32i8(<vscale x 2 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv2f16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv2f16.nxv32i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv2f16.nxv16i32(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i32>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv2f16.nxv16i32(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg2_nxv2f16_nxv16i32(<vscale x 2 x half> %val, half* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv2f16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv2f16.nxv16i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 16 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv2f16_nxv16i32(<vscale x 2 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv2f16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv2f16.nxv16i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv2f16.nxv2i16(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i16>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv2f16.nxv2i16(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg2_nxv2f16_nxv2i16(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv2f16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv2f16.nxv2i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv2f16_nxv2i16(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv2f16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 killed $v16_v17 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v25, v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv2f16.nxv2i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv2f16.nxv2i64(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i64>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv2f16.nxv2i64(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg2_nxv2f16_nxv2i64(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv2f16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv2f16.nxv2i64(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv2f16_nxv2i64(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv2f16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv2f16.nxv2i64(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv2f16.nxv16i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i16>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv2f16.nxv16i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg3_nxv2f16_nxv16i16(<vscale x 2 x half> %val, half* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv2f16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv2f16.nxv16i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 16 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv2f16_nxv16i16(<vscale x 2 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv2f16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv2f16.nxv16i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv2f16.nxv32i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 32 x i16>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv2f16.nxv32i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 32 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg3_nxv2f16_nxv32i16(<vscale x 2 x half> %val, half* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv2f16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv2f16.nxv32i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 32 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv2f16_nxv32i16(<vscale x 2 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv2f16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv2f16.nxv32i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv2f16.nxv4i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i32>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv2f16.nxv4i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg3_nxv2f16_nxv4i32(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv2f16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv2f16.nxv4i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv2f16_nxv4i32(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv2f16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv2f16.nxv4i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv2f16.nxv16i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i8>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv2f16.nxv16i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg3_nxv2f16_nxv16i8(<vscale x 2 x half> %val, half* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv2f16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv2f16.nxv16i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 16 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv2f16_nxv16i8(<vscale x 2 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv2f16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv2f16.nxv16i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv2f16.nxv1i64(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv2f16.nxv1i64(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i64>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg3_nxv2f16_nxv1i64(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv2f16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei64.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv2f16.nxv1i64(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv2f16_nxv1i64(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv2f16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei64.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv2f16.nxv1i64(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv2f16.nxv1i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv2f16.nxv1i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg3_nxv2f16_nxv1i32(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv2f16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv2f16.nxv1i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv2f16_nxv1i32(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv2f16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv2f16.nxv1i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv2f16.nxv8i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i16>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv2f16.nxv8i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg3_nxv2f16_nxv8i16(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv2f16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv2f16.nxv8i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv2f16_nxv8i16(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv2f16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv2f16.nxv8i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv2f16.nxv4i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i8>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv2f16.nxv4i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg3_nxv2f16_nxv4i8(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv2f16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv2f16.nxv4i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv2f16_nxv4i8(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv2f16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv2f16.nxv4i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv2f16.nxv1i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv2f16.nxv1i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg3_nxv2f16_nxv1i16(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv2f16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv2f16.nxv1i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv2f16_nxv1i16(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv2f16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv2f16.nxv1i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv2f16.nxv2i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i32>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv2f16.nxv2i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg3_nxv2f16_nxv2i32(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv2f16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv2f16.nxv2i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv2f16_nxv2i32(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv2f16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv2f16.nxv2i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv2f16.nxv8i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i8>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv2f16.nxv8i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg3_nxv2f16_nxv8i8(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv2f16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv2f16.nxv8i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv2f16_nxv8i8(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv2f16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv2f16.nxv8i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv2f16.nxv4i64(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i64>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv2f16.nxv4i64(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i64>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg3_nxv2f16_nxv4i64(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv2f16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei64.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv2f16.nxv4i64(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv2f16_nxv4i64(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv2f16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei64.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv2f16.nxv4i64(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv2f16.nxv64i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 64 x i8>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv2f16.nxv64i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 64 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg3_nxv2f16_nxv64i8(<vscale x 2 x half> %val, half* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv2f16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv2f16.nxv64i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 64 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv2f16_nxv64i8(<vscale x 2 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv2f16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv2f16.nxv64i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv2f16.nxv4i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i16>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv2f16.nxv4i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg3_nxv2f16_nxv4i16(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv2f16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv2f16.nxv4i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv2f16_nxv4i16(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv2f16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv2f16.nxv4i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv2f16.nxv8i64(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i64>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv2f16.nxv8i64(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i64>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg3_nxv2f16_nxv8i64(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv2f16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei64.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv2f16.nxv8i64(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv2f16_nxv8i64(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv2f16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei64.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv2f16.nxv8i64(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv2f16.nxv1i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv2f16.nxv1i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg3_nxv2f16_nxv1i8(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv2f16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv2f16.nxv1i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv2f16_nxv1i8(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv2f16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv2f16.nxv1i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv2f16.nxv2i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i8>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv2f16.nxv2i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg3_nxv2f16_nxv2i8(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv2f16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv2f16.nxv2i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv2f16_nxv2i8(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv2f16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv2f16.nxv2i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv2f16.nxv8i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i32>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv2f16.nxv8i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg3_nxv2f16_nxv8i32(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv2f16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv2f16.nxv8i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv2f16_nxv8i32(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv2f16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv2f16.nxv8i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv2f16.nxv32i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 32 x i8>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv2f16.nxv32i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 32 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg3_nxv2f16_nxv32i8(<vscale x 2 x half> %val, half* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv2f16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv2f16.nxv32i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 32 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv2f16_nxv32i8(<vscale x 2 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv2f16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv2f16.nxv32i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv2f16.nxv16i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i32>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv2f16.nxv16i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg3_nxv2f16_nxv16i32(<vscale x 2 x half> %val, half* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv2f16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv2f16.nxv16i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 16 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv2f16_nxv16i32(<vscale x 2 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv2f16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv2f16.nxv16i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv2f16.nxv2i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i16>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv2f16.nxv2i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg3_nxv2f16_nxv2i16(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv2f16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv2f16.nxv2i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv2f16_nxv2i16(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv2f16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv2f16.nxv2i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv2f16.nxv2i64(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i64>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv2f16.nxv2i64(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg3_nxv2f16_nxv2i64(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv2f16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei64.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv2f16.nxv2i64(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv2f16_nxv2i64(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv2f16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg3ei64.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv2f16.nxv2i64(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv2f16.nxv16i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i16>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv2f16.nxv16i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg4_nxv2f16_nxv16i16(<vscale x 2 x half> %val, half* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv2f16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv2f16.nxv16i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 16 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv2f16_nxv16i16(<vscale x 2 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv2f16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv2f16.nxv16i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv2f16.nxv32i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 32 x i16>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv2f16.nxv32i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 32 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg4_nxv2f16_nxv32i16(<vscale x 2 x half> %val, half* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv2f16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv2f16.nxv32i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 32 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv2f16_nxv32i16(<vscale x 2 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv2f16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv2f16.nxv32i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv2f16.nxv4i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i32>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv2f16.nxv4i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg4_nxv2f16_nxv4i32(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv2f16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv2f16.nxv4i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv2f16_nxv4i32(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv2f16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv2f16.nxv4i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv2f16.nxv16i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i8>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv2f16.nxv16i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg4_nxv2f16_nxv16i8(<vscale x 2 x half> %val, half* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv2f16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv2f16.nxv16i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 16 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv2f16_nxv16i8(<vscale x 2 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv2f16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv2f16.nxv16i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv2f16.nxv1i64(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv2f16.nxv1i64(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i64>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg4_nxv2f16_nxv1i64(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv2f16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei64.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv2f16.nxv1i64(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv2f16_nxv1i64(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv2f16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei64.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv2f16.nxv1i64(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv2f16.nxv1i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv2f16.nxv1i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg4_nxv2f16_nxv1i32(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv2f16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv2f16.nxv1i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv2f16_nxv1i32(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv2f16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv2f16.nxv1i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv2f16.nxv8i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i16>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv2f16.nxv8i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg4_nxv2f16_nxv8i16(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv2f16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv2f16.nxv8i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv2f16_nxv8i16(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv2f16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv2f16.nxv8i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv2f16.nxv4i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i8>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv2f16.nxv4i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg4_nxv2f16_nxv4i8(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv2f16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv2f16.nxv4i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv2f16_nxv4i8(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv2f16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv2f16.nxv4i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv2f16.nxv1i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv2f16.nxv1i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg4_nxv2f16_nxv1i16(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv2f16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv2f16.nxv1i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv2f16_nxv1i16(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv2f16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv2f16.nxv1i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv2f16.nxv2i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i32>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv2f16.nxv2i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg4_nxv2f16_nxv2i32(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv2f16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv2f16.nxv2i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv2f16_nxv2i32(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv2f16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv2f16.nxv2i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv2f16.nxv8i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i8>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv2f16.nxv8i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg4_nxv2f16_nxv8i8(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv2f16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv2f16.nxv8i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv2f16_nxv8i8(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv2f16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv2f16.nxv8i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv2f16.nxv4i64(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i64>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv2f16.nxv4i64(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i64>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg4_nxv2f16_nxv4i64(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv2f16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei64.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv2f16.nxv4i64(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv2f16_nxv4i64(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv2f16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei64.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv2f16.nxv4i64(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv2f16.nxv64i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 64 x i8>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv2f16.nxv64i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 64 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg4_nxv2f16_nxv64i8(<vscale x 2 x half> %val, half* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv2f16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv2f16.nxv64i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 64 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv2f16_nxv64i8(<vscale x 2 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv2f16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv2f16.nxv64i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv2f16.nxv4i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i16>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv2f16.nxv4i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg4_nxv2f16_nxv4i16(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv2f16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv2f16.nxv4i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv2f16_nxv4i16(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv2f16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv2f16.nxv4i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv2f16.nxv8i64(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i64>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv2f16.nxv8i64(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i64>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg4_nxv2f16_nxv8i64(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv2f16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei64.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv2f16.nxv8i64(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv2f16_nxv8i64(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv2f16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei64.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv2f16.nxv8i64(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv2f16.nxv1i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv2f16.nxv1i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg4_nxv2f16_nxv1i8(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv2f16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv2f16.nxv1i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv2f16_nxv1i8(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv2f16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv2f16.nxv1i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv2f16.nxv2i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i8>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv2f16.nxv2i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg4_nxv2f16_nxv2i8(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv2f16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv2f16.nxv2i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv2f16_nxv2i8(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv2f16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv2f16.nxv2i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv2f16.nxv8i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i32>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv2f16.nxv8i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg4_nxv2f16_nxv8i32(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv2f16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv2f16.nxv8i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv2f16_nxv8i32(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv2f16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv2f16.nxv8i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv2f16.nxv32i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 32 x i8>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv2f16.nxv32i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 32 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg4_nxv2f16_nxv32i8(<vscale x 2 x half> %val, half* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv2f16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv2f16.nxv32i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 32 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv2f16_nxv32i8(<vscale x 2 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv2f16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv2f16.nxv32i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv2f16.nxv16i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i32>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv2f16.nxv16i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg4_nxv2f16_nxv16i32(<vscale x 2 x half> %val, half* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv2f16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv2f16.nxv16i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 16 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv2f16_nxv16i32(<vscale x 2 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv2f16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv2f16.nxv16i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv2f16.nxv2i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i16>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv2f16.nxv2i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg4_nxv2f16_nxv2i16(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv2f16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv2f16.nxv2i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv2f16_nxv2i16(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv2f16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv2f16.nxv2i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv2f16.nxv2i64(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i64>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv2f16.nxv2i64(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg4_nxv2f16_nxv2i64(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv2f16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei64.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv2f16.nxv2i64(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv2f16_nxv2i64(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv2f16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg4ei64.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv2f16.nxv2i64(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv2f16.nxv16i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i16>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv2f16.nxv16i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg5_nxv2f16_nxv16i16(<vscale x 2 x half> %val, half* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv2f16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv2f16.nxv16i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 16 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv2f16_nxv16i16(<vscale x 2 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv2f16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv2f16.nxv16i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv2f16.nxv32i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 32 x i16>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv2f16.nxv32i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 32 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg5_nxv2f16_nxv32i16(<vscale x 2 x half> %val, half* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv2f16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv2f16.nxv32i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 32 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv2f16_nxv32i16(<vscale x 2 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv2f16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv2f16.nxv32i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv2f16.nxv4i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i32>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv2f16.nxv4i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg5_nxv2f16_nxv4i32(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv2f16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei32.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv2f16.nxv4i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv2f16_nxv4i32(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv2f16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei32.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv2f16.nxv4i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv2f16.nxv16i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i8>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv2f16.nxv16i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg5_nxv2f16_nxv16i8(<vscale x 2 x half> %val, half* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv2f16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv2f16.nxv16i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 16 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv2f16_nxv16i8(<vscale x 2 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv2f16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv2f16.nxv16i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv2f16.nxv1i64(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv2f16.nxv1i64(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i64>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg5_nxv2f16_nxv1i64(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv2f16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei64.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv2f16.nxv1i64(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv2f16_nxv1i64(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv2f16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei64.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv2f16.nxv1i64(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv2f16.nxv1i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv2f16.nxv1i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg5_nxv2f16_nxv1i32(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv2f16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv2f16.nxv1i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv2f16_nxv1i32(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv2f16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv2f16.nxv1i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv2f16.nxv8i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i16>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv2f16.nxv8i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg5_nxv2f16_nxv8i16(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv2f16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv2f16.nxv8i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv2f16_nxv8i16(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv2f16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv2f16.nxv8i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv2f16.nxv4i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i8>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv2f16.nxv4i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg5_nxv2f16_nxv4i8(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv2f16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv2f16.nxv4i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv2f16_nxv4i8(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv2f16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv2f16.nxv4i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv2f16.nxv1i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv2f16.nxv1i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg5_nxv2f16_nxv1i16(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv2f16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv2f16.nxv1i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv2f16_nxv1i16(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv2f16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv2f16.nxv1i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv2f16.nxv2i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i32>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv2f16.nxv2i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg5_nxv2f16_nxv2i32(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv2f16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv2f16.nxv2i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv2f16_nxv2i32(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv2f16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv2f16.nxv2i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv2f16.nxv8i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i8>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv2f16.nxv8i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg5_nxv2f16_nxv8i8(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv2f16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv2f16.nxv8i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv2f16_nxv8i8(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv2f16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv2f16.nxv8i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv2f16.nxv4i64(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i64>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv2f16.nxv4i64(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i64>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg5_nxv2f16_nxv4i64(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv2f16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei64.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv2f16.nxv4i64(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv2f16_nxv4i64(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv2f16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei64.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv2f16.nxv4i64(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv2f16.nxv64i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 64 x i8>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv2f16.nxv64i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 64 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg5_nxv2f16_nxv64i8(<vscale x 2 x half> %val, half* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv2f16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv2f16.nxv64i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 64 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv2f16_nxv64i8(<vscale x 2 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv2f16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv2f16.nxv64i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv2f16.nxv4i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i16>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv2f16.nxv4i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg5_nxv2f16_nxv4i16(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv2f16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv2f16.nxv4i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv2f16_nxv4i16(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv2f16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv2f16.nxv4i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv2f16.nxv8i64(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i64>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv2f16.nxv8i64(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i64>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg5_nxv2f16_nxv8i64(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv2f16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei64.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv2f16.nxv8i64(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv2f16_nxv8i64(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv2f16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei64.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv2f16.nxv8i64(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv2f16.nxv1i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv2f16.nxv1i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg5_nxv2f16_nxv1i8(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv2f16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv2f16.nxv1i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv2f16_nxv1i8(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv2f16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv2f16.nxv1i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv2f16.nxv2i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i8>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv2f16.nxv2i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg5_nxv2f16_nxv2i8(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv2f16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv2f16.nxv2i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv2f16_nxv2i8(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv2f16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv2f16.nxv2i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv2f16.nxv8i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i32>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv2f16.nxv8i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg5_nxv2f16_nxv8i32(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv2f16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei32.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv2f16.nxv8i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv2f16_nxv8i32(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv2f16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei32.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv2f16.nxv8i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv2f16.nxv32i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 32 x i8>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv2f16.nxv32i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 32 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg5_nxv2f16_nxv32i8(<vscale x 2 x half> %val, half* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv2f16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv2f16.nxv32i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 32 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv2f16_nxv32i8(<vscale x 2 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv2f16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei8.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv2f16.nxv32i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv2f16.nxv16i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i32>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv2f16.nxv16i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg5_nxv2f16_nxv16i32(<vscale x 2 x half> %val, half* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv2f16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei32.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv2f16.nxv16i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 16 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv2f16_nxv16i32(<vscale x 2 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv2f16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei32.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv2f16.nxv16i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv2f16.nxv2i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i16>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv2f16.nxv2i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg5_nxv2f16_nxv2i16(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv2f16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv2f16.nxv2i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv2f16_nxv2i16(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv2f16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv2f16.nxv2i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg5.nxv2f16.nxv2i64(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i64>, i64)
+declare void @llvm.riscv.vsxseg5.mask.nxv2f16.nxv2i64(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg5_nxv2f16_nxv2i64(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_nxv2f16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei64.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.nxv2f16.nxv2i64(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg5_mask_nxv2f16_nxv2i64(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg5_mask_nxv2f16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg5ei64.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg5.mask.nxv2f16.nxv2i64(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv2f16.nxv16i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i16>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv2f16.nxv16i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg6_nxv2f16_nxv16i16(<vscale x 2 x half> %val, half* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv2f16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv2f16.nxv16i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 16 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv2f16_nxv16i16(<vscale x 2 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv2f16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv2f16.nxv16i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv2f16.nxv32i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 32 x i16>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv2f16.nxv32i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 32 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg6_nxv2f16_nxv32i16(<vscale x 2 x half> %val, half* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv2f16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv2f16.nxv32i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 32 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv2f16_nxv32i16(<vscale x 2 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv2f16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv2f16.nxv32i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv2f16.nxv4i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i32>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv2f16.nxv4i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg6_nxv2f16_nxv4i32(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv2f16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei32.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv2f16.nxv4i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv2f16_nxv4i32(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv2f16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei32.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv2f16.nxv4i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv2f16.nxv16i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i8>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv2f16.nxv16i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg6_nxv2f16_nxv16i8(<vscale x 2 x half> %val, half* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv2f16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv2f16.nxv16i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 16 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv2f16_nxv16i8(<vscale x 2 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv2f16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv2f16.nxv16i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv2f16.nxv1i64(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv2f16.nxv1i64(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i64>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg6_nxv2f16_nxv1i64(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv2f16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei64.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv2f16.nxv1i64(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv2f16_nxv1i64(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv2f16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei64.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv2f16.nxv1i64(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv2f16.nxv1i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv2f16.nxv1i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg6_nxv2f16_nxv1i32(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv2f16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv2f16.nxv1i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv2f16_nxv1i32(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv2f16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv2f16.nxv1i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv2f16.nxv8i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i16>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv2f16.nxv8i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg6_nxv2f16_nxv8i16(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv2f16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv2f16.nxv8i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv2f16_nxv8i16(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv2f16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv2f16.nxv8i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv2f16.nxv4i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i8>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv2f16.nxv4i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg6_nxv2f16_nxv4i8(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv2f16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv2f16.nxv4i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv2f16_nxv4i8(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv2f16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv2f16.nxv4i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv2f16.nxv1i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv2f16.nxv1i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg6_nxv2f16_nxv1i16(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv2f16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv2f16.nxv1i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv2f16_nxv1i16(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv2f16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv2f16.nxv1i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv2f16.nxv2i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i32>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv2f16.nxv2i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg6_nxv2f16_nxv2i32(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv2f16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv2f16.nxv2i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv2f16_nxv2i32(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv2f16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv2f16.nxv2i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv2f16.nxv8i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i8>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv2f16.nxv8i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg6_nxv2f16_nxv8i8(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv2f16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv2f16.nxv8i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv2f16_nxv8i8(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv2f16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv2f16.nxv8i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv2f16.nxv4i64(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i64>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv2f16.nxv4i64(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i64>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg6_nxv2f16_nxv4i64(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv2f16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei64.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv2f16.nxv4i64(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv2f16_nxv4i64(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv2f16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei64.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv2f16.nxv4i64(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv2f16.nxv64i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 64 x i8>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv2f16.nxv64i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 64 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg6_nxv2f16_nxv64i8(<vscale x 2 x half> %val, half* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv2f16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv2f16.nxv64i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 64 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv2f16_nxv64i8(<vscale x 2 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv2f16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv2f16.nxv64i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv2f16.nxv4i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i16>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv2f16.nxv4i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg6_nxv2f16_nxv4i16(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv2f16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv2f16.nxv4i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv2f16_nxv4i16(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv2f16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv2f16.nxv4i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv2f16.nxv8i64(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i64>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv2f16.nxv8i64(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i64>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg6_nxv2f16_nxv8i64(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv2f16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei64.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv2f16.nxv8i64(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv2f16_nxv8i64(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv2f16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei64.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv2f16.nxv8i64(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv2f16.nxv1i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv2f16.nxv1i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg6_nxv2f16_nxv1i8(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv2f16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv2f16.nxv1i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv2f16_nxv1i8(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv2f16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv2f16.nxv1i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv2f16.nxv2i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i8>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv2f16.nxv2i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg6_nxv2f16_nxv2i8(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv2f16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv2f16.nxv2i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv2f16_nxv2i8(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv2f16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv2f16.nxv2i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv2f16.nxv8i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i32>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv2f16.nxv8i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg6_nxv2f16_nxv8i32(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv2f16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei32.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv2f16.nxv8i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv2f16_nxv8i32(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv2f16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei32.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv2f16.nxv8i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv2f16.nxv32i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 32 x i8>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv2f16.nxv32i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 32 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg6_nxv2f16_nxv32i8(<vscale x 2 x half> %val, half* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv2f16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv2f16.nxv32i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 32 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv2f16_nxv32i8(<vscale x 2 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv2f16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei8.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv2f16.nxv32i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv2f16.nxv16i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i32>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv2f16.nxv16i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg6_nxv2f16_nxv16i32(<vscale x 2 x half> %val, half* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv2f16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei32.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv2f16.nxv16i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 16 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv2f16_nxv16i32(<vscale x 2 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv2f16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei32.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv2f16.nxv16i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv2f16.nxv2i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i16>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv2f16.nxv2i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg6_nxv2f16_nxv2i16(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv2f16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv2f16.nxv2i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv2f16_nxv2i16(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv2f16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv2f16.nxv2i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg6.nxv2f16.nxv2i64(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i64>, i64)
+declare void @llvm.riscv.vsxseg6.mask.nxv2f16.nxv2i64(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg6_nxv2f16_nxv2i64(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_nxv2f16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei64.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.nxv2f16.nxv2i64(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg6_mask_nxv2f16_nxv2i64(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg6_mask_nxv2f16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg6ei64.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg6.mask.nxv2f16.nxv2i64(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv2f16.nxv16i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i16>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv2f16.nxv16i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg7_nxv2f16_nxv16i16(<vscale x 2 x half> %val, half* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv2f16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv2f16.nxv16i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 16 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv2f16_nxv16i16(<vscale x 2 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv2f16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv2f16.nxv16i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv2f16.nxv32i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 32 x i16>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv2f16.nxv32i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 32 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg7_nxv2f16_nxv32i16(<vscale x 2 x half> %val, half* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv2f16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv2f16.nxv32i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 32 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv2f16_nxv32i16(<vscale x 2 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv2f16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv2f16.nxv32i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv2f16.nxv4i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i32>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv2f16.nxv4i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg7_nxv2f16_nxv4i32(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv2f16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei32.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv2f16.nxv4i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv2f16_nxv4i32(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv2f16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei32.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv2f16.nxv4i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv2f16.nxv16i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i8>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv2f16.nxv16i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg7_nxv2f16_nxv16i8(<vscale x 2 x half> %val, half* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv2f16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv2f16.nxv16i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 16 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv2f16_nxv16i8(<vscale x 2 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv2f16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv2f16.nxv16i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv2f16.nxv1i64(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv2f16.nxv1i64(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i64>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg7_nxv2f16_nxv1i64(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv2f16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei64.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv2f16.nxv1i64(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv2f16_nxv1i64(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv2f16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei64.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv2f16.nxv1i64(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv2f16.nxv1i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv2f16.nxv1i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg7_nxv2f16_nxv1i32(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv2f16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv2f16.nxv1i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv2f16_nxv1i32(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv2f16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv2f16.nxv1i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv2f16.nxv8i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i16>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv2f16.nxv8i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg7_nxv2f16_nxv8i16(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv2f16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv2f16.nxv8i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv2f16_nxv8i16(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv2f16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv2f16.nxv8i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv2f16.nxv4i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i8>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv2f16.nxv4i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg7_nxv2f16_nxv4i8(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv2f16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv2f16.nxv4i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv2f16_nxv4i8(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv2f16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv2f16.nxv4i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv2f16.nxv1i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv2f16.nxv1i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg7_nxv2f16_nxv1i16(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv2f16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv2f16.nxv1i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv2f16_nxv1i16(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv2f16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv2f16.nxv1i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv2f16.nxv2i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i32>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv2f16.nxv2i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg7_nxv2f16_nxv2i32(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv2f16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv2f16.nxv2i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv2f16_nxv2i32(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv2f16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv2f16.nxv2i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv2f16.nxv8i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i8>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv2f16.nxv8i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg7_nxv2f16_nxv8i8(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv2f16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv2f16.nxv8i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv2f16_nxv8i8(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv2f16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv2f16.nxv8i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv2f16.nxv4i64(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i64>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv2f16.nxv4i64(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i64>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg7_nxv2f16_nxv4i64(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv2f16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei64.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv2f16.nxv4i64(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv2f16_nxv4i64(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv2f16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei64.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv2f16.nxv4i64(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv2f16.nxv64i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 64 x i8>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv2f16.nxv64i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 64 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg7_nxv2f16_nxv64i8(<vscale x 2 x half> %val, half* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv2f16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv2f16.nxv64i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 64 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv2f16_nxv64i8(<vscale x 2 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv2f16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv2f16.nxv64i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv2f16.nxv4i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i16>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv2f16.nxv4i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg7_nxv2f16_nxv4i16(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv2f16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv2f16.nxv4i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv2f16_nxv4i16(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv2f16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv2f16.nxv4i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv2f16.nxv8i64(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i64>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv2f16.nxv8i64(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i64>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg7_nxv2f16_nxv8i64(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv2f16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei64.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv2f16.nxv8i64(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv2f16_nxv8i64(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv2f16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei64.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv2f16.nxv8i64(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv2f16.nxv1i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv2f16.nxv1i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg7_nxv2f16_nxv1i8(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv2f16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv2f16.nxv1i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv2f16_nxv1i8(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv2f16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv2f16.nxv1i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv2f16.nxv2i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i8>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv2f16.nxv2i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg7_nxv2f16_nxv2i8(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv2f16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv2f16.nxv2i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv2f16_nxv2i8(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv2f16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv2f16.nxv2i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv2f16.nxv8i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i32>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv2f16.nxv8i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg7_nxv2f16_nxv8i32(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv2f16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei32.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv2f16.nxv8i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv2f16_nxv8i32(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv2f16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei32.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv2f16.nxv8i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv2f16.nxv32i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 32 x i8>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv2f16.nxv32i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 32 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg7_nxv2f16_nxv32i8(<vscale x 2 x half> %val, half* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv2f16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv2f16.nxv32i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 32 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv2f16_nxv32i8(<vscale x 2 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv2f16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei8.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv2f16.nxv32i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv2f16.nxv16i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i32>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv2f16.nxv16i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg7_nxv2f16_nxv16i32(<vscale x 2 x half> %val, half* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv2f16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei32.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv2f16.nxv16i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 16 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv2f16_nxv16i32(<vscale x 2 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv2f16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei32.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv2f16.nxv16i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv2f16.nxv2i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i16>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv2f16.nxv2i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg7_nxv2f16_nxv2i16(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv2f16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv2f16.nxv2i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv2f16_nxv2i16(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv2f16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv2f16.nxv2i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg7.nxv2f16.nxv2i64(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i64>, i64)
+declare void @llvm.riscv.vsxseg7.mask.nxv2f16.nxv2i64(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg7_nxv2f16_nxv2i64(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_nxv2f16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei64.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.nxv2f16.nxv2i64(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg7_mask_nxv2f16_nxv2i64(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg7_mask_nxv2f16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg7ei64.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg7.mask.nxv2f16.nxv2i64(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv2f16.nxv16i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i16>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv2f16.nxv16i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg8_nxv2f16_nxv16i16(<vscale x 2 x half> %val, half* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv2f16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv2f16.nxv16i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 16 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv2f16_nxv16i16(<vscale x 2 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv2f16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv2f16.nxv16i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 16 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv2f16.nxv32i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 32 x i16>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv2f16.nxv32i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 32 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg8_nxv2f16_nxv32i16(<vscale x 2 x half> %val, half* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv2f16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vmv1r.v v23, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv2f16.nxv32i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 32 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv2f16_nxv32i16(<vscale x 2 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv2f16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vmv1r.v v23, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv2f16.nxv32i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 32 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv2f16.nxv4i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i32>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv2f16.nxv4i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg8_nxv2f16_nxv4i32(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv2f16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei32.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv2f16.nxv4i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv2f16_nxv4i32(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv2f16_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei32.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv2f16.nxv4i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv2f16.nxv16i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i8>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv2f16.nxv16i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg8_nxv2f16_nxv16i8(<vscale x 2 x half> %val, half* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv2f16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv2f16.nxv16i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 16 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv2f16_nxv16i8(<vscale x 2 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv2f16_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv2f16.nxv16i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 16 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv2f16.nxv1i64(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv2f16.nxv1i64(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i64>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg8_nxv2f16_nxv1i64(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv2f16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei64.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv2f16.nxv1i64(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv2f16_nxv1i64(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv2f16_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei64.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv2f16.nxv1i64(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv2f16.nxv1i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv2f16.nxv1i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg8_nxv2f16_nxv1i32(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv2f16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv2f16.nxv1i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv2f16_nxv1i32(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv2f16_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv2f16.nxv1i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv2f16.nxv8i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i16>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv2f16.nxv8i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg8_nxv2f16_nxv8i16(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv2f16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv2f16.nxv8i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv2f16_nxv8i16(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv2f16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv2f16.nxv8i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv2f16.nxv4i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i8>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv2f16.nxv4i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg8_nxv2f16_nxv4i8(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv2f16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv2f16.nxv4i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv2f16_nxv4i8(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv2f16_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv2f16.nxv4i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv2f16.nxv1i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv2f16.nxv1i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg8_nxv2f16_nxv1i16(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv2f16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv2f16.nxv1i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv2f16_nxv1i16(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv2f16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv2f16.nxv1i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv2f16.nxv2i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i32>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv2f16.nxv2i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg8_nxv2f16_nxv2i32(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv2f16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei32.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv2f16.nxv2i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv2f16_nxv2i32(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv2f16_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei32.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv2f16.nxv2i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv2f16.nxv8i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i8>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv2f16.nxv8i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg8_nxv2f16_nxv8i8(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv2f16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv2f16.nxv8i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv2f16_nxv8i8(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv2f16_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv2f16.nxv8i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv2f16.nxv4i64(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i64>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv2f16.nxv4i64(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i64>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg8_nxv2f16_nxv4i64(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv2f16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei64.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv2f16.nxv4i64(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv2f16_nxv4i64(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv2f16_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei64.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv2f16.nxv4i64(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv2f16.nxv64i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 64 x i8>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv2f16.nxv64i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 64 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg8_nxv2f16_nxv64i8(<vscale x 2 x half> %val, half* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv2f16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vmv1r.v v23, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv2f16.nxv64i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 64 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv2f16_nxv64i8(<vscale x 2 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv2f16_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vmv1r.v v23, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv2f16.nxv64i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 64 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv2f16.nxv4i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i16>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv2f16.nxv4i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 4 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg8_nxv2f16_nxv4i16(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv2f16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv2f16.nxv4i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv2f16_nxv4i16(<vscale x 2 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv2f16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv2f16.nxv4i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 4 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv2f16.nxv8i64(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i64>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv2f16.nxv8i64(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i64>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg8_nxv2f16_nxv8i64(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv2f16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vmv1r.v v23, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei64.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv2f16.nxv8i64(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv2f16_nxv8i64(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv2f16_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vmv1r.v v23, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei64.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv2f16.nxv8i64(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv2f16.nxv1i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv2f16.nxv1i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 1 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg8_nxv2f16_nxv1i8(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv2f16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv2f16.nxv1i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv2f16_nxv1i8(<vscale x 2 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv2f16_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv2f16.nxv1i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 1 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv2f16.nxv2i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i8>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv2f16.nxv2i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg8_nxv2f16_nxv2i8(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv2f16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv2f16.nxv2i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv2f16_nxv2i8(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv2f16_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv2f16.nxv2i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv2f16.nxv8i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i32>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv2f16.nxv8i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 8 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg8_nxv2f16_nxv8i32(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv2f16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei32.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv2f16.nxv8i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv2f16_nxv8i32(<vscale x 2 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv2f16_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei32.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv2f16.nxv8i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 8 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv2f16.nxv32i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 32 x i8>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv2f16.nxv32i8(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 32 x i8>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg8_nxv2f16_nxv32i8(<vscale x 2 x half> %val, half* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv2f16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv2f16.nxv32i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 32 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv2f16_nxv32i8(<vscale x 2 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv2f16_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei8.v v1, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv2f16.nxv32i8(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 32 x i8> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv2f16.nxv16i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i32>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv2f16.nxv16i32(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 16 x i32>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg8_nxv2f16_nxv16i32(<vscale x 2 x half> %val, half* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv2f16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vmv1r.v v23, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei32.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv2f16.nxv16i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 16 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv2f16_nxv16i32(<vscale x 2 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv2f16_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16 killed $v16 def $v16_v17_v18_v19_v20_v21_v22_v23
+; CHECK-NEXT:    vmv1r.v v17, v16
+; CHECK-NEXT:    vmv1r.v v18, v16
+; CHECK-NEXT:    vmv1r.v v19, v16
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vmv1r.v v20, v16
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv1r.v v21, v16
+; CHECK-NEXT:    vmv1r.v v22, v16
+; CHECK-NEXT:    vmv1r.v v23, v16
+; CHECK-NEXT:    vsetvli a1, a2, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei32.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv2f16.nxv16i32(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 16 x i32> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv2f16.nxv2i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i16>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv2f16.nxv2i16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i16>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg8_nxv2f16_nxv2i16(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv2f16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v0, (a0), v17
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv2f16.nxv2i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv2f16_nxv2i16(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv2f16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei16.v v1, (a0), v17, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv2f16.nxv2i16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i16> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg8.nxv2f16.nxv2i64(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i64>, i64)
+declare void @llvm.riscv.vsxseg8.mask.nxv2f16.nxv2i64(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i64>, <vscale x 2 x i1>, i64)
+
+define void @test_vsxseg8_nxv2f16_nxv2i64(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_nxv2f16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v0, v16
+; CHECK-NEXT:    vmv1r.v v1, v0
+; CHECK-NEXT:    vmv1r.v v2, v0
+; CHECK-NEXT:    vmv1r.v v3, v0
+; CHECK-NEXT:    vmv1r.v v4, v0
+; CHECK-NEXT:    vmv1r.v v5, v0
+; CHECK-NEXT:    vmv1r.v v6, v0
+; CHECK-NEXT:    vmv1r.v v7, v0
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei64.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.nxv2f16.nxv2i64(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg8_mask_nxv2f16_nxv2i64(<vscale x 2 x half> %val, half* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg8_mask_nxv2f16_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v1, v16
+; CHECK-NEXT:    vmv1r.v v2, v1
+; CHECK-NEXT:    vmv1r.v v3, v1
+; CHECK-NEXT:    vmv1r.v v4, v1
+; CHECK-NEXT:    vmv1r.v v5, v1
+; CHECK-NEXT:    vmv1r.v v6, v1
+; CHECK-NEXT:    vmv1r.v v7, v1
+; CHECK-NEXT:    vmv1r.v v8, v1
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vsxseg8ei64.v v1, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg8.mask.nxv2f16.nxv2i64(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i64> %index, <vscale x 2 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv4f32.nxv16i16(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 16 x i16>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv4f32.nxv16i16(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 16 x i16>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg2_nxv4f32_nxv16i16(<vscale x 4 x float> %val, float* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv4f32_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv4f32.nxv16i16(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 16 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv4f32_nxv16i16(<vscale x 4 x float> %val, float* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv4f32_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv4f32.nxv16i16(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv4f32.nxv32i16(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 32 x i16>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv4f32.nxv32i16(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 32 x i16>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg2_nxv4f32_nxv32i16(<vscale x 4 x float> %val, float* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv4f32_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv4f32.nxv32i16(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 32 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv4f32_nxv32i16(<vscale x 4 x float> %val, float* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv4f32_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv4f32.nxv32i16(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv4f32.nxv4i32(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 4 x i32>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv4f32.nxv4i32(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 4 x i32>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg2_nxv4f32_nxv4i32(<vscale x 4 x float> %val, float* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv4f32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv2r.v v26, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v26
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv4f32.nxv4i32(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 4 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv4f32_nxv4i32(<vscale x 4 x float> %val, float* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv4f32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv2r.v v26, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v26, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv4f32.nxv4i32(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv4f32.nxv16i8(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 16 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv4f32.nxv16i8(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 16 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg2_nxv4f32_nxv16i8(<vscale x 4 x float> %val, float* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv4f32_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv2r.v v26, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v26
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv4f32.nxv16i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 16 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv4f32_nxv16i8(<vscale x 4 x float> %val, float* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv4f32_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv2r.v v26, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v26, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv4f32.nxv16i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv4f32.nxv1i64(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv4f32.nxv1i64(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 1 x i64>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg2_nxv4f32_nxv1i64(<vscale x 4 x float> %val, float* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv4f32_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv1r.v v25, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv4f32.nxv1i64(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 1 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv4f32_nxv1i64(<vscale x 4 x float> %val, float* %base, <vscale x 1 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv4f32_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv1r.v v25, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv4f32.nxv1i64(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 1 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv4f32.nxv1i32(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv4f32.nxv1i32(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 1 x i32>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg2_nxv4f32_nxv1i32(<vscale x 4 x float> %val, float* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv4f32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv1r.v v25, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv4f32.nxv1i32(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 1 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv4f32_nxv1i32(<vscale x 4 x float> %val, float* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv4f32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv1r.v v25, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv4f32.nxv1i32(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv4f32.nxv8i16(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 8 x i16>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv4f32.nxv8i16(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 8 x i16>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg2_nxv4f32_nxv8i16(<vscale x 4 x float> %val, float* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv4f32_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv2r.v v26, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v26
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv4f32.nxv8i16(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 8 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv4f32_nxv8i16(<vscale x 4 x float> %val, float* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv4f32_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv2r.v v26, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v26, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv4f32.nxv8i16(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv4f32.nxv4i8(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 4 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv4f32.nxv4i8(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 4 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg2_nxv4f32_nxv4i8(<vscale x 4 x float> %val, float* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv4f32_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv1r.v v25, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv4f32.nxv4i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 4 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv4f32_nxv4i8(<vscale x 4 x float> %val, float* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv4f32_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv1r.v v25, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv4f32.nxv4i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv4f32.nxv1i16(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv4f32.nxv1i16(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 1 x i16>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg2_nxv4f32_nxv1i16(<vscale x 4 x float> %val, float* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv4f32_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv1r.v v25, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv4f32.nxv1i16(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 1 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv4f32_nxv1i16(<vscale x 4 x float> %val, float* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv4f32_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv1r.v v25, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv4f32.nxv1i16(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv4f32.nxv2i32(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 2 x i32>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv4f32.nxv2i32(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 2 x i32>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg2_nxv4f32_nxv2i32(<vscale x 4 x float> %val, float* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv4f32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv1r.v v25, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv4f32.nxv2i32(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 2 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv4f32_nxv2i32(<vscale x 4 x float> %val, float* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv4f32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv1r.v v25, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv4f32.nxv2i32(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv4f32.nxv8i8(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 8 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv4f32.nxv8i8(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 8 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg2_nxv4f32_nxv8i8(<vscale x 4 x float> %val, float* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv4f32_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv1r.v v25, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv4f32.nxv8i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 8 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv4f32_nxv8i8(<vscale x 4 x float> %val, float* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv4f32_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv1r.v v25, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv4f32.nxv8i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv4f32.nxv4i64(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 4 x i64>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv4f32.nxv4i64(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 4 x i64>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg2_nxv4f32_nxv4i64(<vscale x 4 x float> %val, float* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv4f32_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv4f32.nxv4i64(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 4 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv4f32_nxv4i64(<vscale x 4 x float> %val, float* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv4f32_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv4f32.nxv4i64(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv4f32.nxv64i8(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 64 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv4f32.nxv64i8(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 64 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg2_nxv4f32_nxv64i8(<vscale x 4 x float> %val, float* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv4f32_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv4f32.nxv64i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 64 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv4f32_nxv64i8(<vscale x 4 x float> %val, float* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv4f32_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv4f32.nxv64i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv4f32.nxv4i16(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 4 x i16>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv4f32.nxv4i16(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 4 x i16>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg2_nxv4f32_nxv4i16(<vscale x 4 x float> %val, float* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv4f32_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv1r.v v25, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv4f32.nxv4i16(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 4 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv4f32_nxv4i16(<vscale x 4 x float> %val, float* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv4f32_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv1r.v v25, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv4f32.nxv4i16(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv4f32.nxv8i64(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 8 x i64>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv4f32.nxv8i64(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 8 x i64>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg2_nxv4f32_nxv8i64(<vscale x 4 x float> %val, float* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv4f32_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv4f32.nxv8i64(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 8 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv4f32_nxv8i64(<vscale x 4 x float> %val, float* %base, <vscale x 8 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv4f32_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv4f32.nxv8i64(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 8 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv4f32.nxv1i8(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv4f32.nxv1i8(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 1 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg2_nxv4f32_nxv1i8(<vscale x 4 x float> %val, float* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv4f32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv1r.v v25, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv4f32.nxv1i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 1 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv4f32_nxv1i8(<vscale x 4 x float> %val, float* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv4f32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv1r.v v25, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv4f32.nxv1i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv4f32.nxv2i8(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 2 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv4f32.nxv2i8(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 2 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg2_nxv4f32_nxv2i8(<vscale x 4 x float> %val, float* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv4f32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv1r.v v25, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv4f32.nxv2i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 2 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv4f32_nxv2i8(<vscale x 4 x float> %val, float* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv4f32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv1r.v v25, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv4f32.nxv2i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv4f32.nxv8i32(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 8 x i32>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv4f32.nxv8i32(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 8 x i32>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg2_nxv4f32_nxv8i32(<vscale x 4 x float> %val, float* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv4f32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv4f32.nxv8i32(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 8 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv4f32_nxv8i32(<vscale x 4 x float> %val, float* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv4f32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv4f32.nxv8i32(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv4f32.nxv32i8(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 32 x i8>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv4f32.nxv32i8(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 32 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg2_nxv4f32_nxv32i8(<vscale x 4 x float> %val, float* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv4f32_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv4f32.nxv32i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 32 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv4f32_nxv32i8(<vscale x 4 x float> %val, float* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv4f32_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei8.v v16, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv4f32.nxv32i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv4f32.nxv16i32(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 16 x i32>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv4f32.nxv16i32(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 16 x i32>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg2_nxv4f32_nxv16i32(<vscale x 4 x float> %val, float* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv4f32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv4f32.nxv16i32(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 16 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv4f32_nxv16i32(<vscale x 4 x float> %val, float* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv4f32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei32.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv4f32.nxv16i32(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv4f32.nxv2i16(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 2 x i16>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv4f32.nxv2i16(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 2 x i16>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg2_nxv4f32_nxv2i16(<vscale x 4 x float> %val, float* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv4f32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv1r.v v25, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v25
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv4f32.nxv2i16(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 2 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv4f32_nxv2i16(<vscale x 4 x float> %val, float* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv4f32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv1r.v v25, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei16.v v16, (a0), v25, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv4f32.nxv2i16(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg2.nxv4f32.nxv2i64(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 2 x i64>, i64)
+declare void @llvm.riscv.vsxseg2.mask.nxv4f32.nxv2i64(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 2 x i64>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg2_nxv4f32_nxv2i64(<vscale x 4 x float> %val, float* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_nxv4f32_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv2r.v v26, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v26
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.nxv4f32.nxv2i64(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 2 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg2_mask_nxv4f32_nxv2i64(<vscale x 4 x float> %val, float* %base, <vscale x 2 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg2_mask_nxv4f32_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 killed $v16m2_v18m2 def $v16m2_v18m2
+; CHECK-NEXT:    vmv2r.v v26, v18
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg2ei64.v v16, (a0), v26, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg2.mask.nxv4f32.nxv2i64(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 2 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv4f32.nxv16i16(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 16 x i16>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv4f32.nxv16i16(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 16 x i16>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg3_nxv4f32_nxv16i16(<vscale x 4 x float> %val, float* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv4f32_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv4f32.nxv16i16(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 16 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv4f32_nxv16i16(<vscale x 4 x float> %val, float* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv4f32_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v2, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv4f32.nxv16i16(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv4f32.nxv32i16(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 32 x i16>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv4f32.nxv32i16(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 32 x i16>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg3_nxv4f32_nxv32i16(<vscale x 4 x float> %val, float* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv4f32_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vmv2r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv4f32.nxv32i16(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 32 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv4f32_nxv32i16(<vscale x 4 x float> %val, float* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv4f32_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vmv2r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv4f32.nxv32i16(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv4f32.nxv4i32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 4 x i32>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv4f32.nxv4i32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 4 x i32>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg3_nxv4f32_nxv4i32(<vscale x 4 x float> %val, float* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv4f32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv4f32.nxv4i32(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 4 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv4f32_nxv4i32(<vscale x 4 x float> %val, float* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv4f32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv4f32.nxv4i32(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv4f32.nxv16i8(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 16 x i8>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv4f32.nxv16i8(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 16 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg3_nxv4f32_nxv16i8(<vscale x 4 x float> %val, float* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv4f32_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv4f32.nxv16i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 16 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv4f32_nxv16i8(<vscale x 4 x float> %val, float* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv4f32_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv4f32.nxv16i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv4f32.nxv1i64(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv4f32.nxv1i64(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 1 x i64>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg3_nxv4f32_nxv1i64(<vscale x 4 x float> %val, float* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv4f32_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei64.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv4f32.nxv1i64(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 1 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv4f32_nxv1i64(<vscale x 4 x float> %val, float* %base, <vscale x 1 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv4f32_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei64.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv4f32.nxv1i64(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 1 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv4f32.nxv1i32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv4f32.nxv1i32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 1 x i32>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg3_nxv4f32_nxv1i32(<vscale x 4 x float> %val, float* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv4f32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv4f32.nxv1i32(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 1 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv4f32_nxv1i32(<vscale x 4 x float> %val, float* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv4f32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv4f32.nxv1i32(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv4f32.nxv8i16(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 8 x i16>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv4f32.nxv8i16(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 8 x i16>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg3_nxv4f32_nxv8i16(<vscale x 4 x float> %val, float* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv4f32_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv4f32.nxv8i16(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 8 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv4f32_nxv8i16(<vscale x 4 x float> %val, float* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv4f32_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv4f32.nxv8i16(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv4f32.nxv4i8(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 4 x i8>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv4f32.nxv4i8(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 4 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg3_nxv4f32_nxv4i8(<vscale x 4 x float> %val, float* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv4f32_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv4f32.nxv4i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 4 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv4f32_nxv4i8(<vscale x 4 x float> %val, float* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv4f32_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv4f32.nxv4i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv4f32.nxv1i16(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv4f32.nxv1i16(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 1 x i16>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg3_nxv4f32_nxv1i16(<vscale x 4 x float> %val, float* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv4f32_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv4f32.nxv1i16(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 1 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv4f32_nxv1i16(<vscale x 4 x float> %val, float* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv4f32_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv4f32.nxv1i16(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv4f32.nxv2i32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 2 x i32>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv4f32.nxv2i32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 2 x i32>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg3_nxv4f32_nxv2i32(<vscale x 4 x float> %val, float* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv4f32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv4f32.nxv2i32(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 2 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv4f32_nxv2i32(<vscale x 4 x float> %val, float* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv4f32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv4f32.nxv2i32(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv4f32.nxv8i8(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 8 x i8>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv4f32.nxv8i8(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 8 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg3_nxv4f32_nxv8i8(<vscale x 4 x float> %val, float* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv4f32_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv4f32.nxv8i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 8 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv4f32_nxv8i8(<vscale x 4 x float> %val, float* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv4f32_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv4f32.nxv8i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv4f32.nxv4i64(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 4 x i64>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv4f32.nxv4i64(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 4 x i64>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg3_nxv4f32_nxv4i64(<vscale x 4 x float> %val, float* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv4f32_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei64.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv4f32.nxv4i64(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 4 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv4f32_nxv4i64(<vscale x 4 x float> %val, float* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv4f32_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei64.v v2, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv4f32.nxv4i64(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv4f32.nxv64i8(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 64 x i8>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv4f32.nxv64i8(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 64 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg3_nxv4f32_nxv64i8(<vscale x 4 x float> %val, float* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv4f32_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vmv2r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv4f32.nxv64i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 64 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv4f32_nxv64i8(<vscale x 4 x float> %val, float* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv4f32_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vmv2r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv4f32.nxv64i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv4f32.nxv4i16(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 4 x i16>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv4f32.nxv4i16(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 4 x i16>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg3_nxv4f32_nxv4i16(<vscale x 4 x float> %val, float* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv4f32_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv4f32.nxv4i16(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 4 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv4f32_nxv4i16(<vscale x 4 x float> %val, float* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv4f32_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv4f32.nxv4i16(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv4f32.nxv8i64(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 8 x i64>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv4f32.nxv8i64(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 8 x i64>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg3_nxv4f32_nxv8i64(<vscale x 4 x float> %val, float* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv4f32_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vmv2r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei64.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv4f32.nxv8i64(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 8 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv4f32_nxv8i64(<vscale x 4 x float> %val, float* %base, <vscale x 8 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv4f32_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vmv2r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei64.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv4f32.nxv8i64(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 8 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv4f32.nxv1i8(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv4f32.nxv1i8(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 1 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg3_nxv4f32_nxv1i8(<vscale x 4 x float> %val, float* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv4f32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv4f32.nxv1i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 1 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv4f32_nxv1i8(<vscale x 4 x float> %val, float* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv4f32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv4f32.nxv1i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv4f32.nxv2i8(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 2 x i8>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv4f32.nxv2i8(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 2 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg3_nxv4f32_nxv2i8(<vscale x 4 x float> %val, float* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv4f32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv4f32.nxv2i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 2 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv4f32_nxv2i8(<vscale x 4 x float> %val, float* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv4f32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv4f32.nxv2i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv4f32.nxv8i32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 8 x i32>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv4f32.nxv8i32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 8 x i32>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg3_nxv4f32_nxv8i32(<vscale x 4 x float> %val, float* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv4f32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv4f32.nxv8i32(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 8 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv4f32_nxv8i32(<vscale x 4 x float> %val, float* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv4f32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v2, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv4f32.nxv8i32(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv4f32.nxv32i8(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 32 x i8>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv4f32.nxv32i8(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 32 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg3_nxv4f32_nxv32i8(<vscale x 4 x float> %val, float* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv4f32_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv4f32.nxv32i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 32 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv4f32_nxv32i8(<vscale x 4 x float> %val, float* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv4f32_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei8.v v2, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv4f32.nxv32i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv4f32.nxv16i32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 16 x i32>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv4f32.nxv16i32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 16 x i32>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg3_nxv4f32_nxv16i32(<vscale x 4 x float> %val, float* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv4f32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vmv2r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv4f32.nxv16i32(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 16 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv4f32_nxv16i32(<vscale x 4 x float> %val, float* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv4f32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vmv2r.v v20, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei32.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv4f32.nxv16i32(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv4f32.nxv2i16(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 2 x i16>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv4f32.nxv2i16(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 2 x i16>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg3_nxv4f32_nxv2i16(<vscale x 4 x float> %val, float* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv4f32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv4f32.nxv2i16(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 2 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv4f32_nxv2i16(<vscale x 4 x float> %val, float* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv4f32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei16.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv4f32.nxv2i16(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg3.nxv4f32.nxv2i64(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 2 x i64>, i64)
+declare void @llvm.riscv.vsxseg3.mask.nxv4f32.nxv2i64(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 2 x i64>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg3_nxv4f32_nxv2i64(<vscale x 4 x float> %val, float* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_nxv4f32_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei64.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.nxv4f32.nxv2i64(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 2 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg3_mask_nxv4f32_nxv2i64(<vscale x 4 x float> %val, float* %base, <vscale x 2 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg3_mask_nxv4f32_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg3ei64.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg3.mask.nxv4f32.nxv2i64(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 2 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv4f32.nxv16i16(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 16 x i16>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv4f32.nxv16i16(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 16 x i16>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg4_nxv4f32_nxv16i16(<vscale x 4 x float> %val, float* %base, <vscale x 16 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv4f32_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vmv2r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv4f32.nxv16i16(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 16 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv4f32_nxv16i16(<vscale x 4 x float> %val, float* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv4f32_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v2, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv4f32.nxv16i16(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 16 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv4f32.nxv32i16(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 32 x i16>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv4f32.nxv32i16(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 32 x i16>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg4_nxv4f32_nxv32i16(<vscale x 4 x float> %val, float* %base, <vscale x 32 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv4f32_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2_v22m2
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vmv2r.v v20, v16
+; CHECK-NEXT:    vmv2r.v v22, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv4f32.nxv32i16(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 32 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv4f32_nxv32i16(<vscale x 4 x float> %val, float* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv4f32_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2_v22m2
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vmv2r.v v20, v16
+; CHECK-NEXT:    vmv2r.v v22, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv4f32.nxv32i16(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 32 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv4f32.nxv4i32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 4 x i32>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv4f32.nxv4i32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 4 x i32>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg4_nxv4f32_nxv4i32(<vscale x 4 x float> %val, float* %base, <vscale x 4 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv4f32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vmv2r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv4f32.nxv4i32(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 4 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv4f32_nxv4i32(<vscale x 4 x float> %val, float* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv4f32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv4f32.nxv4i32(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 4 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv4f32.nxv16i8(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 16 x i8>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv4f32.nxv16i8(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 16 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg4_nxv4f32_nxv16i8(<vscale x 4 x float> %val, float* %base, <vscale x 16 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv4f32_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vmv2r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv4f32.nxv16i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 16 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv4f32_nxv16i8(<vscale x 4 x float> %val, float* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv4f32_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv4f32.nxv16i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 16 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv4f32.nxv1i64(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 1 x i64>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv4f32.nxv1i64(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 1 x i64>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg4_nxv4f32_nxv1i64(<vscale x 4 x float> %val, float* %base, <vscale x 1 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv4f32_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vmv2r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei64.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv4f32.nxv1i64(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 1 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv4f32_nxv1i64(<vscale x 4 x float> %val, float* %base, <vscale x 1 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv4f32_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei64.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv4f32.nxv1i64(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 1 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv4f32.nxv1i32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 1 x i32>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv4f32.nxv1i32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 1 x i32>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg4_nxv4f32_nxv1i32(<vscale x 4 x float> %val, float* %base, <vscale x 1 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv4f32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vmv2r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv4f32.nxv1i32(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 1 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv4f32_nxv1i32(<vscale x 4 x float> %val, float* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv4f32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv4f32.nxv1i32(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 1 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv4f32.nxv8i16(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 8 x i16>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv4f32.nxv8i16(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 8 x i16>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg4_nxv4f32_nxv8i16(<vscale x 4 x float> %val, float* %base, <vscale x 8 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv4f32_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vmv2r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv4f32.nxv8i16(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 8 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv4f32_nxv8i16(<vscale x 4 x float> %val, float* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv4f32_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv4f32.nxv8i16(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 8 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv4f32.nxv4i8(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 4 x i8>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv4f32.nxv4i8(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 4 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg4_nxv4f32_nxv4i8(<vscale x 4 x float> %val, float* %base, <vscale x 4 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv4f32_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vmv2r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv4f32.nxv4i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 4 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv4f32_nxv4i8(<vscale x 4 x float> %val, float* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv4f32_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv4f32.nxv4i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 4 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv4f32.nxv1i16(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 1 x i16>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv4f32.nxv1i16(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 1 x i16>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg4_nxv4f32_nxv1i16(<vscale x 4 x float> %val, float* %base, <vscale x 1 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv4f32_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vmv2r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv4f32.nxv1i16(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 1 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv4f32_nxv1i16(<vscale x 4 x float> %val, float* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv4f32_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv4f32.nxv1i16(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 1 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv4f32.nxv2i32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 2 x i32>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv4f32.nxv2i32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 2 x i32>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg4_nxv4f32_nxv2i32(<vscale x 4 x float> %val, float* %base, <vscale x 2 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv4f32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vmv2r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv4f32.nxv2i32(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 2 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv4f32_nxv2i32(<vscale x 4 x float> %val, float* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv4f32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv4f32.nxv2i32(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 2 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv4f32.nxv8i8(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 8 x i8>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv4f32.nxv8i8(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 8 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg4_nxv4f32_nxv8i8(<vscale x 4 x float> %val, float* %base, <vscale x 8 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv4f32_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vmv2r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv4f32.nxv8i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 8 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv4f32_nxv8i8(<vscale x 4 x float> %val, float* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv4f32_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv4f32.nxv8i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 8 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv4f32.nxv4i64(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 4 x i64>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv4f32.nxv4i64(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 4 x i64>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg4_nxv4f32_nxv4i64(<vscale x 4 x float> %val, float* %base, <vscale x 4 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv4f32_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vmv2r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei64.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv4f32.nxv4i64(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 4 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv4f32_nxv4i64(<vscale x 4 x float> %val, float* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv4f32_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei64.v v2, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv4f32.nxv4i64(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv4f32.nxv64i8(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 64 x i8>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv4f32.nxv64i8(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 64 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg4_nxv4f32_nxv64i8(<vscale x 4 x float> %val, float* %base, <vscale x 64 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv4f32_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2_v22m2
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vmv2r.v v20, v16
+; CHECK-NEXT:    vmv2r.v v22, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv4f32.nxv64i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 64 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv4f32_nxv64i8(<vscale x 4 x float> %val, float* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv4f32_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2_v22m2
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vmv2r.v v20, v16
+; CHECK-NEXT:    vmv2r.v v22, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv4f32.nxv64i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 64 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv4f32.nxv4i16(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 4 x i16>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv4f32.nxv4i16(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 4 x i16>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg4_nxv4f32_nxv4i16(<vscale x 4 x float> %val, float* %base, <vscale x 4 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv4f32_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vmv2r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv4f32.nxv4i16(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 4 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv4f32_nxv4i16(<vscale x 4 x float> %val, float* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv4f32_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv4f32.nxv4i16(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 4 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv4f32.nxv8i64(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 8 x i64>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv4f32.nxv8i64(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 8 x i64>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg4_nxv4f32_nxv8i64(<vscale x 4 x float> %val, float* %base, <vscale x 8 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv4f32_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2_v22m2
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vmv2r.v v20, v16
+; CHECK-NEXT:    vmv2r.v v22, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei64.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv4f32.nxv8i64(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 8 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv4f32_nxv8i64(<vscale x 4 x float> %val, float* %base, <vscale x 8 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv4f32_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2_v22m2
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vmv2r.v v20, v16
+; CHECK-NEXT:    vmv2r.v v22, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei64.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv4f32.nxv8i64(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 8 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv4f32.nxv1i8(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 1 x i8>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv4f32.nxv1i8(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 1 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg4_nxv4f32_nxv1i8(<vscale x 4 x float> %val, float* %base, <vscale x 1 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv4f32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vmv2r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv4f32.nxv1i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 1 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv4f32_nxv1i8(<vscale x 4 x float> %val, float* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv4f32_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv4f32.nxv1i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 1 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv4f32.nxv2i8(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 2 x i8>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv4f32.nxv2i8(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 2 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg4_nxv4f32_nxv2i8(<vscale x 4 x float> %val, float* %base, <vscale x 2 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv4f32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vmv2r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv4f32.nxv2i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 2 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv4f32_nxv2i8(<vscale x 4 x float> %val, float* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv4f32_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv4f32.nxv2i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 2 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv4f32.nxv8i32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 8 x i32>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv4f32.nxv8i32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 8 x i32>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg4_nxv4f32_nxv8i32(<vscale x 4 x float> %val, float* %base, <vscale x 8 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv4f32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vmv2r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv4f32.nxv8i32(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 8 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv4f32_nxv8i32(<vscale x 4 x float> %val, float* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv4f32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v2, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv4f32.nxv8i32(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 8 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv4f32.nxv32i8(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 32 x i8>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv4f32.nxv32i8(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 32 x i8>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg4_nxv4f32_nxv32i8(<vscale x 4 x float> %val, float* %base, <vscale x 32 x i8> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv4f32_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vmv2r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v0, (a0), v20
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv4f32.nxv32i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 32 x i8> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv4f32_nxv32i8(<vscale x 4 x float> %val, float* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv4f32_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei8.v v2, (a0), v20, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv4f32.nxv32i8(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 32 x i8> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv4f32.nxv16i32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 16 x i32>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv4f32.nxv16i32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 16 x i32>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg4_nxv4f32_nxv16i32(<vscale x 4 x float> %val, float* %base, <vscale x 16 x i32> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv4f32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2_v22m2
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vmv2r.v v20, v16
+; CHECK-NEXT:    vmv2r.v v22, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v16, (a0), v8
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv4f32.nxv16i32(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 16 x i32> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv4f32_nxv16i32(<vscale x 4 x float> %val, float* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv4f32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    # kill: def $v16m2 killed $v16m2 def $v16m2_v18m2_v20m2_v22m2
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vmv2r.v v18, v16
+; CHECK-NEXT:    vmv2r.v v20, v16
+; CHECK-NEXT:    vmv2r.v v22, v16
+; CHECK-NEXT:    vsetvli a1, a2, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei32.v v16, (a0), v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv4f32.nxv16i32(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 16 x i32> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv4f32.nxv2i16(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 2 x i16>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv4f32.nxv2i16(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 2 x i16>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg4_nxv4f32_nxv2i16(<vscale x 4 x float> %val, float* %base, <vscale x 2 x i16> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv4f32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vmv2r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv4f32.nxv2i16(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 2 x i16> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv4f32_nxv2i16(<vscale x 4 x float> %val, float* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv4f32_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei16.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv4f32.nxv2i16(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 2 x i16> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+
+declare void @llvm.riscv.vsxseg4.nxv4f32.nxv2i64(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 2 x i64>, i64)
+declare void @llvm.riscv.vsxseg4.mask.nxv4f32.nxv2i64(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 2 x i64>, <vscale x 4 x i1>, i64)
+
+define void @test_vsxseg4_nxv4f32_nxv2i64(<vscale x 4 x float> %val, float* %base, <vscale x 2 x i64> %index, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_nxv4f32_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v0, v16
+; CHECK-NEXT:    vmv2r.v v2, v0
+; CHECK-NEXT:    vmv2r.v v4, v0
+; CHECK-NEXT:    vmv2r.v v6, v0
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei64.v v0, (a0), v18
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.nxv4f32.nxv2i64(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 2 x i64> %index, i64 %vl)
+  ret void
+}
+
+define void @test_vsxseg4_mask_nxv4f32_nxv2i64(<vscale x 4 x float> %val, float* %base, <vscale x 2 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl) {
+; CHECK-LABEL: test_vsxseg4_mask_nxv4f32_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv2r.v v2, v16
+; CHECK-NEXT:    vmv2r.v v4, v2
+; CHECK-NEXT:    vmv2r.v v6, v2
+; CHECK-NEXT:    vmv2r.v v8, v2
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vsxseg4ei64.v v2, (a0), v18, v0.t
+; CHECK-NEXT:    ret
+entry:
+  tail call void @llvm.riscv.vsxseg4.mask.nxv4f32.nxv2i64(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 2 x i64> %index, <vscale x 4 x i1> %mask, i64 %vl)
+  ret void
+}
+